Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.

Abstract: A method of processor-aided design of a workholding frame for a manufacturing process includes using a processor to perform operations including receiving, by a processor, first data representing a first three-dimensional (3D) model of an object to be manufactured. The operations further include obtaining, by the processor, second data describing a second 3D model. The second 3D model represents a bounding box having one or more sides adjoining a surface of the object within the first 3D model. The operations further include automatically generating, by the processor and based on the first data and the bounding box, third data indicating one or more parameters of the workholding frame. The workholding frame and the object are to be formed based on the one or more parameters and as a single workpiece from a blank material during a machining process associated with the object.

Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.

Abstract: Embodiments of the present disclosure provide an array substrate, a display device, a method for manufacturing an array substrate, a method for manufacturing a display device, and a spliced display device. The array substrate includes: a base substrate in which a through hole is provided; a filling portion disposed in the through hole, including a recessed structure and made from a flexible material; an electrically conductive pattern disposed on the filling portion and at least partially located in the recessed structure; and a film layer disposed on a side of the electrically conductive pattern facing away from the base substrate.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.

Abstract: A dye-sensitized solar cell includes: a transparent electrode; a power generation layer on the first main surface of the transparent electrode, including a semiconductor layer, a photosensitizing dye and an electrolyte layer; a counter electrode on the main surface of the power generation layer, having an electrode extraction region, wherein at least a part of the side surfaces of the counter electrode and at least a part of the side surfaces of the power generation layer are positioned coplanar, the electrode extraction region of the counter electrode overlaps with at least a part of the main surface of the power generation layer in a top view, and the side surfaces of the power generation layer are covered with a sealing layer formed extending from one of the transparent electrode and the counter electrode to the other.

Abstract: A semiconductor assembly includes a first wiring structure, a first semiconductor die and a first electronic element. The first wiring structure has a first surface. The first semiconductor die is disposed on the first surface of the first wiring structure. The first electronic element is electrically connected to the first wiring structure. The first electronic element includes a first metal layer, a second metal layer and a dielectric material interposed between the first metal layer and the second metal layer. The first metal layer and the second metal layer are substantially perpendicular to the first surface of the first wiring structure.

Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

Abstract: A semiconductor package using an insulating frame of various is disclosed. The insulating frame has a through hole therein, and the semiconductor chip is mounted in the through hole. Further, a via hole is provided in the periphery of the through hole, and a via contact filling the via hole is provided. Whereby the pad of the semiconductor chip is electrically connected to the via contact through the distribution layer. Further, an adhesive buffer layer for increasing the adhesive force is introduced into the upper portion of the insulating frame.

Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

Abstract: The disclosure concerns a semiconductor chip, which may be an interposer, having conductive through vias having a parallelepipedal shape.

Abstract: A printed circuit board includes a top conducting layer, an escaping layer, one or more first reference layers interposed between the top conducting layer and the escaping layer, and a second reference layer disposed under the escaping layer. The top conducting layer includes two connecting pads for receiving a pair of differential signals. A pair of vias are provided to extend vertically to penetrate the one or more first reference layers, the escaping layer, and the second reference layer. The vias connects the top conducting layer with the escaping layer. Each of the one or more first reference layers includes a continuous via void surrounding the pair of vias. The second reference layer includes two round via voids each surrounding one of the vias. The second reference layer includes a conductive film disposed between the two round via voids.

Abstract: A circuit board includes a core layer including a plurality of metal layers laminated one over another, a bottommost metal layer of the plurality of metal layers being thickest, and a topmost metal layer of the plurality of metal layer being thinnest; an upper insulating layer and an upper conductive pattern provided over a top surface of the core layer; and a lower insulating layer and a lower conductive pattern provided below a bottom surface of the core layer, wherein the topmost metal layer of the core metal layer is patterned to have a prescribed shaped section that serves as wiring and that is connected to the upper conductive pattern, wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the bottommost metal layer than in the topmost metal layer.

Abstract: A package structure includes a redistribution structure, a chip, an inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed over the redistribution structure. The inner conductive reinforcing element has a Young's modulus in a range of from 30 to 200 GPa. The protective layer covers the chip and a sidewall of an opening of the inner conductive reinforcing element.

Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

Abstract: A carrier substrate includes a core layer and at least one unit pattern portion, and the unit pattern portion includes a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, a second metal layer disposed on the release layer, and a third metal layer disposed on the second metal layer and covering side surfaces of the release layer, and a method of manufacturing a semiconductor package using the carrier substrate.

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.

Abstract: A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure.

Abstract: A linear image sensor includes first and second sensor chips, first and second substrates, a common support substrate, a support portion, a dam portion, and a sealing portion. The first sensor chip is mounted to partially protrude on one end side of the first substrate. The second sensor chip is mounted to partially protrude on one end side of the second substrate. The first and second substrates are mounted on the common support substrate. The support portion is provided in a gap between the end faces of the first and second substrates. The dam portion is provided annularly to surround the sensor chips. The sealing portion seals the sensor chips, in a region surrounded by the dam portion.

Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.

Abstract: A linear image sensor includes first and second sensor chips, first and second substrates, a common support substrate, a support portion, a dam portion, and a sealing portion. The first sensor chip is mounted to partially protrude on one end side of the first substrate. The second sensor chip is mounted to partially protrude on one end side of the second substrate. The first and second substrates are mounted on the common support substrate. The support portion is provided in a gap between the end faces of the first and second substrates. The dam portion is provided annularly to surround the sensor chips. The sealing portion seals the sensor chips, in a region surrounded by the dam portion.

Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

Abstract: A display device includes a flexible base layer including a first portion and a second portion disposed around the second portion; a display unit disposed on a first surface of the first portion and including a light emitting element; a driving circuit disposed on a first surface of the second portion and including a driving chip; a support member attached to a second surface of the first portion and a second surface of the second portion; and an adhesive member disposed between the flexible base layer and the support member, wherein the adhesive member includes a first adhesive member having a first elastic modulus and a second adhesive member having a second elastic modulus that is higher than the first elastic modulus, and the second adhesive member overlaps the driving circuit.

Abstract: A thin-film capacitor structure (50) is joined to an electrode pad surface (2S) of an area array integrated circuit (2) having a plurality of electrode pads (3G, 3P, 3S) arranged in an area array on the electrode pad surface (2S). The thin-film capacitor structure (50) includes a thin-film capacitor (10) including a first sheet electrode (11), a second sheet electrode (13), and a thin-film dielectric layer (12) formed between the first sheet electrode (11) and the second sheet electrode (12), a first insulating film (21), a second insulating film (22), and a plurality of through holes (30P, 30G, 30S). The plurality of through holes (30P, 30G, 30S) are bored from the first insulating film (21) to the second insulating film (22) through the thin-film capacitor (10) and formed in positions corresponding to the plurality of electrode pads (3G, 3P, 3S).

Abstract: A power module of double-faced cooling includes: an upper substrate; a lower substrate on which a plurality of semiconductor chips are disposed; and a first spacer disposed between the upper substrate and the lower substrate, electrically connecting the upper substrate and the lower substrate to each other, and disposed on the lower substrate to be equally distanced from each of the semiconductor chips. Power is supplied to the semiconductor chips on the lower substrate through the upper substrate and the first spacer.

Abstract: A circuit module (101) includes a substrate (1) having a principal surface (1a), a first component (6) mounted on the principal surface (1a), and a sealing resin portion (3) that covers at least a side surface of the first component (6) while covering the principal surface (1a). The first component (6) includes an empty portion (6c) and a connection portion (6b) exposed to the empty portion (6c). The sealing resin portion (3) is arranged to avoid at least a part of a region that is included in an upper surface of the first component (6) and corresponds to the empty portion (6c).

Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

Abstract: The present application discloses a packaging structure for a power module, comprising: a heat dissipation substrate; at least one first power device disposed on a first substrate having an insulating layer, the first substrate disposed on the heat dissipating substrate; and at least one second power device including a jumping electrode having a jumping potential, wherein the at least one second power device is disposed on at least one second substrate having an insulating layer, and the at least one second substrate is disposed on the first substrate, to reduce a parasitic capacitance between the jumping electrode and the heat dissipation substrate. The packaging structure for the power module according to the present application can reduce the parasitic capacitance between the jumping electrode of the power module and the heat dissipation substrate, thereby greatly reducing the EMI noise of the power module in operation.

Abstract: A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a continuous loop around upper edges of the walls; a sensitive component that is bonded within the cavity; and a non-magnetic lid that is sealed to the seal ring to close the cavity by a metallic seal.

Abstract: The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes. The protrusions extend from a body of encapsulant around the leadframe to couple to surface contacts on a substrate. The protrusions have a recess that is filled with encapsulant. Additionally, the protrusions may be part of the lead or may be a conductive layer on the lead. In some embodiments a die pad of the leadframe supporting a semiconductor die also has a protrusion on the underside of the leadframe. The protrusion on the die pad has a recess that houses an adhesive and at least part of the semiconductor die. The die pad with a protrusion may include anchor locks at the ends of the die pad to couple to the encapsulant.

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

Abstract: A method for manufacturing a chip component includes forming an element, which includes a plurality of element parts, on a substrate. A plurality of fuses are formed, for disconnectably connecting each of the plurality of element parts to an external connection electrode. The external connection electrode, which is arranged to provide external connection for the element, is formed by electroless plating on the substrate.

Abstract: A multi-layer device including device layers connected by an interposer. For example, an electronic display may include a light emitting diode (LED) layer including LEDs and a control circuitry layer to provide control signals to the LEDs. The electronic display further includes an interposer positioned between the LED layer and the control circuitry layer. The interposer includes a substrate and an array of conductive pillars extending through the substrate. The conductive pillars electrically connect the LED layer with the control circuitry layer. Bonding layers may be formed on the interposer and a corresponding side of a device layer to facilitate a hybrid bonding process that electrically connects contacts of the device layer to the conductive pillars and joins the bonding layers to attach the device layer to the interposer.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and internal electrodes with external electrodes disposed on one surface of the body, wherein the external electrodes include a first electrode layer disposed on one surface of the body, in contact with the internal electrodes, and including titanium nitride (TiN), and a second electrode layer disposed on the first electrode layer.

Abstract: A low temperature cofired ceramic substrate comprises a plurality of dielectric layers, at least one inner conductor layer, a plurality of bond pads, and a solder mask. The dielectric layers are formed from ceramic material and placed one on top of another to form a stack. The inner conductor is formed from electrically conductive paste and positioned on an upper surface of at least one inner dielectric layer. The bond pads are positioned on an outer surface of the stack. Each bond pad is formed from a plurality of conductive sublayers of thin film metal stacked one on top of another, with each conductive sublayer being formed from a different metal. The solder mask is positioned on the same outer surface of the stack as the bond pads and includes a plurality of openings, with each opening exposing at least a portion of one of the bond pads.

Abstract: A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.

Abstract: A power converter module includes an active metal braze (AMB) substrate, power converter circuitry, and a housing. The AMB substrate includes an aluminum nitride base layer, a first conductive layer on a first surface of the aluminum nitride base layer, and a second conductive layer on a second surface of the aluminum nitride base layer opposite the first surface. The power converter circuitry includes a number of silicon carbide switching components coupled to one another via the first conductive layer. The housing is over the power converter circuitry and the AMB substrate. By using an AMB substrate with an aluminum nitride base layer, the thermal dissipation characteristics of the power converter module may be substantially improved while maintaining the structural integrity of the power converter module.

Abstract: A composite structure is a stack of thinned substrates each having a plurality of active devices of the same or different technologies. An assembled carrier substrate includes die assembled into cavities formed on the carrier substrate such that when the die rest within the cavity, a gap is formed between a bottom surface of the die and a bottom surface of the cavity. This gap removes contact stress applied to the bottom of the die. Another gap can also be formed above the die. Either gap can be filled with a low-stress material. A yield improvement process functionally and physically partitions a conceptual large area die into an array of separate die modules of smaller area. The separate die modules are assembled into an array of cavities formed in a carrier substrate and interconnected to achieve a combined functionality equivalent to the functionality of the conceptual large area die.

Abstract: An electro-optical interconnection platform is provided. The platform includes an interface medium; a plurality of optical pads; a plurality of electrical pads; and at least one beam coupler adapted to optically couple at least one pair of optical pads of the plurality of optical pads, wherein the at least one pair of optical pads are placed on opposite sides of the interface medium.

Abstract: The method of chip packaging comprises: S1: providing a carrier, and forming an adhesive layer on a surface of the carrier; S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes corresponding to electrical leads of a semiconductor chip in the dielectric layer; S3: attaching the semiconductor chip with the front surface facing downwards to the surface of the first dielectric layer; S4: forming a plastic encapsulation layer covering the chip on the surface of the first dielectric layer; S5: separating the adhesive layer and the first dielectric layer to remove the carrier and the adhesive layer; and S6: forming a redistribution layer for the semiconductor chip based on the first dielectric layer and the first through holes.

Abstract: Techniques are disclosed for forming self-aligned transistor structures including two-dimensional electron gas (2DEG) source/drain tip portions or tips. In some cases, the 2DEG source/drain tips utilize polarization doping to enable ultra-short transistor channel lengths of less than 20 nm, for example, and create highly conductive, thin source/drain tip portions in transistor devices. In some instances, the 2DEG source/drain tips can be formed by self-aligned regrowth of a polarization layer over a base III-V compound layer and on either side of a dummy gate, in locations to be substantially covered by spacers. In some cases, the III-V base layer may include gallium nitride (GaN) or indium gallium nitride (InGaN), for example, and the polarization layer may include aluminum indium nitride (AlInN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), for example.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

Abstract: A printed circuit board with built-in vertical heat dissipation ceramic block, and an electrical assembly are disclosed. The electrical assembly includes the board and a plurality of electronic components. The printed circuit boards includes a dielectric material layer defining at least one through hole, at least one ceramic block corresponding to the through hole, at least one fixing portion for joining the ceramic block to the through hole of the dielectric material layer, a metal circuit layer provided on upper surfaces of the dielectric material layer and the ceramic block, and a high thermal conductivity layer provided on lower surfaces of the dielectric material layer and the ceramic block. The printed circuit board allows the location and size of the ceramic block to be modified according to requirements, so as to implement complicated circuit designs, achieve good effect of thermal conduction, control thermal conduction path, and reduce manufacturing cost.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.