Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.

Abstract: The disclosure relates to a microcrystal silicon thin film transistor; The transistor includes a substrate, a gate electrode formed on the substrate, an insulating film formed on the substrate, a non-doped microcrystal silicon film formed on the insulating film, and source and drain electrodes which are formed on the microcrystal film. In the transistor, there is provided an ohmic contact between the source and drain electrodes through the microcrystal silicon film. The insulating film optionally has an etched surface layer prepared by etching the insulating film which has been formed on the substrate, with an aqueous solution containing HF. The TFT can be produced in a simple manner with safety and with a simple equipment.

Abstract: A stress relaxation layer is inserted between an electrode layer and an antireflection layer to relax a stress imparted from one of the electrode and antireflection layers to the other. A semiconductor device is provided which can suppress separation of the antireflection film during device fabrication processes and dispense with the process of etching and removing the antireflection film.

Abstract: A substrate for a display device wherein a plurality of row electrode lines and a plurality of column electrode lines are arranged in a matrix form on a substrate; pixel electrodes and pixel-drive-TFTs each having a polycrystalline semiconductor channel are provided so as to correspond to each intersection of the row electrode lines and the column electrode lines; the pixel-drive-TFTs are arranged in a line-like form in the direction of row electrode line; row signals are supplied through the row electrode lines to the pixel-drive-TFTs; and column signals are supplied through the column electrode lines to the pixel-drive-TFTs; a plurality of row driver circuits for supplying row signals are formed on the substrate so as to correspond to each of the row electrode lines; each of the row driver circuits has row-drive-TFTs; the row-drive-TFT has a polycrystalline semiconductor channel; and the row-drive-TFT is arranged in a line-like form in the direction of row electrode line with respect to the pixel-drive-TFTs

Abstract: It is intended to provide a semiconductor circuit including thin-film transistors (TFTs) having a small leak current and TFTs capable of operating at high speed, and a method for manufacturing such a circuit. A material containing a catalyst element is selectively formed so as to be in close contact with an amorphous silicon film, or a catalyst element is selectively introduced into an amorphous silicon film. The amorphous silicon film thus processed is crystallized by illumination with laser light or strong light equivalent to it. A crystalline silicon area with a small amount of catalyst element is used for TFTs in a pixel circuit and a crystalline silicon area with a large amount of catalyst element is used for TFTs in peripheral circuits of an active matrix circuit.

Abstract: Amorphous silicon in impurity regions (source and drain regions or N-type or p-type regions) of TFT and TFD are crystallized and activated to lower electric resistance, by depositing film having a catalyst element such as nickel (Ni), iron (Fe), cobalt (Co) or platinum (Pt) on or beneath an amorphous silicon film, or introducing such a catalyst element into the amorphous silicon film by ion implantation and subsequently crystallizing the same by applying heat annealing at an appropriate temperature.

Abstract: A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors.

Abstract: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ monocrystals. Further, by connecting in parallel a plurality of such thin-film transistors it is possible to obtain characteristics which are effectively equivalent to those of a monocrystalline thin-film transistor in which the channel width has been increased.

Abstract: An integrated circuit includes: a) a semiconductor substrate; b) a first conductivity type substrate diffusion region within the semiconductor substrate, the first conductivity type substrate diffusion region being electrically conductive and having an outer first total area; c) a thin film polysilicon layer of the first conductivity type overlying and being in ohmic electrical connection with the substrate diffusion region; and d) a pillar of electrically conductive material extending outwardly from the thin film polysilicon layer over the electrically conductive diffusion region, the pillar having a total cross sectional second area where the pillar joins the thin film polysilicon layer, the second area being less than the outer first local area and being received entirely within the confines of the first area.

Abstract: A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.

Abstract: To form a silicide layer excellent in flatness, uniform in film thickness, and less in junction leak, by destroying the natural oxide film which adversely affects a formation of silicide layer of cobalt or nickel. A cobalt layer (7) is formed in a film thickness of 20 nm or less on an electrode layer (4A) of a gate electrode (4) and on source/drain diffusion layers (1, 2), and a nitrogen (8) is injected by the ion implantation at a density of about 1E15/cm.sup.3 with an injection energy of 10 keV or more. At this time, the nitrogens (8) destroy the natural oxide film existing in the interface of the cobalt layer (7) and electrode layer (4A), and in the interface of the cobalt layer (7) and the source/drain diffusion layers (1, 2), and distribute deeply into the electrode layer (4A) and the source/drain diffusion layers (1, 2). Later, by a silicide forming reaction of cobalt, a silicide layer (6) is formed. Since the natural oxide film does not exist, the silicide forming reaction proceeds uniformly.

Abstract: A semiconductor device using a crystalline semiconductor film is manufactured. The crystalline semiconductor film is formed by providing an amorphous silicon film with a catalyst metal for promoting a crystallization thereof and then heated for performing a thermal crystallization, following which the crystallized film is further exposed to a laser light for improving the crystallinity. The concentration of the catalyst metal in the semiconductor film and the location of the region to be added with the catalyst metal are so selected in order that a desired crystallinity and a desired crystal structure such as a vertical crystal growth or lateral crystal growth can be obtained. Further, active elements and driver elements of a circuit substrate for an active matrix type liquid crystal device are formed by such semiconductor devices having a desired crystallinity and crystal structure respectively.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector-base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.

Abstract: A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another.

Abstract: In a SRAM cell including two cross-coupled inverters having an input connected to a first node and an output connected to a second node, each inverter having a load TFT of a first conductivity type and a driving MOS transistor of a second conductivity type, a drain of each of the load TFT's is connected via a connection plug to the corresponding one of the first and second nodes.

Abstract: A method for forming an interconnect for establishing electrical communication with a semiconductor die is provided. The method includes: providing a microbump tape and then mounting the tape to a substrate with a compliant layer therebetween. The microbump tape includes an insulating film having a pattern of microbump contact members corresponding to a pattern of bond pads on the die. The compliant layer can be formed of a curable adhesive such as a silicone elastomer. A coupon containing a plurality of microbump tapes can be mounted to a substrate wafer which can then be singulated to form a plurality of interconnects. The interconnects can be used with a testing apparatus for testing unpackaged semiconductor dice.

Abstract: An integrated circuit arrangement comprising a pair of double-gated insulated-gate transistor devices connectible in series, the first transistor of the pair being biased by one of the gates of the device so as to be operable as a depletion-mode device whilst the second transistor of the pair is biased by one of its two gates so as to be operable as an enhancement-mode device. The separately-biasable gate electrode permits the threshold voltage of the transistors to be adjusted independently so that the device may operate as either a depletion-mode transistor or as an enhancement mode transistor.

Abstract: Reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The structure involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The structure provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The structure further allows process steps to be used that provide larger latitude in etching the contact opening and thereby provides a structure that is very manufacturable.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6').

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 .ANG. to 500 .ANG., and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 .mu.m.

Abstract: A thin film transistor includes a first active layer formed on a substrate; a gate electrode formed on a center portion of the first active layer and having a lower side connected to the center portion of the first active layer; a second active layer electrically connected to the first active layer and formed on lateral sides and on an upper side of the gate electrode; and impurity regions formed at opposing lateral sides of the gate electrode.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: Complementary circuits with inorganic n-channel thin film transistors (TFTs) and organic p-channel TFTs can exhibit advantageous properties, without being subject to some of the drawbacks of prior art complimentary inorganic TFTs or complementary organic TFTs. In preferred embodiments of the invention, the n-channel inorganic TFTs have an amorphous Si active layer, and the p-channel organic TFTs have .DELTA.-hexathienylene (.alpha.-6T) active layer. Complementary inverters according to the invention are disclosed, as is an exemplary processing sequence that can be used to manufacture integrated complementary inverters and other complementary circuits according to the invention.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: The absolute value of the threshold voltage of a P-channel TFT is reduced by making its channel length shorter than that of an N-channel TFT by at least 20%, to thereby approximately equalize the threshold voltage absolute values of those TFTs.

Abstract: A FET has comb-shaped electrode assemblies for source, drain and gate of the FET. Each of the source and drain electrode assemblies has a plurality of electrodes contacting the active region of the FET and formed as a first layer metal laminate, and a bus bar connecting the electrodes together to a corresponding pad and formed as a second layer metal laminate. The gate electrode layer has a plurality of gate electrodes contacting the active layer in Schottky contact, a gate bus bar connecting the gate electrodes together, a gate pad connected to the gate bus bar. The gate bus bar is formed as a first layer metal laminate intersecting the stem portion of the comb-shaped source bus bar. The two-layer metal structure of the FET reduces the number of photolithographic steps and thereby fabrication costs of the FET.

Abstract: Method of fabricating edgeless staggered type thin-film transistors (TFTs) substantially without producing steps on gate electrodes. This method is effective in reducing parasitic capacitance and isolating transistors from each other. A catalyst element such as nickel is added to regions corresponding to source/drain regions of TFTs, or a layer of the catalyst element or a layer of a compound of the catalyst element is formed. An intrinsic amorphous silicon film is formed either on the regions or on the layer of the catalyst element or its compound. The laminate is thermally annealed to diffuse the catalyst element into the amorphous silicon film. The amorphous silicon film is selectively crystallized around the source/drain regions. As a result, high-resistivity regions are produced in the other regions. No channel is created. The TFTs can be isolated from each other.

Abstract: A transistor comprising a P-type high concentration impurity diffusion layer which can also serve as an emitter for a parasitic PNP transistor wherein a layer of crystal defect obtained by ion implantation of inert impurity atoms or a compound thereof is arranged in the P-type high concentration impurity diffusion layer thereby decreasing the current amplification rate of the parasitic transistor.

Abstract: A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n.sup.+ gate PMOS devices and p.sup.+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n.sup.+ gate. The PMOS FET n.sup.+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n.sup.+ gate PMOS FET devices as well as for p.sup.+ gate NMOS FET devices.

Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

Abstract: A semiconductor device according to the invention includes a first conductivity type of driver transistor, a second conductivity type of load transistor formed on the driver transistor and an insulation layer formed between the driver transistor and the load transistor. The insulation layer is provided thereon with a depression area in which a channel region, a gate insulation layer and a gate electrode of the load transistor are formed.

Abstract: Amorphous silicon in impurity regions (source and drain regions or N-type or p-type regions) of TFT and TFD are crystallized and activated to lower electric resistance, by depositing film having a catalyst element such as nickel (Ni), iron (Fe), cobalt (Co) or platinum (Pt) on or beneath an amorphous silicon film, or introducing such a catalyst element into the amorphous silicon film by ion implantation and subsequently crystallizing the same by applying heat annealing at an appropriate temperature.

Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer.The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.

Abstract: An integrated circuit includes: a) a semiconductor substrate; b) a first conductivity type substrate diffusion region within the semiconductor substrate, the first conductivity type substrate diffusion region being electrically conductive and having an outer first total area; c) a thin film polysilicon layer of the first conductivity type overlying and being in ohmic electrical connection with the substrate diffusion region; and d) a pillar of electrically conductive material extending outwardly from the thin film polysilicon layer over the electrically conductive diffusion region, the pillar having a total cross sectional second area where the pillar joins the thin film polysilicon layer, the second area being less than the first area and being received entirely within the confines of the first area.

Abstract: A monolithic circuit comprises a plurality of thin film transistors. Source and drain regions of the TFT are provided with a metal silicide layer having a relatively low resistivity. Thereby, the effective distance between a gate and a source/drain electrode can be reduced.

Abstract: A combination of a lower thin film transistor formed on an insulating substrate and an upper thin film transistor laminated over the lower transistor has a lower channel formed in the lower transistor, an upper channel formed in the upper transistor, a lower gate electrode disposed under the lower channel, an intermediate gate electrode disposed between the lower channel and the upper channel, and an upper gate electrode disposed over the upper channel.

Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.

Abstract: This invention relates to the Thin Film Transistor having the self-aligned diffused source/drain regions for improving the ratio of on to off current and the method of fabricating the same.

Abstract: A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.

Abstract: A p-well region is formed in a main surface of a semiconductor substrate. A contact electrode is electrically connected to a predetermined n-type impurity region formed in a surface of the p-well region. A diffusion preventing layer is formed between the contact electrode and a drain region of a TFT. An interconnection layer is formed on the semiconductor substrate with an interlayer insulating film therebetween. A diffusion preventing layer is also formed between the interconnection layer and a source region of the TFT. Diffusion preventing layers are further formed between a channel region of the TFT and the source/drain regions of the TFT.

Abstract: A thin-film transistor of an inverted-staggered structure includes a semiconductor layer with a channel portion, a protective insulating film extending on the channel portion of the semiconductor layer, a source electrode, and a drain electrode. The protective insulating film has a rectangular shape with four corners, and each of two of the corners overlaps one of the source electrode and the drain electrode while two others of the corners overlap neither the source electrode nor the drain electrode. The thin-film transistor may be modified so that one of the corners overlaps one of the source electrode and the drain electrode while three others of the corners overlap neither the source electrode nor the drain electrode.

Abstract: A three dimensional latch and bulk silicon pass transistor for high density field reconfigurable architectures is provided utilizing bulk silicon with a layer of polysilicon or silicon on insulator (SOI) thereover. The pass transistor, which must have very low resistance to provide a good short circuit path between the metal runs and fast switching speed, is fabricated in the bulk silicon wherein the resistivity can be made very low relative to polysilicon and because only the pass transistor is disposed in the bulk silicon, thereby permitting the dimensions thereof to be increased to provide even lower resistance. Since only the latch is fabricated in the layer of polysilicon or SOI and is disposed over the pass transistor, the amount of chip area utilized can be the same or less than required in the prior art wherein all circuitry was in the bulk silicon.

Abstract: Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.

Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.