Field Effect Transistor In Single Crystal Material, Complementary To That In Non-single Crystal, Or Recrystallized, Material (e.g., Cmos) Patents (Class 257/69)
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Patent number: 6891192Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.Type: GrantFiled: August 4, 2003Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Oleg G. Gluschenkov, An L. Steegen, Haining S. Yang
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Patent number: 6885070Abstract: In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gate structure; and a second impurity region formed in the substrate on a second side of the gate structure, the second impurity region including: a third impurity region of the first conductive type, a fourth impurity region of the first conductive type between the third impurity region and the second side of the gate structure, and a halo ion region of a second conductive type formed adjacent to the fourth impurity region.Type: GrantFiled: September 30, 2002Date of Patent: April 26, 2005Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sang-Bai Yi, Jae-Min Yu, Sung-Chul Lee
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Patent number: 6881976Abstract: A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.Type: GrantFiled: November 6, 2003Date of Patent: April 19, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jia Zhen Zheng, Lap Chan, Shao-fu Sanford Chu
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Patent number: 6881653Abstract: A method of manufacturing a CMOS semiconductor device able to reduce the effective thickness of the gate insulating film and able to secure stable performance is provided. The method in one embodiment comprises the steps of: forming a polycrystalline silicon film on a gate insulating film; introducing an n-type impurity into the polycrystalline silicon film in an nMOS formation region before gate processing of the polycrystalline silicon film; performing heat treatment so that the impurity diffuses in the polycrystalline silicon film and is activated; and patterning the polycrystalline silicon to form a gate pattern before introducing an impurity into the polycrystalline silicon film at a pMOS formation region.Type: GrantFiled: December 22, 2003Date of Patent: April 19, 2005Assignee: Fujitsu LimitedInventors: Manabu Kojima, Kenichi Goto, Hiroshi Morioka, Kenichi Okabe
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Patent number: 6878968Abstract: A metallic element is effectively removed from a semiconductor film crystallized by using the metallic element. The concentration distribution of phosphorous or antimony in the depth direction of at least one of a source and a drain of a TFT semiconductor film has: a region in which the concentration is 1×1020 atoms/cm3 or less is 5 nm or greater in thickness, and 5×1019 atoms/cm3 or greater in the maximum value. By creating this concentration distribution, and by thermal annealing at about between 500 and 650° C., the metallic element within a channel forming region diffuses to the source or the drain, and at the same time as gettering is accomplished, the region in which the concentration is 1×1020 atoms/cm3 or less is made into a nucleus and the source region/drain region is recrystallized.Type: GrantFiled: May 9, 2000Date of Patent: April 12, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hideto Ohnuma
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Patent number: 6875999Abstract: The absolute value of the threshold voltage of a P-channel TFT is reduced by making its channel length shorter than that of an N-channel TFT by at least 20% to thereby approximately equalize the threshold voltage absolute values of those TFTs.Type: GrantFiled: November 18, 2002Date of Patent: April 5, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Yasuhiko Takemura
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Patent number: 6861710Abstract: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is formed on the TFT from an inorganic material and serves as a first insulating film, an organic insulating film is formed on the first insulating film from an organic material and serves as a second insulating film, and an inorganic insulating film is formed on the second insulating film from an inorganic material and serves as a third insulating film. Thus obtained is a structure for preventing the second insulating film from releasing moisture and oxygen. In order to avoid defect in forming the film, a portion of the third insulating film where a contact hole is formed is removed alone.Type: GrantFiled: December 27, 2002Date of Patent: March 1, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Toru Takayama, Kengo Akimoto
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Patent number: 6847075Abstract: A semiconductor integrated circuit apparatus having a planar capacitor can use a plurality of source voltages therein. According to the semiconductor integrated circuit apparatus, it is possible to not only control thresholds of individual MOS transistors but also reduce the threshold voltage of the planar capacitor without any additional fabrication process. The semiconductor integrated circuit apparatus includes a p-channel memory transistor and a capacitor in a first n-type element region, an n-channel low-voltage MOS transistor in a second p-type element region, and an n-channel high-voltage MOS transistor in a third p-type element region. A channel region of the second MOS transistor is doped under a high density profile by using a p-type impurity element. At the same time, the p-type impurity element is imported in a capacitor region of the first element region under the substantially same profile.Type: GrantFiled: June 3, 2003Date of Patent: January 25, 2005Assignee: Fujitsu LimitedInventor: Toru Anezaki
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Patent number: 6841797Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.Type: GrantFiled: January 8, 2003Date of Patent: January 11, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
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Patent number: 6835586Abstract: Providing a semiconductor device with a TFT structure with high reliability In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 107a is provided in an n-channel TFT. The LDD regions 113 overlaps the first wiring line 102a and does not overlap the second wiring line 107a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.Type: GrantFiled: April 19, 2001Date of Patent: December 28, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Patent number: 6825495Abstract: A CMOS transistor is described. The CMOS transistor comprises a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a gate, a channel region, a first doped region of the first conductivity type and a source region, wherein the channel region, the first doped region and the source region are arranged along a first direction. The second TFT includes a gate, a channel region, a second doped region of the second conductivity type and a drain region, wherein the channel region, the second doped region and the drain region are arranged along the first direction. The first and the second doped regions are arranged along a second direction that is perpendicular to the first direction, and are electrically connected by a conductive line extending along the second direction.Type: GrantFiled: September 1, 2003Date of Patent: November 30, 2004Assignee: Au Optronics CorporationInventors: Jen-Yi Hu, Wein-Town Sun
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Patent number: 6825534Abstract: A semiconductor device includes a combination substrate having a bulk silicon region, and a silicon-on-insulator (SOI) region. The SOI region includes a crystallized silicon layer formed by annealing amorphous silicon and having isolation trenches formed therein so as to remove defective regions, and isolation oxides formed in the isolation trenches.Type: GrantFiled: December 27, 2000Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Howard H. Chen, Louis L. Hsu, Li-Kong Wang
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Patent number: 6822262Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.Type: GrantFiled: November 18, 2002Date of Patent: November 23, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
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Publication number: 20040227137Abstract: A CMOS transistor is described. The CMOS transistor comprises a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a gate, a channel region, a first doped region of the first conductivity type and a source region, wherein the channel region, the first doped region and the source region are arranged along a first direction. The second TFT includes a gate, a channel region, a second doped region of the second conductivity type and a drain region, wherein the channel region, the second doped region and the drain region are arranged along the first direction. The first and the second doped regions are arranged along a second direction that is perpendicular to the first direction, and are electrically connected by a conductive line extending along the second direction.Type: ApplicationFiled: September 1, 2003Publication date: November 18, 2004Inventors: Jen-Yi Hu, Wein-Town Sun
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Publication number: 20040222422Abstract: A CMOS circuit such as an inverter or latch is disclosed where transistors used in the circuit are interconnected using a connector disposed intermediate, and operatively connecting, a gate of a first transistor forming region and a gate of a second transistor forming region, the connector generally defining a Z-shape. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: May 8, 2003Publication date: November 11, 2004Inventors: Wein-Town Sun, Hu Jen-Yi
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Patent number: 6812492Abstract: The present invention relates to a method of fabricating a lightly-doped drain (“LDD”) thin film transistor of a coplanar type wherein the transistor has an LDD region of uniform resistance formed by locating a peak point of dopant in an active layer covered with an insulating layer wherein the dopant is very lightly distributed. The present invention further includes the steps of forming an active layer on an insulated substrate, forming an insulating layer covering the active layer, forming a gate electrode on the insulating layer over the active layer, doping lightly the active layer as a target with impurities, forming a gate insulating layer by patterning the insulating layer to be extended out of the gate electrode, and forming a source region and a drain region in portions of the active layer which are exposed by the step of forming the gate insulating layer.Type: GrantFiled: December 4, 1998Date of Patent: November 2, 2004Assignee: LG Philips LCD Co., Ltd.Inventor: Dong-Wook Choi
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Patent number: 6812493Abstract: The present invention provides a thin film semiconductor element which is small in area with high on-current enough to be suitable for the power saving, miniaturization, and high definition display of a device. According to the present invention, an outer shape of a semiconductor thin film is processed and regions (a channel region, a source region, and a drain region) in the semiconductor thin film are formed by using, as masks, other element components such as a gate electrode. Specifically, ion-implanted regions are formed by implanting impurity ions into predetermined regions of the semiconductor thin film using, as a mask, the gate electrode overlapped on the thin film via an insulation film. Thereafter, the semiconductor is processed into a predetermined shape by etching using, as masks, previously formed element components such as the gate electrode.Type: GrantFiled: October 4, 2002Date of Patent: November 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Mikio Nishio
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Patent number: 6812111Abstract: In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a height of the notch region of the gate electrode may be readily adjusted and controlled.Type: GrantFiled: November 12, 2002Date of Patent: November 2, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Kong-Soo Cheong, Hee-Sung Kang
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Patent number: 6809339Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.Type: GrantFiled: December 29, 2003Date of Patent: October 26, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideomi Suzawa, Koji Ono, Toru Takayama
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Publication number: 20040195569Abstract: A device manufacturing method, including: a first process for providing the plural elements on the original substrate via a separation layer in a condition where terminal sections are exposed to a surface on an opposite side to the separation layer; a second process for adhering the surface where the terminal sections of the elements to be transferred on the original substrate are exposed, via conductive adhesive, to a surface of the final substrate on a side where conductive sections for conducting with the terminal sections of the elements are provided; a third process for producing exfoliation in the separation layer between the original substrate and the final substrate; and a fourth process for separating the original substrate from which the transfer of elements has been completed, from the final substrate.Type: ApplicationFiled: January 14, 2004Publication date: October 7, 2004Applicant: SEIKO EPSON CORPORATIONInventors: Takashi Hashimoto, Atsushi Takakuwa, Tomoyuki Kamakura, Sumio Utsunomiya
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Patent number: 6800874Abstract: A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.Type: GrantFiled: October 31, 2003Date of Patent: October 5, 2004Assignee: Hannstar Display Corp.Inventor: In-Cha Hsieh
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Publication number: 20040180489Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.Type: ApplicationFiled: March 26, 2004Publication date: September 16, 2004Applicant: Hynix Semiconductor Inc.Inventors: Yong-Sun Sohn, Chang-Woo Ryoo, Jeong-Youb Lee
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Publication number: 20040173798Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is influenced into the void and strained. In various embodiments, the naturally-occurring Van der Waal's force is sufficient to influence the film into the void. In various embodiments, a nano-imprint mask is used to assist with influencing the film into the void. In various embodiments, an oxide region is formed in a silicon substrate, and a single crystalline silicon film is formed on the semiconductor substrate and on at least a portion of the oxide region. The oxide region is removed allowing the Van der Waal's force to bond the film to the silicon substrate. Other aspects are provided herein.Type: ApplicationFiled: March 5, 2003Publication date: September 9, 2004Applicant: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 6784454Abstract: The number of TFT (20), thin film transistors for controlling the supplied power to an element to be driven such as an organic EL element (50) which operates based on the supplied power, provided between the element to be driven and a power supply line VL, is equal to n, where n is an integer greater than or equal to two. The n TFTs (20) and corresponding element to be driven (50) are electrically connected by contact points, the number of which is less than or equal to (n−1). It is possible to improve the reliability as a semiconductor device and a display device, and, at the same time, to secure maximum actual operation region (illumination region for an illuminating element) of the element to be driven.Type: GrantFiled: September 28, 2001Date of Patent: August 31, 2004Assignee: Sanyo Electric Co., Ltd.Inventor: Katsuya Anzai
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Publication number: 20040144979Abstract: The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a semiconductor-on-insulator thin film transistor construction, and can be formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The thin film of semiconductor material can comprise both silicon and germanium. Further, the thin film can contain two different layers. A first of the two layers can have silicon and germanium present in a relaxed crystalline lattice, and a second of the two layers can be a strained crystalline lattice of either silicon alone, or silicon in combination with germanium. The invention also includes computer systems utilizing such CMOS inverters.Type: ApplicationFiled: January 14, 2004Publication date: July 29, 2004Inventor: Arup Bhattacharyya
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Publication number: 20040144980Abstract: A metal oxynitride layer formed by atomic layer deposition of a plurality of reacted monolayers, the monolayers comprising at least one each of a metal, an oxide and a nitride. The metal oxynitride layer is formed from zirconium oxynitride, hafnium oxynitride, tantalum oxynitride, or mixtures thereof. The metal oxynitride layer is used in gate dielectrics as a replacement material for silicon dioxide. A semiconductor device structure having a gate dielectric formed from a metal oxynitride layer is also disclosed.Type: ApplicationFiled: January 27, 2003Publication date: July 29, 2004Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20040144981Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.Type: ApplicationFiled: August 28, 2003Publication date: July 29, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Hun Seo, Seung-Hyun Park, Han-Sin Lee, Moo-Sung Kim, Won-Suk Yang
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Patent number: 6765272Abstract: A semiconductor device has a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween; a LDD structure in which, on either side of said gate electrode, there are formed a LDD region and a source/drain region; an interlayer insulating film to cover said gate electrode as well as said LDD regions; and contact sections. A contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying thereunder; and a contact section connecting to the other side of the source/drain region having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying thereunder.Type: GrantFiled: April 25, 2002Date of Patent: July 20, 2004Assignee: NEC Electronics CorporationInventor: Hidetaka Natsume
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Patent number: 6762469Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: GrantFiled: April 19, 2002Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Publication number: 20040065884Abstract: The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a semiconductor-on-insulator thin film transistor construction, and can be formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The thin film of semiconductor material can comprise both silicon and germanium. Further, the thin film can contain two different layers. A first of the two layers can have silicon and germanium present in a relaxed crystalline lattice, and a second of the two layers can be a strained crystalline lattice of either silicon alone, or silicon in combination with germanium. The invention also includes computer systems utilizing such CMOS inverters.Type: ApplicationFiled: October 3, 2002Publication date: April 8, 2004Inventor: Arup Bhattacharyya
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Patent number: 6717180Abstract: A semiconductor device which is excellent in reliability and electrical characteristics. The semiconductor device is formed on an insulating substrate. A channel region is formed between a source and a drain by the voltage applied to a gate electrode. The channel region, the source, and the drain are fabricated from a semiconductor having a large mobility. The other regions including the portion located under the channel region are fabricated from a semiconductor having a small mobility.Type: GrantFiled: January 23, 2002Date of Patent: April 6, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura
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Patent number: 6713819Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.Type: GrantFiled: April 8, 2002Date of Patent: March 30, 2004Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Dong-Hyuk Ju, Srinath Krishnan
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Publication number: 20040058490Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.Type: ApplicationFiled: April 24, 2003Publication date: March 25, 2004Applicant: SEIKO INSTRUMENTS INC.Inventor: Kazutoshi Ishii
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Patent number: 6710371Abstract: There is provided a semiconductor integrated circuit device wherein functional circuit groups are arranged on a chip in a direction spreads, which aims to enhance layout efficiency and to prevent deterioration of element characteristics. A unit wiring region IL1P is constituted outside of a power voltage wiring VCC, a part of a second region BIP and a unit wiring region IL1N is constituted outside of a reference voltage wiring VSS, a part of a second region BIN. Within the second wiring regions BIP and BIN, connection wirings 11, 12A, 13, 14 are wired. These connection wirings connect between units within the logic circuits CIA11, CIR12 or between the logic circuits CIR11, CIR12. There is only arranged an input/output wiring region IOL1 on a first region A1 located between the power voltage wiring VCC1 and the reference voltage wiring VSS1. Since no unit wiring region exists in the first region A1, width of the first region A1 can be laid-out short.Type: GrantFiled: January 9, 2002Date of Patent: March 23, 2004Assignee: Fujitsu LimitedInventors: Terumasa Kitahara, Koichi Yasuda
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Patent number: 6709912Abstract: A method for forming a dual Si—Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Si—Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Si—Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration.Type: GrantFiled: October 8, 2002Date of Patent: March 23, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew-Hoe Ang, Jeffrey Chee Wei-Lun, Wenhe Lin, Jia Zhen Zheng
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Patent number: 6700133Abstract: A film having a high thermal conductivity material such as aluminum nitride is formed on a substrate, and then a silicon film is formed. When a laser light or an intense light corresponding to the laser light is irradiated to the silicon film, since the aluminum nitride film absorbs heat, a portion of the silicon film near the aluminum nitride film is solidified immediately. However, since a solidifying speed is slow in another portion of the silicon film, crystallization progresses from the portion near the aluminum nitride film. When a substrate temperature is 400° C. or higher at laser irradiation, since a solidifying speed is decreased, a crystallinity of the silicon film is increased. Also, when the substrate is thin, the crystallinity of the silicon film is increased.Type: GrantFiled: September 18, 2000Date of Patent: March 2, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Yasuhiko Takemura, Akiharu Miyanaga, Shunpei Yamazaki
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Publication number: 20040023449Abstract: A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.Type: ApplicationFiled: July 31, 2003Publication date: February 5, 2004Applicant: International Business Machines CorporationInventors: Louis L. Hsu, Jack Allan Mandelman, William Robert Tonti, Li-Kong Wang
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Patent number: 6682966Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.Type: GrantFiled: June 17, 2002Date of Patent: January 27, 2004Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Seizo Kakimoto, Masayuki Nakano, Kouichiro Adachi
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Patent number: 6677612Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type and p-type) on a substrate. An isolation material layer is formed abutting the first activated area. A second doped and activated polysilicon area of opposite conductivity type from the first activated area is formed adjacent to the isolation material layer. The second activated opposite area has a height that does not exceed that of the first doped and activated polysilicon layer. Further processing may be effected to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in previously existing methods.Type: GrantFiled: August 28, 2001Date of Patent: January 13, 2004Assignee: Micron Technology, Inc.Inventor: Salman Akram
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Patent number: 6670635Abstract: A semiconductor device includes a control circuit for carrying out gamma correction of a supplied signal, and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs, and are integrally formed on the same insulating substrate. A semiconductor display device includes a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a picture signal supply source for supplying a picture signal; a control circuit for carrying out gamma correction of the picture signal; and a memory for storing data used in the gamma correction of the picture signal. The plurality of TFTs, the driver, the control circuit, and the memory are integrally formed on the same insulating substrate.Type: GrantFiled: March 31, 2000Date of Patent: December 30, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
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Patent number: 6667902Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.Type: GrantFiled: December 17, 2001Date of Patent: December 23, 2003Assignee: Kilopass Technologies, Inc.Inventor: Jack Zezhong Peng
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Patent number: 6661063Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.Type: GrantFiled: March 2, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Kenichi Kikushima, Fumio Ootsuka, Kazushige Sato
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Patent number: 6657229Abstract: A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.Type: GrantFiled: August 24, 1999Date of Patent: December 2, 2003Assignee: United Microelectronics CorporationInventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
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Patent number: 6653657Abstract: To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.Type: GrantFiled: December 11, 2000Date of Patent: November 25, 2003Assignee: Semoconductor Energy Laboratory Co., Ltd.Inventors: Ritsuko Kawasaki, Kenji Kasahara, Hisashi Ohtani
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Patent number: 6649935Abstract: A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.Type: GrantFiled: February 28, 2001Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Jack Allan Mandelman, William Robert Tonti, Li-Kong Wang
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Patent number: 6639246Abstract: There is a problem in that a possibility of a carrier being caused on an interface between a semiconductor layer and an insulating film is high, and the carrier is injected into the insulating film and the interface between the insulating film and the semiconductor layer, so that a threshold rises.Type: GrantFiled: July 22, 2002Date of Patent: October 28, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Honda
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Patent number: 6627919Abstract: A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.Type: GrantFiled: December 12, 2002Date of Patent: September 30, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-shen Maa, Douglas James Tweet, Sheng Teng Hsu
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Patent number: 6624477Abstract: A monolithic circuit comprises a plurality of thin film transistors. Source and drain regions of the TFT are provided with a metal silicide layer having a relatively low resistivity. Thereby, the effective distance between a gate and a source/drain electrode can be reduced.Type: GrantFiled: July 24, 1998Date of Patent: September 23, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiko Takemura, Hongyong Zhang, Toshimitsu Konuma
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Patent number: 6624445Abstract: A semiconductor device using a crystalline semiconductor film is manufactured. The crystalline semiconductor film is formed by providing an amorphous silicon film with a catalyst metal for promoting a crystallization thereof and then heated for performing a thermal crystallization, following which the crystallized film is further exposed to a laser light for improving the crystallinity. The concentration of the catalyst metal in the semiconductor film and the location of the region to be added with the catalyst metal are so selected in order that a desired crystallinity and a desired crystal structure such as a vertical crystal growth or lateral crystal growth can be obtained. Further, active elements and driver elements of a circuit substrate for an active matrix type liquid crystal device are formed by such semiconductor devices having a desired crystallinity and crystal structure respectively.Type: GrantFiled: May 1, 2002Date of Patent: September 23, 2003Assignee: Semiconductor Energy Laboratory Co., LTDInventors: Akiharu Miyanaga, Hisashi Ohtani, Yasuhiko Takemura
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Patent number: 6620659Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.Type: GrantFiled: May 18, 2001Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Philip George Emmma, Wei Hwang, Stephen McConnell Gates