Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: The present invention provides a semiconductor device and a method of manufacturing the same, the device being provided with a semiconductor circuit consisting of a semiconductor element that is capable of improving characteristics of a TFT and has uniform characteristics, the device and the method being provided by improving the interface between an active layer, in particular, a region for constructing a channel formation region and an insulating film.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type.

Abstract: A semiconductor device having a plurality of crystalline silicon clusters. The semiconductor device is formed on an insulating surface and includes crystalline silicon clusters anchored with each other with substantially no grain boundary therebetween.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.

Abstract: A method for annealing amorphous silicon film to produce polycrystalline film suitable for thin-film transistors fabricated on glass substrates is provided. The method involves using the selective location of nickel on a predetermined region of silicon to define the pattern of the lateral growth front as the silicon is crystallized. The method defines the resistivity of the silicide formed. The method also defines a specific range of nickel thicknesses to form the nickel silicide. A minimum thickness ensures that a continuous layer of nickel silicide exists on the growth front to promote an isotropic lateral growth front to form a crystalline film having high electron mobility. A maximum thickness limit reduces the risk of nickel silicide enclaves in the crystalline film to degrade the leakage current. Strategic placement of the nickel helps prevent nickel silicide contamination of the transistor channel regions, which degrade the leakage current.

Abstract: A method of stabilizing an anti-reflection coating (ARC) layer is disclosed. The method provides a substrate with a dielectric layer, a conductive layer, and the ARC layer formed thereon. The ARC layer is treated in an alloy treatment step prior to forming a photoresist layer over the ARC layer, so that the specificity of the ARC layer is stabilized to allow accurate transfer of a desired pattern. A photomask with the desired pattern is provided, while a photolithographic process is then performed to transfer the pattern onto the wafer.

Abstract: A semiconductor device of the present invention comprises a gate insulating layer made of a oxynitride formed on a semiconductor substrate, a gate electrode formed on the gate insulating layer, source/drain regions formed in the semiconductor substrate on both sides of the gate electrode and including impurity, and a oxynitride insulating layer covering the source/drain regions on a surface of the semiconductor substrate and having nitrogen concentration distribution which is different from that of the gate insulating layer along a film thickness direction.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Nitrogen Oxide base film on a substrate, and then depositing an ultra-thin nitride film on the base film. The semiconductor device is then annealed in situ in ammonia, following which the device is oxidized in Nitrogen Oxide. FET gates are then conventionally formed over the gate insulator, and the gates are next implanted with Nitrogen to passivate dangling Nitrogen and Silicon bonds in the nitride, thus decreasing the charge content in the film. Consequently, the resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: A method of forming a nitrogen-implanted gate oxide in a semiconductor device includes preparing a silicon substrate; forming an oxide layer on the prepared substrate; and implanting N+ or N2+ ions into the oxide layer in a plasma immersion ion implantation apparatus.

Abstract: A display device having high definition and high reliability, and technology for manufacturing the same. In an active matrix type display device of integrated peripheral driving circuit type, pixel TFTs of an active matrix circuit 100 are not provided with LDD regions. Also, among circuits constituting peripheral driving circuits 101, 102, buffer circuits, of which a high withstand voltage and high-speed operation are required, are made with thin film transistors having floating island regions and base regions between source and drain regions of their active layers.

Abstract: To provide a semiconductor device having a function equivalent to that of IGFET, an activation layer is formed by a crystal silicon film crystallized by using a catalyst element helping promote crystallization and a heating treatment is carried out in an atmosphere including a halogen element by which the catalyst element is removed, the activation layer processed by such steps is constituted by a peculiar crystal structure and according to the crystal structure, a rate of incommensurate bonds in respect of all of bonds at grain boundaries is 5% or less (preferably, 3% or less).

Abstract: The absolute value of the threshold voltage of a P-channel TFT is reduced by making its channel length shorter than that of an N-channel TFT by at least 20%, to thereby approximately equalize the threshold voltage absolute values of those TFTs.

Abstract: The present invention discloses a structure for 3-D transistors with high electrostatic discharge (ESD) reliability. The 3-D transistors are fabricated on a substrate. The substrate has several recess portions and silicon islands. Several buried oxide regions are formed in the silicon islands and upper portions of the silicon islands are isolated from the substrate by the buried oxide regions. Then, a gate oxide layer is formed on the substrate. The upper portions of the silicon islands are enclosed by the gate oxide layer and the buried oxide region. A gate structure is defined on each of the recess portions and silicon islands. Two N-type source/drain regions are defined in each of the silicon islands adjacent to each of the gates on the silicon islands. Two P-type source/draid regions are fabricated in each of the recess portions adjacent to each of the gates on the recess portion. Spacers are defined on the sidewalls of the gates and abutting to the gates.

Abstract: In forming an electrode on a silicon oxide film on a semiconductor substrate through a silicon oxide film, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers. The portion of the gate electrode is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and of crystallizing (recrystallizing) this amorphous material. Depositing of the amorphous layers is carried out a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and crystallizing the amorphous material are repeated, whereby a laminated structure of polycrystalline layers having a necessary film thickness is obtained.

Abstract: A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening.

Abstract: A transistor includes an MILC (metal-induced lateral crystallization) region formed on a substrate with a semiconductor material and including a channel region, and a plurality of MIC (metal-induced crystallization) regions formed on the sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region. A method of fabricating a transistor includes the steps of forming an MILC (metal-induced lateral crystallization) region on a substrate using a semiconductor material, the MILC region including a channel region, and forming a plurality of MIC (metal-induced crystallization) regions formed on sides of the MILC region using a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm.sup.2 /Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.

Abstract: A thin film transistor includes: an insulating film having a surface; a semiconductor film formed on the surface of the insulating film; a source electrode and a drain electrode which are in contact with the semiconductor film; and a gate electrode which is electrically insulated from the semiconductor film. In the thin film transistor, a portion of the semiconductor film at distances of less than 500 angstroms from the surface of the insulating film contains at least silicon including a microcrystalline structure having a conductivity of 5.times.10.sup.-9 S/cm or more. Also, a method for fabricating such a thin film transistor is disclosed.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: A CMOS device includes a first conductivity type semiconductor substrate having an active region, the active region including two second conductivity type of impurity regions and a first channel region between the two second conductivity type impurity regions, a field insulation region on the semiconductor substrate for electrical isolation of the active region from other adjacent active regions, a second conductivity type semiconductor layer on the field insulation layer, the semiconductor layer including two first conductivity type impurity regions and a second channel region between the two first conductivity type impurity regions, and a gate electrode over the first channel region in the active region and the second channel region in the semiconductor layer.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: A pixel circuit construction for image sensing includes a photosensor, an amplifier, a selector switch and, and a reset switch. The amplifier may be a single polycrystalline silicon (channel) transistor for high gain. The selector switch may also be a single polycrystalline silicon (channel) transistor for high conductivity. The reset switch may a single amorphous crystalline silicon (channel) transistor for low leakage current. The photosensor and amplifier may be connected to a shared bias line or may be connected to separate bias and drive lines, respectively. The selector and reset switches may be connected to a shared data line or may be connected to separate data and reset lines, respectively. Laser crystallization and rehydrogenation techniques are well suited to obtaining devices described herein.

Abstract: A gate insulating film 103 is oxidized by a thermal oxidation method using a gate electrode 104 as a mask. At this time, the thickness of the gate insulating film 103 becomes thicker so that the portions indicated by 106 and 107 are obtained. The thickness of an active layer becomes thin at an end 112 of a channel, so that the distance from the gate electrode becomes long by the thickness. Then the strength of an electric field between a source and drain is relaxed by this portion. In this way, a thin film transistor having improved withstand voltage characteristics and leak current characteristics is obtained.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: A semiconductor device includes a plurality of thin film transistors on a substrate having an insulating surface. A channel region of the thin film transistor comprises a crystalline Si film crystallized by a successive irradiation with a pulse laser beam in a scanning pitch P. A size Xs of the channel region in the scanning direction of the pulse laser beam and the scanning pitch P of the pulse laser beam have a relationship approximately equal to Xs=nP where n is an integer of 1 or more.

Abstract: In a thin film transistor (TFT), a mask is formed on a gate electrode, and a porous anodic oxide is formed in both sides of the gate electrode using a relatively low voltage. A barrier anodic oxide is formed between the gate electrode and the porous anodic oxide and on the gate electrode using a relatively high voltage. A gate insulating film is etched using the barrier anodic oxide as a mask. The porous anodic oxide is selectively etched after etching barrier anodic oxide, to obtain a region of an active layer on which the gate insulating film is formed and the other region of the active layer on which the gate insulating film is not formed. An element including at least one of oxygen, nitrogen and carbon is introduced into the region of the active layer at high concentration in comparison with a concentration of the other region of the active layer. Further, N- or P-type impurity is introduced into the active layer.

Abstract: An SRAM cell and a method of manufacturing the same are disclosed. An SRAM cell including pull down devices, access devices and pull up devices each having source and drain regions with LDD structure, the source and drain regions of the access devices having: N.sup.+ source and drain regions; N.sup.- source and drain regions formed under the N.sup.+ source and drain regions; and P.sup.- impurity regions whose predetermined portion is overlapped with the N.sup.- source and drain region.

Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Abstract: The invention provides an improved technique for forming a MOS transistor having lightly doped source and drain junction regions and low parasitic capacitance. The transistor includes raised source and drain electrodes which are strapped to the substrate adjacent the gate insulation. The raised electrodes include interconnect portions which overlie the field oxide separating the semiconductor substrate into a plurality of active regions. The source and drain electrodes are thickest where each overlies its junction with the substrate in order to control the depth of penetration of doping impurities into the substrate. After doping the electrodes, a rapid thermal anneal is performed which diffuses the doping impurities throughout the electrodes and into thin junction regions of the substrate, immediately beneath the source and drain electrodes.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A semiconductor device includes an insulating substrate; a plurality of pixel electrodes arranged in a matrix on the insulating substrate; first thin film transistors for individually driving the pixel electrodes; and driving circuits composed of second thin film transistors formed on the insulating substrate. In this semiconductor device, each of the first and second thin film transistors has a bottom-gate structure comprising a gate electrode patterned on the insulating substrate; a gate insulating film covering the gate electrode; and a semiconducting thin film having a channel region and a source/drain region, which is formed on the gate insulating film. Each of the second thin film transistors has a lightly doped region at least between a drain side highly doped region and the channel region.

Abstract: There is provided a technique for fabricating a thin film transistor having excellent performance. A configuration is employed in which when the thin film transistor is in an on-state, the flowing direction of the on-current coincides with the direction of crystal growth. With such a configuration, grain boundaries of the crystalline silicon in the active layer will not block the on-current. Further, when the thin film transistor is in an off-state, the off-current is always orthogonal to the grain boundaries of the crystalline silicon. The grain boundaries of the crystalline silicon effectively suppresses the off-current in such locations.

Abstract: The absolute value of the threshold voltage of a P-channel TFT is reduced by making its channel length shorter than that of an N-channel TFT by at least 20%, to thereby approximately equalize the threshold voltage absolute values of those TFTs.

Abstract: A substrate transistor is formed, including a gate insulation region formed on a substrate, spaced apart source/drain regions formed in the substrate, and a gate electrode formed on the gate insulation region, disposed between the spaced apart source/drain regions, the gate electrode having a sidewall portion. A lateral thin film transistor is formed, including a sidewall gate insulation region on the sidewall portion of the gate electrode and a lateral channel region on the sidewall gate insulation region such that the gate electrode controls the current in the lateral channel region. A first one of the spaced apart source/drain regions of the substrate transistor preferably includes a lightly-doped inner portion disposed adjacent the gate electrode and a heavily-doped outer portion disposed adjacent the lightly-outer portion, opposite the gate electrode. The lateral channel region preferably is electrically connected to a second one of the spaced-apart source/drain regions of the substrate transistor.

Abstract: In a circuit configuration comprising an n-channel thin-film transistor and a p-channel thin-film transistor integrally produced on a single substrate, a lightly-doped drain (LDD) region is formed selectively in the n-channel thin-film transistor, and damages to semiconductor layers caused when implanting impurity ions are balanced between the n- and p-channel thin-film transistors. This configuration achieves a balance between the n- and p-channel thin-film transistors and thereby provides high characteristics CMOS circuit.

Abstract: A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semi-conductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element may be formed.

Abstract: By forming a gate electrode, a source electrode and a drain electrode so as to assume concentric circles on an active layer made of, for instance, a crystalline silicon thin film, it is prevented that an edge of the active layer is located on a line connecting the source and drain electrodes. This configuration prevents the source and drain electrodes from being short-circuited by the gate electrode, resulting in reduction of a leak current. Specifically, a channel region may surround one the source and drain region while the other of the source and drain region surrounds the channel region. Alternatively, the gate electrode may surround one the source and drain region while the other of the source and drain region surrounds the channel region.

Abstract: In a micro-patterned semiconductor device that uses thin-film polycrystalline silicon for both interconnection and TFT (Thin Film Transistor) configuration elements, the required current supply capacity is achieved by increasing the leakage current of a reverse-direction diode when the reverse-direction junction diode is present in the current path consisting of polycrystalline silicon. Leakage current is increased by steepening the density slope at the PN junction of the diode which consists of polycrystalline silicon, or by making the region near the junction amorphous. For example, sufficient current can be supplied to a large number of memory cells via reverse-direction diodes even when cells that use TFTs consisting of thin-film polycrystalline silicon as the load for the flip-flop are used as large-scale SRAM memory cells. In this way, ultra high-integration memory ICs can be realized.

Abstract: A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: A semiconductor device is disclosed including a first insulating film having a contact hole and being formed on a substrate. A first impurity region is formed in the active layer on the bottom of the contact hole, and a second impurity region is formed in the active layer on the first insulating film outside the contact hole. In addition, a semiconductor region is formed in the active layer on the sidewall of the contact hole, and a second insulating film is formed on the first impurity region in the contact hole. A gate electrode is formed on the second insulating film.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: A first word line connects the gate electrodes of first transfer transistors in adjacent memory cells. A second word line connects the gate electrodes of second transfer transistors in adjacent memory cells. A ground line connects the source regions of first and second driver transistors. The first and second word lines and ground line are formed by a wiring layer different from the wiring layer that forms the gate electrodes of the first and second transfer transistors. The ground line shields the first and second driver transistors, TFTs and the like. Drain contacts include chamfered sides between which the ground line is disposed.

Abstract: A PMOS thin film transistor (TFT) with self-align offset region for SRAM application is described. A source and a drain regions are above the gate region. A channel region is formed offset from the gate. An offset region is formed in the channel region having a length of 0.3 to 0.4 .mu.m. The key point of the present invention is the novel offset design of PMOS-TFT as load elements in an SRAM cell. Unlike the conventional offset design which is outside the gate, the offset region of the present invention is a disconnection region inside the gate which can be easily formed by so called self-align technique. Since the gate has a disconnected portion in the offset region, the trench-like profile of the offset region makes the load resistance in the offset region much higher to effectively reduce the leakage current.

Abstract: A thin file transistor (TPT) has first (lower) and second (upper) gate electrodes which are provide respectively above and under a semiconductor active layer and first and second insulating films (which serve as gate insulating films) provided respectively between the first gate electrode and a semiconductor layer and between a second gate electrode and the semiconductor layer. The second gate electrode has an anodic oxide film made of a material constituting the gate electrode on the upper and side surfaces thereof formed by anodization. Also, a silicide region is provided by covering the source/drain regions of the TFT with a silicide and changing a part of the region into a silicide.

Abstract: A semiconductor device having an integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits.

Abstract: With regard to paired drive transistors, the shape of an active area is (point or line) symmetrical to a channel area in the vicinity of the channel area. With regard to paired transfer transistors, likewise, the shape of a word line is (point or line) symmetrical to the channel area in the vicinity thereof. With this structure, even if a gate electrode (word line) should be misaligned, therefore, the shapes of the channel areas of the paired transistors would become identical, so that there would be no difference between characteristics.