Abstract: A self-aligned LDD TFT and a fabrication method thereof. A substrate is provided, on which a semiconductor layer is formed. A first masking layer is provided over a first region of the portion of the semiconductor layer. The first masking layer includes a material that provides a permeable barrier to a dopant. The semiconductor layer including the first region covered by the first masking layer is exposed to the dopant, wherein the first region covered by the first masking layer is lightly doped with the dopant in comparison to a second region not covered by the first masking region.

Abstract: In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over the pad layer. A first trench is formed extending through the pad layer, second substrate, buried insulating layer and into the first substrate. The first trench is filled with a first isolation. A second trench is formed in the first isolation and filled with a conductive material. An MOS transistor is formed on the second substrate. A bottom gate is formed under the buried insulating layer and self-aligned to the top gate formed on the second substrate.

Abstract: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).

Abstract: A thin film transistor and method for fabricating the same are provided. The thin film transistor comprises a semiconductor layer having a MILC region that has first crystalline grains crystallized by MILC method and second crystalline grains disposed between the first crystalline grains and having different crystalline properties from the first crystalline grains.

Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes. At least one nanoparticle is provided on the projecting feature between the first and second electrodes.

Abstract: A liquid crystal display device 100 comprises a thin film transistor T, a source (data) line 26, a color filter 23, a pixel electrode 24 and the like. After a gate electrode 13, a gate insulating film 16, and a channel region 18 are formed on the glass substrate 10, a polyimide film 20 is formed to surround the peripheries of the region for forming the source/drain regions 22, the color filter 23, the pixel electrode 24, and the source line 26, respectively. A liquid material is applied to the regions surrounded with the wall made of the polyimide film 20 and a thermal treatment is performed to form the element of the color filter 23, the pixel electrode 24 and the like. The polyimide film 20 has a property of light-shielding and then has a function as a black matrix for shielding the surroundings of the pixel region.

Abstract: A nitride compound semiconductor element having improved characteristics, productivity and yield. A nitride compound semiconductor element includes: a sapphire substrate; a first single crystalline layer of AlN formed on said sapphire substrate; a second single crystalline layer formed on said first single crystalline layer, said second single crystalline layer being made of AlxGa1-xN (0.8?x?0.97) and having a thickness of equal to or more than 0.3 ?m and equal to or less than 6 ?m; and a device structure section of a nitride semiconductor formed on said second single crystalline layer.

Abstract: A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

Abstract: The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and suitable for mass production. These objects are achieved by a thin-film transistor formed on a substrate 1 with a finely processed concavoconvex surface 2, in which a source electrode and a drain electrode are formed on adjacent convex portions of the concavoconvex surface 2, with a channel and a gate being formed on a concave area between the convex portions. A gate electrode 5, a gate insulating film 6 and a semiconductor channel layer 7 are laminated in this order on the concave area from the bottom surface of the concave portion toward the top surface.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.

Abstract: A semiconductor device having performance comparable with a MOSFET is provided. An active layer of the semiconductor device is formed by a crystalline silicon film crystallized by using a metal element for promoting crystallization, and further by carrying out a heat treatment in an atmosphere containing a halogen element to carry out gettering of the metal element. The active layer after this process is constituted by an aggregation of a plurality of needle-shaped or column-shaped crystals. A semiconductor device manufactured by using this crystalline structure has extremely high performance.

Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.

Abstract: A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.

Abstract: A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially growing a second semiconductor material having a second lattice spacing different from the first lattice spacing in the recesses, and implanting a dopant in the second semiconductor material after the growing step.

Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in substantially the same depth position as the undersurface of the buried oxide layer or in a position deeper than the buried oxide layer.

Abstract: A method for fabricating a CMOS image sensor with a prism includes the steps of: forming a plurality of photodiodes corresponding to respective unit pixels on a substrate; sequentially forming an inter-layer insulation layer and an uppermost metal line on the substrate and the photodiodes; etching the inter-layer insulation layer to form a plurality of trenches corresponding to the respective photodiodes; depositing a high density plasma (HDP) oxide layer such that the HDP oxide layer disposed between the trenches has a tapered profile; depositing a nitride layer having a higher refractive index than that of the inter-layer insulation layer to fill the trenches; and depositing an insulation layer having a lower refractive index than that of the nitride layer to fill the trenches, thereby forming a prism, wherein the prism induces a total reflection of lights incident to the photodiodes disposed in edge regions of a pixel array.

Abstract: A hybrid orientation semiconductor structure and method of forming the same. The structure includes (a) a semiconductor substrate comprising a first semiconductor material having a first lattice orientation; (b) a back gate region on the semiconductor substrate; (c) a back gate dielectric layer on the back gate region; (d) a semiconductor region on the back gate dielectric layer, wherein the semiconductor region is electrically insulated from the back gate region by the back gate dielectric layer, and wherein the semiconductor region comprises a second semiconductor material having a second lattice orientation different from the first lattice orientation; and (e) a field effect transistor (FET) formed on the semiconductor region, wherein changing a voltage potential applied to the back gate region causes a change in a threshold voltage of the FET.

Abstract: A CMOS output stage is disclosed. The CMOS output stage comprises a substrate and at least one well coupled to the substrate. The CMOS output stage also includes a plurality of slots provided through the one well into the substrate. Each of the slots are oxidized. Each of the plurality of slots are filled with metal to provide a plurality of power busses. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector. This results in the buried power buss metal always having oxide isolated surroundings. This feature allows all of these power busses to be established wherever necessary without causing any circuit issues since they are always insulated from other areas of the device. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector.

Abstract: An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.

Abstract: An active matrix substrate comprises a substrate, a thick-film adhesive pad made of organic resin, provided on the substrate and including, at least at a part of a side face thereof, an inclined region having a first contact angle smaller than 90 degrees to the main face of the substrate, a thin-film active element provided on the thick-film adhesive pad, and a thin-film interconnection line connected to the thin-film active element and extending onto the substrate via the inclined region, a film thickness of the thick-film adhesive pad being four or more times that of the thin-film interconnection line.

Abstract: Thermal hot spots in the substrate of a semiconductor die, and the required surface area of the semiconductor die, are substantially reduced by forming thermal or thermal and electrical pipes in the substrate that extend from a bottom surface of the substrate to a point near the top surface of the substrate.

Abstract: A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semi-conductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 ?, e.g., between 100 and 750 ?. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: The channel region (11) and the source-drain regions (9, 10) are arranged vertically at a sidewall of a dielectric trench filling (4). On the opposite side, the semiconductor material is bounded by the gate dielectric (18) and the gate electrode (16), which is arranged in a cutout of the semiconductor material. A memory cell array comprises a multiplicity of vertically oriented strip-type semiconductor regions in which source-drain regions are implanted at the top and bottom and a channel region embedded in insulating material on all sides is present in between as a floating body.

Abstract: A transistor device includes a channel of p-type substantially transparent delafossite material. Source and drain contacts are interfaced to the channel. Gate dielectric is between a gate contact and the channel.

Abstract: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20 of a first conduction type surrounding a first region thereof; a first buried diffused layer 40c of the second conduction type buried in the first region: a second well 44b of the first conduction type formed near a surface of the semiconductor substrate 20 in the first region; and a first transistor 38e formed on the second well 44b.

Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.

Abstract: In order to solve the problem of inferior gettering efficiency in the n-channel TFT, the present invention provides at an end of the source/drain regions of the n-channel TFT a highly efficient gettering region that contains both of an n-type impurity and a p-type impurity with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.

Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Abstract: A method for making an integrated circuit includes forming spaced-apart trenches on a surface of a single crystal silicon substrate, lining the trenches with a silicon oxide layer, forming a first polysilicon layer over the silicon oxide layer, forming a second polysilicon layer over the first polysilicon layer, and removing a thickness of the single crystal silicon substrate to expose tubs of single crystal silicon in the second polysilicon layer.

Abstract: A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the active layer, source and drain regions formed in the active layer, sandwiching the channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and on side surfaces of the island-like active layer, and insulated and isolated from the channel, source, and drain regions, and an electrode connected to the active layer.

Abstract: A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.

Abstract: There is provided a semiconductor device which includes a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

Abstract: A double gate silicon over insulator transistor may be formed wherein the bottom gate electrode is formed of a doped diamond film. The doped diamond film may be formed in the process of semiconductor manufacture resulting in an embedded electrode. The diamond film may be advantageous as a heat spreader.

Abstract: A method of forming a shallow junction in a semiconductor substrate is disclosed. The method of one embodiment comprises preamorphizing a first region of a semiconductor substrate to a first depth and implanting recrystallization inhibitors into a second region of the semiconductor substrate. The second region is a part of the first region and has a second depth. Next, a dopant is implanted into a third region of the semiconductor substrate with the third region being a part of the second region and a first annealing is performed to selectively recrystallize the first region that has no recrystallization inhibitors. Next, a second annealing is performed to recrystallize the second region and diffuse the dopant within the second region.

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of lowdielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract: A method and system is disclosed for an SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type. The cell has a first device of the first type constructed as a part of a first FinFET having one or more devices of the first type, a first device of the second type whose poly region is an extension of a poly region of the first device of the first type with no contact needed to connect therebetween, wherein the two devices are constructed using a silicon-on-insulator (SOI) technology so that they are separated by an insulator region therebetween so as to minimize the distance between the two devices.

Abstract: A TFT capable of showing a large gm (large ON-current) and having characteristics comparable to those of Si-MOSFET despite of its relatively simple configuration was fabricated by the steps of coating, for example, a positive photo-resist on an Mo film; subjecting the photo-resist to back light exposure from the glass-substrate side under masking with a bottom gate electrode, to thereby form a resist pattern having the same geometry and being aligned with the bottom gate electrode because exposure light is intercepted by the bottom gate electrode but can travel through the Mo film; and etching the Mo film under masking by the resist pattern to thereby form a top gate electrode in conformity with the geometry of the resist pattern in a self-aligned manner.

Abstract: A semiconductor display device which includes the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask, and thus impurity concentrations of the Lov regions and the Loff regions can be independently controlled.

Abstract: In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.

Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.

Abstract: A semiconductor device having a single-crystal substrate made of a material different from nitride III-V compound semiconductors, and a device made on one major surface of said single-crystal substrate by using III-V compound semiconductors, including electrical connection to said device being made through a via hole formed in said single-crystal substrate and method of making the same.

Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Abstract: An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access NMOS transistor and a first inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the first active area of the SOI substrate. A second access NMOS transistor and a second inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the second active area of the SOI substrate. Here, the channels of the first and second load PMOS transistors extend so that carriers move in a [110] silicon crystallization growth direction. In each active area, the drain (or source) of an access NMOS transistor, the drain of a drive NMOS transistor, and the drain of a load PMOS transistor contact one another in a shared region.

Abstract: Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110), a light shielding film (112) is disposed at the position corresponding to periphery of each pixel (102), while a color filter (113) is disposed at the position corresponding to each of the pixels (102). This light shielding film makes the contour of the pixels clear, resulting in an image display with high definition. In addition, it is possible to fabricate the EL display device of the present invention with most of an existing manufacturing line for liquid crystal display devices. Thus, an amount of equipment investment can be significantly reduced, thereby resulting in a reduction in the total manufacturing cost.