Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

Abstract: A solder material comprising a solder alloy and a thermal conductivity modifying component. The solder material has a bulk thermal conductivity of between about 75 and about 150 W/m-K and is usable in enhancing the thermal conductivity of the solder, allowing for optimal heat transfer and reliability in electronic packaging applications.

Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.

Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

Abstract: A dark mirror optical stack, particularly a low emittance, high absorbance dark mirror optical stack is provided. The dark mirror optical stack includes a polyimide substrate containing carbon filler, an aluminum layer on the polyimide substrate, a first silicon oxide layer on the aluminum layer, a chromium layer on the first silicon oxide layer, and a second silicon oxide layer on the chromium layer. In a particularly exemplary embodiment, the aluminum layer has an average thickness of 600 to 2000 Angstroms, the first and second silicon oxide layers have average thicknesses of 500 to 1000 Angstroms, and the chromium layer has an average thickness of 40 to 100 Angstroms.

Abstract: Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.

Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Abstract: Techniques are disclosed for forming a frame on the backplane comprising structures at least partially circumscribing or enclosing metal contacts on the backplane. In some embodiments, the frame may comprise a photoresist. The dimensions and structural integrity of the frame can help prevent misalignment and/or damage of physical obtrusions of light-emitting structures during a bonding process of the light-emitting structures to the backplane.

Abstract: The present invention provides a chip packaging structure, and a packaging method thereof. The structure comprises a silicon-based main body and chip electrodes. The silicon-based main body is provided with a passivation layer on a front face thereof and passivation layer openings are provided on the passivation layer. The chip electrodes have rear faces embedded in the front face of the silicon-based main body. Front faces of the chip electrodes are exposed through the passivation layer openings. A dielectric layer is provided on an upper surface of the passivation layer, and dielectric layer openings are provided. Metal protrusion structures are provided on the front faces of the chip electrodes. An encapsulation layer is provided on side walls and a rear face of the silicon-based main body. The chip packaging structure of the present invention employs insulation protection on side walls to avoid electrical leakage and short circuit conditions.

Abstract: A method of manufacturing, a carrier, and a semiconductor package are provided. The method involves depositing a plurality of conductive vias, applying a molding material over the lead frame, grinding the molding material to expose the plurality of conductive vias, and depositing a metalized pattern over the molding material. The carrier is manufacture by this method and the semiconductor package is formed based on the carrier.

Abstract: A chip on film package includes a base film, a chip and a heat-dissipation structure. The base film includes a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface and has a chip length along a first axis of the chip and a chip width along a second axis of the chip perpendicular to the first axis. The heat-dissipation structure includes a covering portion. The covering portion at least partially covers the chip, exposes a side surface of the chip, and has a first length along the first axis and a second length along the second axis being longer than the chip width of the chip. The side surface connects a top surface and a bottom surface of the chip. A heat-dissipation structure is also provided.

Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Abstract: Provide an electronic component that has a hollowed structure and is capable of suppressing the deformation of the hollowed structure due to the pressure during the module resin molding. The electronic component includes a device substrate 2, a driver portion 3 formed on one of the principle surfaces of the device substrate 2, a protection portion 4 configured to cover the driver portion 3 so as to form a hollowed space 8 around the driver portion 3, an adhesion layer 10 that is made of a resin and arranged above the protection portion 4, and a reinforcing plate 11 arranged on the adhesion layer 10, wherein the reinforcing plate 11 is a silicon substrate.

Abstract: In one aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package includes a lead frame. A semiconductor die is attached to a first side of the lead frame. A protective shell covers at least a first portion of the first surface of the semiconductor die. The protective shell comprises of ink residue. A layer of molding compound covers an outer surface of the protective shell and exposed portion of the first surface of the semiconductor die. A cavity space is within an inner space of the protective shell and the first portion of the top surface of the semiconductor die.

Abstract: The subject matter of this specification generally relates to electronic packages. In some implementations, a lidless electronic package includes a substrate having a surface and a die disposed on the surface of the substrate. The die has an outside perimeter, a bottom surface adjacent to the surface of the substrate, and a top surface. The electronic package includes a stiffener disposed on the surface of the substrate. The stiffener includes a first surface that is a first distance from the surface of the substrate and a second surface disposed between the die and the first surface. The first distance is greater than a distance between the surface of the substrate and the top surface of the die. The second surface is a second distance from the surface of the substrate that is less than the distance between the surface of the substrate and the top surface of the die.

Abstract: A method of producing an optoelectronic component includes providing a wafer substrate that includes a light-emitting layer sequence, singulating the wafer substrate having the layer sequence into semiconductor components, applying the semiconductor components to an intermediate carrier, arranging a potting material on the intermediate carrier such that the potting material laterally surrounds the semiconductor components and is in direct contact, at least in places, with side surfaces of the semiconductor components, arranging one contact on one semiconductor component and the potting material, wherein one contact is arranged on a side of the semiconductor component and the potting material remote from the intermediate carrier, connecting the component to a carrier element, on a side of the semiconductor components remote from the intermediate carrier, removing the intermediate carrier and the wafer substrate of the semiconductor components, and bringing the semiconductor components into electrical contact b

Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.

Abstract: A plastic component with at least one electrical contact element has a plastic body and at least one electrical strip conductor, by which the electrical contact element can be electrically connected. Provisions are made for the plastic component to be manufactured by a combined injection molding and metal casting method, in which the plastic body is manufactured by an injection molding method and the at least one electrical strip conductor is manufactured by a metal casting or metal injection molding method one after another. The component formed last is molded onto the component formed first. Further, a method for manufacturing a corresponding plastic component is described.

Abstract: A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure.

Abstract: A rip stop material is attached at a stress area of a flexible circuit board in order to strengthen the flexible circuit board and minimize ripping and cracking in the polyimide and/or the copper conductors of the circuit. A rip stop transition layer is formed and deposited at a location on the flexible circuit in order to minimize, reduce, if not preventing cracking and ripping of the circuit as it is bent and flexed. The rip stop transition layer can be placed at different locations on and within the flexible circuit in order to minimize cracking and ripping as the flexible circuit is bent, flexed and twisted.

Abstract: A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a molding compound extends over a first portion of an upper surface of each of the leads that is located farthest from the die pad. The molding compound may also extend over an upper surface of the die pad. A second portion of the upper surface of each of the plurality of leads that is located nearest the die pad remains exposed outside the molding compound. A thickness of the molding compound covering the first portion of the upper surface of each of the leads is greater than a thickness of the molding compound covering the upper surface of the die pad.

Abstract: A method includes placing a microelectromechanical system (MEMS) device over a carrier, wire bonding the MEMS device to a bond pad on the carrier with a bond wire, and spray coating a buffer layer over the MEMS device and enclosing the bond wire. A Young's modulus value of the buffer layer is less than a Young's modulus value of the MEMS device.

Abstract: The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal molded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the molded body used according to the method for contacting are selected corresponding to the magnitude.

Abstract: An electric circuit configuration having an MID circuit carrier and a connecting interface, the connecting interface being situated on a surface of the MID circuit carrier. The electric circuit configuration further includes at least one electrical contact pair having at least one connecting interface contact element and at least one MID contact element that is provided on the surface and is situated on the connecting interface contact element. The exemplary embodiments and/or exemplary methods of the present invention further relates to a contact element group having at least one electrical contact element for the electrical contacting of an MID circuit carrier, which is developed on a surface of an MID circuit carrier, is electrically connected to it, and extends away from the surface. The at least one contact element is connected to a line element of the MID circuit carrier.

Abstract: The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

Abstract: The present invention relates to a photo-curable and thermo-curable resin composition that can provide a dry film solder resist having a higher glass transition temperature and improved heat resistance reliability, and the dry film solder resist. Said resin composition may include an acid-modified oligomer including an iminocarbonate-based compound having a carboxy group (—COOH) and a photo-curable unsaturated functional group, a photo-polymerizable monomer having two or more photo-curable unsaturated functional groups, a thermo-curable binder having a thermo-curable functional group, and a photo-initiator.

Abstract: A semiconductor device with a semiconductor chip and electrical connecting elements to a conductor structure, and a method for producing the same is disclosed. In one embodiment, the conductor structure has a chip island and contact terminal areas. These are arranged in a coplanar manner in relation to each other. The semi-conductor structure is selectively coated by a filled plastic film. Both the semiconductor chip and the electrical connecting elements are mechanically fixed and electrically connected by means of the film-covered chip island and the film-covered contact terminal areas, respectively.

Abstract: A chip on film (COF) type semiconductor package is provided. The chip on film (COF) type semiconductor package includes a film, a plurality of leads formed on a surface of the film, a chip adhered to ends of the leads, an underfill layer filled within a space between the chip and the leads, and a heat dissipation layer adhered to an other surface of the film, the heat dissipation layer including a graphite material layer, a protection layer formed on a surface of the graphite material layer to cover the graphite material layer, and an adhesion layer formed on an other surface of the graphite material layer to adhere the heat dissipation layer to the other surface of the film.

Abstract: Semiconductor packages are provided that have a base plate with a matrix of pure silver or a silver alloy and reinforcement particles. The reinforcement particles can include high thermal conductivity, low CTE particles selected from the group consisting of diamond, cubic boron nitride (c-BN), silicon carbide (SiC), and any combinations thereof. In some embodiments, the base plate is entirely comprised of the composite. In other embodiments, the base plate has a core made of the composite. The core can include at least one outer layer on the core. The semiconductor package can include one or more dice or transistors on the base plate, an insulated frame on the base plate, and one or more leads on the insulated frame.

Abstract: A high-frequency module has a multilayer board formed by laminating a plurality of sheets made of a thermoplastic resin material and subjecting the laminated sheets to thermocompression bonding, and an IC chip placed in a cavity provided in the multilayer board. A gap is provided between a side of the IC chip and an inner wall of the cavity. The multilayer board includes a via-hole conductor provided near the inner wall of the cavity for preventing the resin sheets from being softened and flowing into the cavity upon thermocompression bonding.

Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract: A substrate comprising a plurality of layers, a first side and a second side; and a via extending through the substrate from the first side to the second side. The via comprises:a first substrate via extending through a first layer of the plurality of layers, the first substrate via having a first cross-sectional area; a first capture pad disposed under the first substrate via, wherein the first capture pad physically contacts the first substrate via; a second substrate via extending through a second layer of the plurality of layers, the second substrate via physically contacting the first capture pad, the second substrate via having a second cross-sectional area that is greater than the first cross-sectional area; and a second thermal and electrical contact pad disposed under the second dielectric layer, wherein the second contact pad physically contacts the second substrate via.

Abstract: A photosensitive imaging device and a method for forming a semiconductor device are provided. The method includes: providing a first device layer formed on a first substrate, wherein a conductive top bonding pad layer is formed on the first device layer; providing a continuous second device layer formed on a second substrate, wherein a continuous conductive adhesion layer is formed on the continuous second device layer; bonding the first device layer with the second device layer, where the top bonding pad layer on the first device layer is directly connected with the conductive continuous adhesion layer on the continuous second device layer; removing the second substrate; selectively etching the continuous second device and the continuous conductive adhesion layer to form a groove array; and filling up the groove array with an insulation material to form a plurality of second devices. Alignment accuracy may be improved.

Abstract: A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from the first surface toward the second surface. The first insulation layer has a first hole which penetrates through the first insulation layer and includes a first conductor made of a plating in the first hole. The second insulation layer has a second hole which penetrates through the second insulation layer and includes a second conductor made of a conductive paste in the second hole. The third insulation layer has a third hole which penetrates through the third insulation layer and includes a third conductor made of a plating in the third hole. The first, second and third conductors are positioned along the same axis and are electrically continuous with each other.

Abstract: A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract: A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure.

Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.

Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (12). A sidewall (20) is formed around the MEMS device element, and a sacrificial layer (14) is formed over the device element and within the sidewall. A package cover layer (16) is provided over the sacrificial layer, and the sacrificial layer is removed. This method provides additional sidewalls to the cap provided over the MEMS device. These additional sidewalls can then be deposited by a different process and be formed of a different material to the top part of the package cover layer. The sidewalls can prevent reflow of the sacrificial layer and improve the sealing properties of the sidewalls.

Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.

Abstract: A module substrate may include a substrate body on which a plurality of chip mounting regions having connection pads are defined. Repair structures may be respectively formed, or placed, in the chip mounting regions. Each repair structure includes conductive layer patterns formed over the connection pads in each chip mounting region, an insulation layer pattern formed over the substrate body in each chip mounting region in such a way as to expose the conductive layer patterns, plastic conductive members formed between the connection pads and the conductive layer patterns, and a plastic insulation member formed between the substrate body and the insulation layer pattern in each chip mounting region.

Abstract: The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region.

Abstract: A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.

Abstract: A package structure is provided, which includes a dielectric layer having opposing first and second surfaces, and through holes penetrating the surfaces; a strengthening layer formed on the first surface; a circuit layer formed on the second surface, and having wire bonding pads formed thereon and exposed from the through holes, and ball pads electrically connected to the wire bonding pads; a first solder mask layer formed on the first surface and the strengthening layer, and having first apertures formed therethrough for exposing the wire bonding pads; a second solder mask layer formed on the second surface and the circuit layer, and having second apertures formed therethrough for exposing the ball pads; and a semiconductor chip disposed on the first solder mask layer and electrically connected via conductive wires to the wire bonding pads exposed from the through holes. The strengthening layer ensures the steadiness of the chip to be mounted thereon without position shifting.

Abstract: A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer.

Abstract: A semiconductor embedded module 1 of the present invention has a configuration in which a semiconductor device 20, which is an electronic component such as a semiconductor IC (die) in a bare chip state, is embedded in a resin layer 10 (second insulating layer). In the semiconductor device 20, a redistribution layer 22 is connected to land electrodes. A protective layer 24 (first insulating layer) is provided on the redistribution layer 22, and is provided with openings such that external connection pads P of the redistribution layer 22 are exposed. Also, the resin layer 10 is formed to cover the protective layer 24, and vias V are formed at the positions of the respective external connection pads P of the redistribution layer 22. The grinding rate of the resin layer 10 is larger than that of the protective layer 24.

Abstract: A circuit board (1) exhibits an average coefficient of thermal expansion (A) of the first insulating layer (21) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point of equal to or higher than 3 ppm/degrees C. and equal to or lower than 30 ppm/degrees C. Further, an average coefficient of thermal expansion (B) of the second insulating layer (23) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point is equivalent to an average coefficient of thermal expansion (C) of the third insulating layer (25) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point. (B) and (C) are larger than (A), and a difference between (A) and (B) and a difference between (A) and (C) are equal to or higher than 5 ppm/degrees C. and equal to or lower than 35 ppm/degrees C.

Abstract: This publication discloses an electronic module and a method for manufacturing an electronic module, in which a component (6) is glued (5) to the surface of a conductive layer, from which conductive layer conductive patterns (14) are later formed. After gluing the component (6), an insulating-material layer (1), which surrounds the component (6) attached to the conductive layer, is formed on, or attached to the surface of the conductive layer. After the gluing of the component (6), feed-throughs are also made, through which electrical contacts can be made between the conductive layer and the contact zones (7) of the component. After this, conductive patterns (14) are made from the conductive layer, to the surface of which the component (6) is glued.