Abstract: A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned in the concave. The first electrode pins are connected to a first side of the main module and also electrically connected to the light emitting diode chip. The second electrode pins are arranged on a second side of the main module that is relative to the first electrode pins wherein the second electrode pins and the first electrode pins are electrically opposite. The second electrode pins are electrically connected to the light emitting diode chip. The heat dissipation board is connected to a part of the main module between the first electrode pin and the second electrode pin.

Abstract: A heat dissipating wiring board includes a metal wiring plate with a circuit pattern formed therein, a filler containing resin layer embedded with the metal wiring plate such that a top surface of the metal wiring plate is exposed, and a heat dissipating plate arranged on an under surface of the filler containing resin layer. The circuit pattern is formed of a through groove provided in the metal wiring plate. The through groove includes a fine groove that opens at the top surface of the metal wiring plate and an expanded groove that expands from a lower end of the fine groove toward the under surface of the metal wiring plate. The heat dissipating wiring board is capable of improving reliability against electric insulation due to dust or the like in a space of the through groove.

Abstract: A semiconductor device is made by forming a heat spreader over a temporary carrier. A semiconductor die is mounted to the heat spreader. A first polymer layer is formed over the semiconductor die and heat spreader. A first conductive layer is formed over the first polymer layer. The first conductive layer is connected to the heat spreader and contact pads on the semiconductor die. A second polymer layer is formed over the first conductive layer. A second conductive layer is formed over the second polymer layer. The second conductive layer is electrically connected to the first conductive layer. Bumps are formed through a solder masking layer on the second conductive layer. The temporary carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first and second conductive layers.

Abstract: A rectangular display driver integrated circuit device adapted for use with a flat panel display (FPD) device is disclosed and comprises, a plurality of input pads arranged in a central portion of the display driver integrated circuit device, and a plurality of output pads arranged along edges of all four sides of the display driver integrated circuit device. An associated film, film package, and flat panel display (FPD) module adapted to receive the display driver integrated circuit device are also disclosed.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

Abstract: A rectifier comprising at least two wafers hermetically sealed within a first dielectric layer and connected to an input and an output, the rectifier further comprising a second dielectric layer overlying the first layer.

Abstract: An integrated circuit having a semiconductor sensor device including a sensor housing partly filled with a rubber-elastic composition is disclosed. One embodiment has a sensor chip with sensor region arranged in the interior of the housing. The sensor housing has an opening to the surroundings which is arranged in such a way that the sensor region faces the opening. The sensor chip is embedded into a rubber-elastic composition on all sides in the interior of the housing. The sensor housing has a sandwich-like framework having three regions arranged one above another, including an intermediate region with the rubber-elastic composition.

Abstract: An assembly for testing microelectronic devices includes a microelectronic element having faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The assembly also includes a plurality of support elements disposed between the microelectronic element and the substrate for supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: A method for automatically designing a buffer packing size and a computer accessible storage media to store program thereof are provided. First, a buffer thickness of a buffer material is calculated, and a buffer area for a surface of the object receiving an impact is calculated according to a weight of an object and a static stress of the buffer material. Next, a suitable buffer packing size is automatically calculated according to the buffer thickness and the buffer area.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: Methods for the addition polymerization of cycloolefins using a cationic Group 10 metal complex and a weakly coordinating anion of the formula: [(R?)zM(L?)x(L?)y]b[WCA]d wherein [(R?)zM(L?)x(L?)y] is a cation complex where M represents a Group 10 transition metal; R? represents an anionic hydrocarbyl containing ligand; L? represents a Group 15 neutral electron donor ligand; L? represents a labile neutral electron donor ligand; x is 1 or 2; and y is 0, 1, 2, or 3; and z is 0 or 1, wherein the sum of x, y, and z is 4; and [WCA] represents a weakly coordinating counteranion complex; and b and d are numbers representing the number of times the cation complex and weakly coordinating counteranion complex are taken to balance the electronic charge on the overall catalyst complex.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a shaped platform with a conductive post; mounting the shaped platform with the conductive post over a temporary carrier; mounting an integrated circuit device over the temporary carrier; encapsulating the conductive post and the integrated circuit device; removing a portion of the shaped platform isolating the conductive post; and removing the temporary carrier.

Abstract: The invention relates to a semiconductor device with a semiconductor chip and a rewiring layer, the semiconductor chip being embedded in a housing plastics composition by its rear side contact. The active top side of the semiconductor chip forms a coplanar overall top side with the top side of the housing plastics composition. The rear side contact is led to the overall top side via a flat conductor sheet tape, so that the rear side contact of the semiconductor chip can be accessed from the overall top side.

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract: A rigid-flex PCB includes at least one rigid PCB (RPCB) and at least one flexible PCB (FPCB). Each RPCB has a connection section; first and second sections separately extended from two lateral edges of the connection section and having at least one FPCB bonding side each; and a weakening structure formed along each joint of the connection section and the first and second sections. Each FPCB has a bending section corresponding to the connection section on the RPCB; first and second sections separately extended from two lateral edges of the bending section and having at least one RPCB bonding side each corresponding to the FPCB bonding sides of the first and second sections of the RPCB. When a proper pressure is applied against the weakening structures, the RPCB may be easily bent broken at the weakening structures to remove the connection section therefrom.

Abstract: An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and the rigid locking lead; and forming an encapsulation over the integrated circuit with the lead locking portion in the encapsulation and the lead exposed portion exposed from the encapsulation.

Abstract: An adapter board includes a package substrate having a first surface and a second surface and further including a board having wirings formed therein, pads disposed in the device side, and the pads disposed in the bump side, an insulating resin layer joined to the first surface, through holes formed in the positions corresponding to the pads in the insulating resin layer, vias formed in the through holes, and pads covering the through holes, wherein the pads are electrically coupled to the pads through the wirings, and the pads are electrically coupled to the pads through the vias.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.

Abstract: A semiconductor device of the present invention includes: a wiring board 4 in which a conductive wiring 6 is formed on an insulating substrate 5 having an opening 5a; a semiconductor element 2 that has a circuit forming region 2a and an electrode pad 3, and is mounted on the wiring board with the circuit forming region facing the opening, the electrode pad being connected electrically to the conductive wiring via a protruding electrode 3a; a sealing resin 7 that covers the connected portion between the electrode pad and the conductive wiring; a heat dissipating member 9 that is disposed so as to have a portion facing the opening; and a filling material 8 that has a heat conductivity higher than that of the sealing resin, and is filled into the opening, so as to be in contact with the circuit forming region of the semiconductor element and the heat dissipating member. Even when the wiring board has a small area, heat dissipation efficiency can be ensured, and low cost manufacture can be achieved.

Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.

Abstract: A semiconductor device and a method for producing it is disclosed. In one embodiment, an adhesion-promoting layer having nanoparticles is arranged between a circuit carrier and a plastic housing composition for the purpose of enhanced adhesion.

Abstract: An adhesive tape 101 electrically connecting conductive components includes a resin layer 132 containing a thermosetting resin, a solder powder 103 and a curing agent. The solder powder 103 and the curing agent reside in the resin layer 132, the curing temperature T1 of the resin layer 132 and the melting point T2 of the solder powder 103 satisfy T1?T2+20° C., wherein the resin layer 132 shows a melt viscosity of 50 Pa·s or above and 5000 Pa·s or below, at the melting point T2 of the solder powder 103.

Abstract: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through hole for inserting the electric element. The one resin film further has a plurality of protruding members. One protruding member opposes to another one protruding member so that the one and the another one contact and sandwich the electric element. The spacer is arranged between the one resin film and an adjacent resin film and is disposed at a base portion of one of the protruding members.

Abstract: A semiconductor device includes a circuit board, a wiring part, a protective coating glass, and a resin part. The circuit board has an approximately rectangular shape. The protective coating glass is disposed on the circuit board and is arranged on an inside of the circuit board in such a manner that an outer-peripheral end of the protective coating glass is away from each of four sides of the circuit board at a first distance and is away from each of four corners of the circuit board at a second distance that is larger than the first distance. The resin part seals the circuit board, the wiring part, and the protective coating glass in such a manner that an outer-peripheral end portion of the circuit board that is located on an outside of the protective coating glass directly contact with the resin part.

Abstract: An electronic device housing includes a substrate, a film structure, and a protective film. The film structure includes an adhesive film, a film stack, and a protective film. The adhesive film is deposited onto the substrate. The film stack is deposited onto the adhesive film alternating dielectric films and metal films. The metal films are non-continuous with a total thickness of the metal films at a predetermined value. The protective film is deposited onto an upper film of the film stack.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: On a surface of a resin base material (11), a first resin coating film (19) having a larger thickness and a larger area than a second resin coating film (20) formed on the other surface of the resin base material (11) is continuously formed. The second resin coating film (20) is formed so as to be separated into a plurality of portions.

Abstract: A method for producing a device and a device is disclosed. In one embodiment, a component is surrounded by a material. A fluoropolymer-containing compound is produced at a surface of the material. A molding is produced from a material and a fluoropolymer-containing compound is produced at a surface of the molding by a vapor deposition.

Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together.

Abstract: A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.

Abstract: An electronic component has a first semiconductor chip and a second semiconductor chip that is arranged on a plastic compound in which the first semiconductor chip is embedded. The semiconductor chips are connected to one another by rewiring layers and vias which extend between the rewiring layers, the vias being widened at a transition to one of the rewiring layers.

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract: A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first chip such that faces of the signal pads align to enable for capacitive signal coupling. The high permittivity dielectric material layer that fills at least a portion of a gap between the first chip and the second chip, and improves capacitive coupling between signal pads of the first chip and the second chip by providing for an increased permittivity in the gap between the first chip and the second chip. The increased permittivity ensures that electric fields are substantially confined to a space between the signal pad of the first chip and the signal pad of the second chip.

Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.

Abstract: A method of manufacturing a semiconductor device includes placing a chip on a carrier, and applying an electrically conducting layer to the chip and the carrier. The method additionally includes converting the electrically conducting layer into an electrically insulating layer.

Abstract: An insulating film for semiconductor devices is obtained by curing, on a substrate, a high molecular compound obtained by polymerizing a cage-type silsesquioxane compound having two or more unsaturated groups as substituents and having a cyclic siloxane structure, wherein the structure of the cage-type silsesquioxane compound is not broken by curing, and the breakage of the cage structure can be detected by observing a peak at approximately 610 cm?1 in Raman spectrum of the film after curing.

Abstract: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.

Abstract: A highly reliable semiconductor device which is not damaged by local pressing force from the outside and in which unevenness of a portion where an antenna and an element overlap with each other is reduced. The semiconductor device includes a chip and an antenna. The chip includes a semiconductor element layer including a thin film transistor; a conductive resin electrically connected to the semiconductor element layer; and a sealing layer. The sealing layer in which a fiber body is impregnated with an organic resin covers the semiconductor element layer and the conductive resin, and has a thickness of 10 to 100 ?m. The antenna has a depressed portion and is electrically connected to the semiconductor element layer through the conductive resin. The chip is embedded inside the depressed portion. The thickness of the chip is equal to the depth of the depressed portion.

Abstract: A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first notch with a first depth and a second notch with a second depth. The first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch. A final insulating layer and a metal seed layer are sequentially formed on the stair structure. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving exposed portions of the metal seed layer located above the first notch is formed. The patterned photoresist layer and portions of the metal seed layer disposed below the patterned photoresist layer are then removed.

Abstract: A method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. Through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base.

Abstract: A semiconductor device includes a plurality of insulating layers laminated on a substrate to cover passive elements such as a capacitor, an inductor, and the like, and to fix an IC chip in a face up state in one of the insulating layers. The insulating layers have similar structures in each of which the passive element or the semiconductor chip is disposed in at the bottom, a plug is formed in the insulating layer to pass therethrough in the thickness direction for extending an electrode of one of these elements to the top surface, and a conductive layer is provided as wiring on the top surface of the insulating layer to be connected to the plugs for electrically connecting respective elements or rearranging the electrode position. Also, an insulating layer is provided on the top for protecting the semiconductor device and for providing an external connecting electrode.

Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.

Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.