Abstract: Devices and methods for mounting components of electronic circuitry and these mounting devices are capable of surviving repeated thermal cycling. The devices comprise two metal laminate members brazed to a ceramic member on each of the two major surfaces of the ceramic member. The laminates preferably comprise a layer of molybdenum disposed between two layers of copper. The thickness of the individual layers comprising the metal laminate member may be varied to yield a laminate CTE similar to the CTE of the ceramic member to be joined.

Abstract: An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the carrier substrate and in electrical communication with the information router across at least one of the electrical leads associated with the carrier substrate.

Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.

Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.

Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.

Abstract: The objective of the invention is to provide a ceramic substrate: wherein even if rapid temperature rising or rapid temperature falling is conducted, no problem of cracking or warp of the ceramic substrate occurs; wherein, in case that the ceramic substrate is a ceramic substrate constituting an electrostatic chuck, local dispersion of chuck power is eliminated, in case that the ceramic substrate is a ceramic substrate constituting a hot plate, local dispersion of temperature of a wafer treating face is eliminated, in case that the ceramic substrate is a ceramic substrate constituting a wafer prober, dispersion of applied voltage of a guard electrode or a ground electrode is eliminated and a stray capacitor or noise can be eliminated.

Abstract: The present invention provides a method and apparatus for testing semiconductor wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. After testing, the wafer is diced into the individual circuits, eliminating the need for additional packaging. One form of the present invention provides an interposer substrate made of a ceramic material that has an upper and a lower surface. There are one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. There are also one or more electrical pathways that connect the first and second electrical contacts.

Abstract: An electronic package includes a multi-layer substrate module that includes electrically parallel vias to carry an electrical data signal between two nodes. For example, the vias may be coupled between nodes of different metallization layers in or on the substrate module. Alternatively, the vias may be coupled between a node of one of the metallization layers and a signal transmission line that feeds or receives data signals or an interconnection that connects the multi-layer module to a next higher level of the assembly, such as a printed circuit board. In other implementations, the vias may be coupled between a data signal transmission line and an interconnection to the next-higher level of the assembly.

Abstract: A semiconductor device comprises at least one first semiconductor layer (1-4) and a second layer (8) applied on at least a surface portion of the first layer for protecting the device. The protecting layer is of a second material having a larger energy gap between the valence band and the conduction band than a first material forming said first layer. The second material has at least in one portion of said protecting layer a nano-crystalline and amorphous structure by being composed of crystalline gains with a size less than 100 nm and a resistivity at room temperature exceeding 1×1010 &OHgr;cm.

Abstract: A work station for a chip bonder, and/or for a wire bonder includes a clampless, porous ceramic vacuum chuck where the substrate under assembly is securely and uniformly held by vacuum applied through many tiny pores distributed across the work surface. Porous ceramic work stations are applicable to a family of packages, or to a substrate outline, and may include one or more chips within the same indexing operation. Reliability and yield of the assembled semiconductor devices is enhanced by avoiding uneven or warped substrates. In addition, the porous ceramic work holder provides a cost effective apparatus by eliminating device specific clamps and work holders, the time required for change-out and set-up.

Abstract: A radiation shielding system for protecting an integrated circuit package from ionizing radiation is provided for an integrated circuit package which is substantially planar and has a plurality of package leads extending from at least one surface of the package, substantially perpendicular to a surface of the integrated circuit package. The system comprises a base portion comprising shielding material and defining a well for receiving the integrated circuit package. A lid of shielding material is provided for being attached to the base portion to completely encompass the integrated circuit package. The system also includes means for allowing portions of each of the package leads to exit the well when the integrated circuit package is within the well. The means includes insulating material.

Abstract: A ball grid array semiconductor package is provided, wherein at least a predetermined position of a conductive trace on a substrate is formed with a discontinuity, allowing the discontinuity and part of the conductive trace around the discontinuity to be exposed to outside of solder mask applied over the substrate and form a discontinuous pad. The conductive trace having the discontinuous pad is electrically conducted as a solder ball is bonded to the discontinuous pad, and is electrically disconnected when the solder ball is not mounted on the discontinuous pad. As the solder ball is hardly bonded firmly to the discontinuous pad, it can be easily removed from the discontinuous pad to disconnect the conductive trace, and the removed solder ball can be simply mounted back to the discontinuous pad to restore electrical conduction of the conductive trace.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: A multilayer ceramic electronic component includes an electronic component body a notch formed in a side surface of the electronic component body, and a joining electrode formed by dividing a joining via hole conductor is formed at a portion of an inside surface defining the notch. A cover that is mounted to the electronic component body has a leg, with the leg of the cover being positioned inside the notch. By joining the leg to the joining electrode, the cover is secured to the electronic component body. The multilayer ceramic electronic component includes an LGA (land grid array) type external terminal electrode. The multilayer ceramic electronic component makes it possible to mount a cover for covering a mounted component without increasing the planar dimensions of the electronic component and without decreasing an area for mounting a component to be mounted.

Abstract: A surface mount ceramic package, e.g. for a microwave or millimeter wave integrated circuit device, has outer conductive pads that are available for direct connection with traces on the printed circuit board. A metal core or base has spaces at one or more sides, e.g., voids or cutouts, where the outer pads are located. There is a first ceramic layer disposed on the core, with a central cavity for the die, and an upper or second ceramic layer. Printed traces are buried between the two layers, and vias connect the traces with the outer pads. Inner pads are located on a ledge of the first layer adjacent the cavity for connection with electrodes of the die. Each of the first and second ceramic layers may be stacked ceramic tape. The package may be LTCC or HTCC. This construction avoids inductive losses, especially at higher frequencies.

Abstract: A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected through the substrate to input/output terminals of the substrate. The substrate has a metal film on the top surface thereof around the opening of the respective the cavities. A metal lid panel, covering the cavity openings, is soldered to the metal film by reflowing a layer of solder disposed over a lid panel bottom surface, thereby sealing the die in each cavity. Subsequently, individual packages are singulated from the ceramic substrate.

Abstract: An hermetically enhanced hybrid microelectronic package of injection moldable plastic and ceramic parts, wherein a gas barrier is formed onto surfaces of the plastic parts through metalization. Further, interface surfaces between the plastic parts and any metal or ceramic parts are further treated to accommodate hermetically stable low temperature bonding such as soldering at a temperature which does not exceed the temperature limits of the plastic.

Abstract: A high frequency circuit apparatus whose thermal dissipation characteristics is excellent and which is advantageous in the compact design and in the massproductivity is provided. The high frequency circuit apparatus comprises a multilayer substrate 12 in which direct current circuit patterns 16 and 17 for transferring direct current signals are formed on an upper substrate 121 of the multilayer substrate 12 while a high frequency current circuit pattern 18 for transferring high frequency signals is formed on a lower substrate located lower than the upper substrate.

Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: Aspects for routing in multilayer ceramic substrates that reduces via depth and avoids via bulge are described. The aspects include providing a multilayer ceramic substrate with at least two redistribution layers. Vias for each of a plurality of signal lines are jogged on at least a second redistribution layer of the at least two redistribution layers. Further, the aspects include providing the second redistribution layer no more than seven layers deep in the multilayer ceramic substrate.

Abstract: The present invention provides a silicon nitride ceramic substrate composed of a silicon nitride sintered body in which maximum size of pore existing in grain boundary phase of the sintered body is 0.3 &mgr;m or less, and having a thermal conductivity of 50 W/mK or more and a three point bending strength of 500 MPa or more, wherein a leak current is 1000 nA or less when an alternative voltage of 1.5 kV-100 Hz is applied to a portion between front and back surfaces of the silicon nitride sintered body under conditions of a temperature of 25° C. and a relative humidity of 70%. According to the above structure of the present invention, there can be provided a silicon nitride ceramic substrate capable of effectively suppressing a leak current generation when the above substrate is assembled into various power modules and circuit boards, and capable of greatly improving insulating property and operative reliability of power modules in which output power and capacity are greatly increased.

Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: A high temperature hybrid-circuit structure includes a temperature sensitive device which comprises SiC, AlN and/or AlxGa1−xN(x>0.69) connected by electrodes to an electrically conductive mounting layer that is physically bonded to an AlN die. The die, temperature sensitive device and mounting layer (which can be W, WC or W2C) have temperature coefficients of expansion within 1.06 of each other. The mounting layer can consist entirely of a W, WC or W2C adhesive layer, or an adhesive layer with an overlay metallization having a thermal coefficient of expansion not greater than about 3.5 times that of the adhesive layer. The device can be encapsulated with a reacted borosilicate mixture, with or without an upper die which helps to hold on lead wires and increases structural integrity. Applications include temperature sensors, pressure sensors, chemical sensors, and high temperature and high power electronic circuits.

Abstract: A surface-mount package for multiple LED chips is constructed by inscribing a groove in an insulating substrate. The LED chips are mounted in the groove and the leads are connected to metal plates, which wrap around the substrate to provide bottom contacts for surface-mounting.

Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.

Abstract: A ceramic biomolecule imaging chip includes a ceramic body having a planar imaging surface. The planar imaging surface is highly polished within tolerances of plus or minus 1 microinch. This ceramic chip is compatible with fluorescence laser scanning devices. It is preferred that the ceramic body be 99.6% alumina oxide in order to also be compatible with non-fluorescent detection systems.

Abstract: A ceramic substrate having two side surfaces in a lengthwise direction and two side surfaces in a widthwise direction intersecting each other. The ceramic substrate also includes at least one flat surface in a thicknesswise direction. Internal electrode films are embedded in the ceramic substrate with film surfaces thereof extending roughly parallel to the flat surface of the ceramic substrate. External electrodes are each provided on the flat surface of the ceramic substrate toward one of the two ends of the ceramic substrate in the lengthwise direction, are electrically continuous with the internal electrode films and are formed over distances and from the two side surfaces in the widthwise direction.

Abstract: A high temperature hybrid-circuit structure includes a temperature sensitive device which comprises SiC, AlN and/or AlxGa1−xN(x>0.69) connected by electrodes to an electrically conductive mounting layer that is physically bonded to an AlN die. The die, temperature sensitive device and mounting layer (which can be W, WC or W2C) have temperature coefficients of expansion within 1.06 of each other. The mounting layer can consist entirely of a W, WC or W2C adhesive layer, or an adhesive layer with an overlay metallization having a thermal coefficient of expansion not greater than about 3.5 times that of the adhesive layer. The device can be encapsulated with a reacted borosilicate mixture, with or without an upper die which helps to hold on lead wires and increases structural integrity. Applications include temperature sensors, pressure sensors, chemical sensors, and high temperature and high power electronic circuits.

Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.

Abstract: A multilayer ceramic device improves device functionality, reduces overall device size and profile, makes manufacturing easier, and improves reliability. A first ceramic layer has a first multilayer circuit pattern electrically connected through via holes. Also, a second ceramic layer has a second multilayer circuit pattern electrically connected through via holes. A thermosetting resin sheet is disposed between the first and second ceramic layers. The thermosetting resin sheet has through holes filled with a conductive paste for electrically connecting one of multiple circuit pattern layers in the first ceramic layer with one of multiple circuit pattern layers in the second ceramic layer.

Abstract: It is an object of the present invention to provide a ceramic substrate for a semiconductor producing/examining device which has high fracture toughness value, excellent thermal shock resistivity, high thermal conductivity and an excellent temperature rising and falling properties, and is preferable as a hot plate, an electrostatic chuck, a wafer prober and the like. A ceramic substrate, for a semiconductor producing/examining device, having a conductor formed inside thereof or on the surface thereof of the present invention is the ceramic substrate, wherein said ceramic substrate has been sintered such that a fractured section thereof exhibits intergranular fracture.

Abstract: A semiconductor device for controlling electricity including a metal base plate and at least one insulating substrate. The insulating substrate includes an insulator plate, a back-side pattern on a back face of the insulator plate and bonded to the metal base plate, and two circuit patterns located on a front face of the insulator plate and above the back-side pattern. Each of the two circuit patterns has an “L” shape and extends along two sides of the insulator plate that are continued and perpendicular to each other. The two circuit patterns are also arranged at opposed corners of the insulator plate in a centrosymmetrical relation each other. Further, in each circuit pattern, a switching element is sandwiched between a free-wheel diode and an electrode area.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die having a vertical power transistor, a first surface and a second surface. A ground plane proximate the second surface and distal to the first surface. A bus member covers a portion the first surface of the semiconductor die and has at least one leg that electrically couples a source region of the semiconductor die to the ground plane.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature Tg greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: An apparatus includes a package having a first surface and a conductive contact exposed at the first surface. A capacitor is inside the package. The capacitor has a first conductive contact exposed at a first surface of the capacitor. The first conductive contact has a first portion spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion of the first conductive contact of the capacitor to the first conductive contact proximate the first surface of the package.

Abstract: A semiconductor ceramic for thermistors contains zinc oxide and titanium oxide as main components and a predetermined content of manganese. Also, a chip-type thermistor including the semiconductor ceramic is provided. By adding manganese, the resistance-temperature characteristic is controllable in the range of positive temperature coefficient to negative temperature coefficient. Also, by adding nickel, the resistivity is controllable. As a result, a thermistor material which provides a series of semiconductor ceramics having various resistivities and various B constants in a low range, for example 0 to 1,000 K, is available.

Abstract: A pin grid array package comprises a number of signal pins and ground pins. At least one of the signal pins is a controlled impedance signal pin, i.e. a signal pin whose impedance is adjusted and/or reduced according to the present invention. The pin grid array package also includes a number of ground planes and signal planes. A controlled impedance signal pin is coupled to one of the signal planes by means of a signal via. A number of ground pins surround the controlled impedance signal pin. By varying the arrangement, number, and separation distance between the ground pins and the controlled impedance signal pin, the impedance of the signal pin is adjusted and/or reduced. Depending on the particular circuit or logic function assigned to a signal pin and its adjacent signal pin, a different degree of impedance control and/or reduction can be achieved by the present invention.

Abstract: The present invention provides a ceramic substrate which can keep a sufficiently large breakdown voltage even if the pore diameter of its maximum pore is 50 &mgr;m or less to be larger than that of conventional ceramic substrates, can give a large fracture toughness value because of the presence of pores, can resist thermal impact, and can give a small warp amount at high temperature. The ceramic substrate of the present invention is a ceramic substrate for a semiconductor-producing/examining device having a conductor formed on a surface of the ceramic substrate or inside the ceramic substrate, wherein: the substrate is made of a non-oxide ceramic containing oxygen; and the pore diameter of the maximum pore thereof is 50 &mgr;m or less.

Abstract: A vacuum sealed package for a semiconductor chip, such as a micro-electromechanical (MEM) chip, is disclosed, along with a method of making such a package. In an exemplary embodiment, the package includes a ceramic substrate and a lid that together define a cavity wherein the chip is mounted. The substrate includes a conductive (e.g., metal) interconnect pattern that extends, at least in part, vertically through the substrate. I/O terminals are provided on an external surface of the substrate. A vent hole, at least partially lined with a metal coating, extends through the substrate into the cavity. A metal plug seals the vent hole. The vent hole is sealed by placing the package in a vacuum chamber, evacuating the chamber, and heating the chamber so as to cause a metal preform on the substrate to flow into the vent hole and form the plug.

Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.

Abstract: A laminated radiation member includes a radiation plate, an insulation substrate bonded to the upper surface of the radiation plate and an electrode provided on the upper surface of the insulation substrate. The laminated radiation member is made by a method including the steps of surface treating a bonding surface of the radiation plate and/or the insulation substrate, interposing ceramic particles surface treated to assure wettability with a hard solder or a metal between the radiation plate and the insulation substrate, disposing a hard solder above and/or below the ceramic particles, heating the hard solder to a temperature higher than the melting point of the solder, penetrating the molten hard solder into spaces between the ceramic particles to react the ceramic particles with the solder to produce a metal base composite material, and bonding the radiation plate and the insulation substrate with the metal base composite material.

Abstract: A method of manufacturing a ceramic includes forming a film which includes a complex oxide material having an oxygen octahedral structure and a paraelectric material having a catalytic effect for the complex oxide material in a mixed state, and performing a heat treatment to the film, wherein the paraelectric material is one of a layered catalytic substance which includes Si in the constituent elements and a layered catalytic substance which includes Si and Ge in the constituent elements. The heat treatment includes sintering and post-annealing. At least the post-annealing is performed in a pressurized atmosphere including at least one of oxygen and ozone. A ceramic is a complex oxide having an oxygen octahedral structure, and has Si and Ge in the oxygen octahedral structure.

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.

Abstract: A circuit board comprising a first metal layer 14 formed in patterns on a ceramic substrate 11, and a second metal layer 16 formed in patterns at least 0.5 ∥m thick on the first metal layer, wherein the first metal layer is reduced in width by etching. Also, a third metal layer 13 may be formed in patterns on the same plane as the first metal layer. The outermost surface of the second metal layer 16 is a metal such as gold that will not be etched. The circuit board has a fine and high-resolution wiring pattern and makes it possible to realize a miniature high-performance high-output module by mounting at least one high-output semiconductor element thereon.

Abstract: An electronic component cooling apparatus is provided that can prevent a reduction in a heat dissipation effect on an electronic component with a pushing force toward a heat sink thereof being applied to the opposite wall of a casing thereof. Pushing force transferring sections 37 for transferring a pushing force from mounting tools 35 to a heat sink 3 through contact with leading ends of radiation fins 11 are integrally formed on a pair of wall sections 25a of a casing 21. The pushing force transfer sections 37 have a shape that can distribute the pushing force and transfer distributed force to the heat sink 3 so as to prevent a force applied to an electronic component MPU by the pushing force from being locally and extremely increased.

Abstract: A new method and structure is provided to create a System On Package (SOP). The process starts with a ceramic substrate that is typically used as the basis for a ceramic substrate. One or more layers of dielectric such as polyimide are deposited over the surface of the ceramic substrate, patterned and etched to created openings in the one or more layers of dielectric that align with conductive plugs that have been provided in the ceramic substrate. Passive components and metal interconnections can be created on the surface of the layers of dielectric using thin film technology. As a final step, a protective layer of dielectric is deposited over the surface of the top layer of dielectric. Active semiconductor devices may be attached to the surface of the SOP, heat sinks can be attached to the semiconductor devices. The SOP may further be mounted on the surface of a Printed Circuit Board.

Abstract: A capacitor module incorporating a ceramic capacitor having terminal members for reducing stress caused by thermal stress or electrostriction in the ceramic capacitor itself, and a semiconductor device using the capacitor module. The capacitor module and the semiconductor device are designed to have a reduced size and improved reliability.

Abstract: A semiconductor device substrate and a method of manufacturing the same by removing variations in resin thickness due to resin flows, warps in the substrate, cracking in the substrate, and foams contained in the resin.