Abstract: A package structure having a semiconductor chip embedded therein and a method of fabricating the same are disclosed. The package structure comprises: an aluminum oxide composite plate and a semiconductor chip. The aluminum oxide composite plate is formed by a stack consisting of an adhesive layer placed in between two aluminum oxide layers. The semiconductor chip having an active surface a plurality of electrode pads disposed thereon can be embedded and secured in the aluminum oxide composite plate. The present invention also comprises a method of fabricating the above-mentioned package structure. The present invention provides an excellent package structure, which can decrease the thickness of the package structure and make the package structure having characteristics of high rigidity and enduring tenacity at the same time.

Abstract: A ceramic chip assembly is provided. The ceramic chip assembly includes a ceramic base, a plurality of external electrodes, a pair of cylindrical metal lead wires, and an insulating protection material. The ceramic base has electrical characteristics of a semiconductor. The pair of external electrodes is oppositely formed on both side surfaces of the ceramic base, respectively. The cylindrical metal lead wire has one end thereof electrically and mechanically connected to the external electrodes by an electrical conductive adhesive, respectively, and has an external diameter identical to or greater than the thickness of the ceramic base. The insulating protection material includes a pair of insulating films and an insulating coating layer.

Abstract: This publication discloses a method for manufacturing an electronic module, in which manufacture commences from an insulating-material sheet (1). At least one recess (2) is made in the sheet (1) and extends through the insulating-material layer (1) as far as the conductive layer on the opposite surface (1a). A component (6) is set in the recess, with its contact surface towards the conductive layer and the component (6) is attached to the conductive layer. After this, a conductive pattern (14) is formed from the conductive pattern closing the recess, which is electrically connected from at least some of the contact areas or contact protrusions of the component (6) set in the recess.

Abstract: A wiring board (20A) includes a first wiring portion (10A) having a plurality of wiring layers (1) and external connecting bumps (5), and at least one second wiring portion (15A) having a plurality of contact plugs (14). The second wiring portion is integrated with the first wiring portion such that each terminal (14a) of the second wiring portion is in direct contact with one of the wiring layers of the first wiring portion. Hence, there is no risk to produce an internal stress caused by the diffused component of the solder bump in the junction portion between the second and first wiring portions. Accordingly, even when a semiconductor chip (30) of a low-k material is highly integrated on the wiring board, a highly reliable semiconductor device (50) can be obtained.

Abstract: A ceramic multilayer substrate exhibiting reduced pealing and breakage of an internal conductor disposed between a ceramic layer serving as a base member and a ceramic layer for restricting shrinkage includes a first ceramic layer 11, a second ceramic layer 12 laminated so as to come into contact with a principal surface of the first ceramic layer 11, and an internal conductor 13 disposed between the first ceramic layer 11 and the second ceramic layer 12, a phosphorus component layer 16a is disposed in the first ceramic layer 11 with a concentration gradient in which the concentration decreases in a direction away from the internal conductor 13.

Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

Abstract: A semiconductor module includes a multilayer substrate. The multilayer substrate includes a first metal layer and a first ceramic layer over the first metal layer. An edge of the first ceramic layer extends beyond an edge of the first metal layer. The multilayer substrate includes a second metal layer over the first ceramic layer and a second ceramic layer over the second metal layer. An edge of the second ceramic layer extends beyond an edge of the second metal layer. The multilayer substrate includes a third metal layer over the second ceramic layer.

Abstract: A deposition method modulates the reaction rate and thickness of highly conformal dielectric films deposited by forming a saturated catalytic layer on the surface and then exposing the surface to silicon-containing precursor gas and a reaction modulator, which may accelerate or quench the reaction. The modulator may be added before, after, or during exposure of the silicon-containing precursor gas. The film thickness after one cycle of deposition may be increased up to 20 times or decreased up to 20 times.

Abstract: A ceramic multilayer substrate has a ceramic laminate including a plurality of ceramic layers laminated, having a first main surface, and including internal circuit elements disposed in the inside, a resin layer having a bonding surface in contact with the first main surface of the ceramic laminate and a mounting surface opposite to the bonding surface, external electrodes, each disposed on the mounting surface of the resin layer and electrically connected to at least one of the internal circuit elements of the ceramic laminate, and a ground electrode, a dummy electrode, or capacitor electrodes disposed at an interface between the first main surface of the ceramic laminate and the bonding surface of the resin layer or in the inside of the resin layer.

Abstract: A semiconductor device and a method for producing it, and the use of the electrospinning method is disclosed. In one embodiment, delamination of the plastic housing composition from the circuit carrier can occur under loading, which can lead to the failure of the semiconductor device. For better adhesion, an adhesion-promoting layer having fibers applied by electrospinning is arranged between the circuit carrier and the plastic housing composition.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Abstract: Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.

Abstract: A semiconductor device includes an insulating substrate; at least one semiconductor element mounted on a first principal surface of the insulating substrate; and a heat radiator joined through a solder member to a second principal surface of the insulating substrate opposite to the first principal surface on which the semiconductor element is mounted. The solder member contains at least tin and antimony, and the antimony content of the solder member is in a range of from 7% by weight to 15% by weight, both inclusively. Thus, reliability of the semiconductor device is improved.

Abstract: Disclosed is a power module having improved joint reliability. Specifically disclosed is a power module including a power module substrate wherein a circuit layer is brazed on the front surface of a ceramic substrate, a metal layer is brazed on the rear surface of the ceramic substrate and a semiconductor chip is soldered to the circuit layer. The metal layer is composed of an Al alloy having an average purity of not less than 98.0 wt. % but not more than 99.9 wt. % as a whole. In this metal layer, the Fe concentration in the side of a surface brazed with the ceramic substrate is set at less than 0.1 wt. %, and the Fe concentration in the side of a surface opposite to the brazed surface is set at not less than 0.1 wt. %.

Abstract: A power semiconductor module and an inverter apparatus in which a device or a joining part is not mechanically damaged even when the temperature in use becomes a high temperature in the range of 175 to 250° C., resulting in excellent reliability at high temperature retaining test and thermal cycling test. Low thermal expansion ceramic substrates are disposed above and below the device. A material having a coefficient of thermal expansion of 10 ppm/K or less is disposed between the ceramic substrates. In addition, an inorganic material having a coefficient of thermal expansion in the range of 2 to 6 ppm/K or less is disposed around the device.

Abstract: An RF power transistor package with a rectangular ceramic base can house one or more dies affixed to an upper surface of the ceramic base. Source leads attached to the ceramic base extend from at least opposite sides of the rectangular base beneath a periphery of a non-conductive cover overlying the ceramic base. The cover includes recesses arranged to receive the one or more die, the ceramic base, gate and drain leads and a portion of the source leads. The cover further includes bolt holes arranged to clamp the ceramic base and source leads to a heat sink. Bosses at corners of the cover outward of the bolt holes exert a downward bowing force along the periphery of the cover between the bolt holes.

Abstract: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and a build-up structure mounted on the surface of the aluminum plate, the active surface of the chip, and the surface of the electrode pad, wherein the build-up structure comprises at least one conducting to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed. Therefore, the plate structure having a chip embedded therein can be processed by a simple method to achieve the tenacity of aluminum and the rigidity of aluminum oxide.

Abstract: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.

Abstract: A multilayer ceramic substrate having a cavity is formed by the steps of laminating a plurality of ceramic green sheets including ceramic green sheets having through holes corresponding to the cavity to form a multilayer body, pressing the multilayer body and firing the pressed body. At this time, a shrinkage suppression green sheet is laminated on the surface of the a ceramic green sheet constituting the outermost layer of the multilayer body, and a shrinkage suppression green sheet piece is disposed on the ceramic green sheet exposed to the bottom of the cavity in accordance with the shape of the cavity. A burnable sheet is further disposed on the shrinkage suppression green sheet piece. Before the pressing step, an embedded green sheet separate from the ceramic green sheets (portion separated by inserting a cut) is disposed on the shrinkage suppression green sheet piece or the burnable sheet so that it is filled in the cavity. After the firing step, the embedded green sheet fired is removed.

Abstract: A module with a built-in component is produced by disposing a cavity on a mounting surface side of a ceramic multilayer substrate, storing a circuit component therein and, thereafter, performing resin molding. A second resin portion is disposed on the mounting surface side of the ceramic multilayer substrate so as to continuously cover a frame-shaped portion and a first resin portion molded. External terminal electrodes are disposed on an outer surface of the second resin portion.

Abstract: A semiconductor module 10 includes a ceramic substrate having a front surface on which a semiconductor element 12 is mounted and a rear surface on the opposite side of the front surface, a front metal plate 15 joined to the front surface, a rear metal plate 16 joined to the rear surface, and a heat sink 13 joined to the rear metal plate 16. The rear metal plate 16 includes a joint surface 16b that faces the heat sink 13. The joint surface 16b includes a joint area and a non-joint area. The non-joint area includes recesses 18 which extend in the thickness direction of the rear metal plate 16. The joint area of the rear metal plate 16 is in a range from 65% to 85% of the total area of the joint surface 16b on the rear metal plate 16. As a result, excellent heat dissipating performance can be achieved while occurrence of distortion and cracking due to thermal stress is prevented.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different second ceramic material film on a first electrode; and forming a second electrode on the second ceramic material film to form a capacitor structure having the first ceramic material film and the second ceramic material film disposed between the first electrode and the second electrode, wherein the first ceramic material has a conductivity selected to dampen undesired oscillations in electrical device operation to which the capacitor structure may be exposed. An apparatus including a first electrode; a second electrode; and a composite dielectric including a plurality of dielectric films including a different Curie temperature.

Abstract: The present invention relates to a process for the deposition of protective coatings on complex shaped Si-based substrates which are used in articles and structures subjected to high temperature, aqueous environments comprises a non-line-of-sightprocess, particularly, electrophoretic deposition (EPD) process.

Abstract: An apparatus (100) is provided for dispersing heat from an integrated circuit (202) to a heat sink (404). The apparatus (100) is formed on a nonconductive body (102) having at least two conductive surfaces (110, 112) disposed thereon. One of the conductive surfaces (110) is reflowed to a heat generating lead of the integrated circuit (202), and the other conductive surface (112) provides a surface for contacting a heat sink (404). The apparatus (100) and integrated circuit provide a package (200) which can be tape and reeled (300) for easy mounting to a printed circuit board (402) of a communication device (400).

Abstract: An objective is to provide a reliability-improved semiconductor device in which heat radiation characteristics are superior, and warpage of the semiconductor device occurring due to heat generation of a semiconductor chip or to varying of the usage environment is also suppressed. The semiconductor device is provided that includes a thermal-conductive sheet 3 formed on a base board 4, including thermal-conductive resin 6, a heat sink 2 provided on the base board 4 through the thermal-conductive sheet 3, a semiconductor chip 1 mounted on the heat sink 2, and a ceramic-embedded region 31 selectively provided in a region of the thermal-conductive sheet 3 under the semiconductor chip 1, including a ceramic component 5. In this semiconductor device, superior thermal conductivity can be ensured, and warpage and peeling in the semiconductor device occurring due to heat generation of the semiconductor chip or to varying of the usage environment can also be reduced.

Abstract: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Abstract: In a ceramic circuit board 1 prepared by integrally joining a circuit layer 4 composed of a clad member including a circuit plate 2 made of an Al plate and an Al—Si brazing material layer 3 to a ceramic substrate 6, a surface of the clad member adjacent to the Al—Si brazing material layer 3 is joined to the ceramic substrate 6 with an Al alloy film 5 therebetween, the Al alloy film 5 having a thickness of less than 1 ?m and being provided on the surface of the ceramic substrate 6. According to this structure, a ceramic circuit board in which the generation of voids in the joint interface can be effectively suppressed, the joint strength of the metal member serving as the circuit layer can be increased, and the heat resistance cycle characteristics can be drastically improved, and a method for producing the same can be provided.

Abstract: A semiconductor package for surface mounting has a substrate having electrode patterns formed on both its surfaces which are electrically connected through passages such as throughholes formed through the substrate, all of these electrode patterns having a metal film formed by an electrolytic plating process. Semiconductor chips are wire-bonded onto one its surfaces (mounting surface) which is sealed with a resin layer. Lead-in wires each with one end exposed externally are included only those of the electrode patterns on the back surface of the substrate opposite its mounting surface such that the mounting surface has no lead-in wires with a part exposed externally.

Abstract: A coupling between a device and a mating part includes an elastic material and perhaps a tensioner coupled to the elastic material. The elastic material is wrapped around at least part of the device. The tensioner or other method is used to stretch the elastic material, thereby reducing the thickness of the elastic material. With the thickness of the elastic material reduced by the stretching, the device is inserted into a hole in a mating part. Then the tension on the elastic material is removed, allowing the elastic material to increase in thickness, so as to fill at least part of the gap between the device and the mating part. The coupling may act as an effective heat transfer device for transmitting (by conduction) heat produced by the heat-producing device, to the mating part, which may act as, or be thermally coupled to, a heat sink.

Abstract: The surface mount package is assembled from a ceramic base which is imprinted on its upper and lower surfaces with conductive patterns for attachment of and connection to an electronic or electromechanical device, a molded dielectric layer for forming a cavity and a seal ring. The molded dielectric is formed by aligning a dielectric preform with the base, positioning the seal ring on top of the preform, then applying a mold over the layers to shape the dielectric during a firing process that fuses the base, preform and seal ring to create a hermetic seal. The preform is of sufficient thickness that the electronic device will be fully contained within the cavity when placed into the completed package.

Abstract: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different second ceramic material film on a first electrode; and forming a second electrode on the second ceramic material film to form a capacitor structure having the first ceramic material film and the second ceramic material film disposed between the first electrode and the second electrode, wherein the first ceramic material has a conductivity selected to dampen undesired oscillations in electrical device operation to which the capacitor structure may be exposed. An apparatus including a first electrode; a second electrode; and a composite dielectric including a plurality of dielectric films including a different Curie temperature.

Abstract: A circuit device includes a ceramic substrate, an Al wiring layer provided on the ceramic substrate, and a semiconductor device and a bus bar which are electrically connected to the wiring layer. On part of the wiring layer, a Ni layer is plated. Thus a coated region in which the wiring layer is coated with nickel having solder wetability superior to aluminum and an exposing region in which the wiring layer is exposed as viewed from above the ceramic substrate are provided. The semiconductor device is connected onto the Ni layer within the coated region through solder. The bus bar is ultrasonically bonded to the wiring layer within the exposing region as viewed from above the ceramic substrate. Thus, the circuit device including the semiconductor device and the bus bar that are bonded to the ceramic substrate by sufficient bonding strength and its manufacturing method are provided.

Abstract: Affords a holder for use in semiconductor or liquid-crystal manufacturing devices—as well as semiconductor or liquid-crystal manufacturing devices in which the holder is installed—in which temperature uniformity in the processed-object retaining face is heightened. Configuring the holder with, furnished atop a ceramic susceptor, a composite of a ceramic and a metal improves the temperature uniformity in the holder's processed-object retaining face and makes for curtailing the generation of particulates and other contaminants. In addition, putting a coating on at least the retaining face improves the durability of the holder. Installing a holder of this sort in a semiconductor manufacturing device or a liquid-crystal manufacturing device contributes to making available semiconductor or liquid-crystal manufacturing devices whose productivity and throughput are excellent.

Abstract: In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the substrate to allow heat to be conducted away from the backside of the die to a top most metal layer of the substrate. Thermal balls may be attached to the bottom side of the substrate on the same plane as the die.

Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.

Abstract: In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.

Abstract: An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor material and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating layers. The wiring patterns are electrically connected via through holes formed at required positions in the interposer portions. The outer interposer portion is made of an insulator or a metal body. Further, external connection terminals are bonded to one surface of the interposer.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, and which exhibits no drop in bonding strength during panel bonding carried out after mounting of semiconductor chips, whereby reliability and productivity of a semiconductor chip mounting line is enhanced. The invention also provides a method of producing the COF flexible printed wiring board.

Abstract: A semiconductor device having a CSP packaging structure, which exhibits a reduced thermal stress exerted on a semiconductor chip without deteriorating electrical characteristics, is provided. A semiconductor device comprises an electroconductive cap, functioning as an external coupling terminal and including a metallic member and a composite material; and a semiconductor chip, having a circuit surface constituting an external electrode and a metallized surface opposite to the circuit surface, wherein the metallic member of the electroconductive cap is electrically connected to the metallized surface of the semiconductor chip via an electroconductive junction material, without a presence of the composite material therebetween.

Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.

Abstract: In a multilayer printed wiring board having a plurality of laminated resin layers, a plurality of wiring patterns formed on the interfacial surface of the resin layers, and a plurality of lands formed on the outermost layer of the resin layers and on which the solder is provided, at least one of the wiring patterns has a plurality of openings in the form of a mesh, the size of openings of the wiring patterns in a region corresponding to the position of solder in which a stress generated in the solder provided on the lands becomes a value larger than a desired value due to thermal deformation of the semiconductor device and the multilayer printed wiring board is larger than that of openings in the other regions.

Abstract: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (?m).

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

Abstract: A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: First, a melt of Al or a melt of an Al alloy containing Si is injected in a die filled with SiC powder and cast to form a plate member made of an Al/SiC composite. Next, an Al foil member made of an Al—Mg-based alloy is joined with the surface of the plate member through hot pressing. As a result, part of the Al foil member enters casting blowholes on the surface of the plate member to fill the casting blowholes. In addition, an Al—Mg-based alloy layer is formed on the surface of the plate member. Thus, a base plate having a nearly flat surface is produced.