Abstract: There is provided an aluminum/ceramic bonding substrate having a high reliability to high-temperature heat cycles. An aluminum member of an aluminum alloy having a Vickers hardness of 35 to 45 is bonded to a ceramic substrate having a flexural strength of 500 to 600 MPa in three-point bending. The ceramic substrate is made of high-strength aluminum nitride, silicon nitride, alumina containing zirconia, or high-purity alumina. The aluminum alloy is an aluminum alloy containing silicon and boron, or an aluminum alloy containing copper.

Abstract: A package substrate includes signal pads provided on a main surface of the package substrate, footpads provided on a backside of the package substrate, and a sealing electrode provided on the main surface to surround the signal pads, the signal pads being electrically coupled to the footpads, the sealing electrode being insulated from the footpads.

Abstract: A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric layer having a reinforced filling material are provided. The first dielectric layer mounted with the semiconductor chip, the support plate, and the second dielectric layer are pressed together, such that the semiconductor chip is received in the opening of the support plate, and the dielectric layers fill in a gap between the semiconductor chip and the opening of the support plate. The reinforced filling material of the dielectric layers can maintain flatness and consistency of the semiconductor chip embedded in the support plate, and fine circuits can be fabricated on the support plate by build-up and electroplating processes.

Abstract: An insulating substrate includes a metal base as a base member, an insulating layer which is a room temperature, aerosol deposited shock solidification film formed on the metal base, and a circuit pattern which is a cold sprayed thermal spray coating formed on the insulating layer. A semiconductor device incorporates the insulating substrate, and thereby has improved heat radiation characteristics.

Abstract: An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.

Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.

Abstract: A laminated wiring board comprising: a first wiring board forming wiring layers on the upper surface and on the lower surface of a first ceramic insulated substrate; and a second wiring board forming wiring layers on the upper surface and on the lower surface of a second ceramic insulated substrate; the wiring layer on the lower surface of the first wiring board and the wiring layer on the upper surface of the second wiring board being connected together through connecting electrodes; wherein a coefficient ?1 of thermal expansion of the first ceramic insulated substrate at 0 to 150° C. and a coefficient ?2 of thermal expansion of the second ceramic insulated substrate at 0 to 150° C. are satisfying the following conditions: ?1<?2 ?2??1?9×10?6/° C.

Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).

Abstract: A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage structures.

Abstract: A semiconductor component that is able to be produced simply, quickly, and yet reliably and that usable for power applications, and including a semiconductor chip, a lower, first main electrode layer formed on a first side of the semiconductor chip, a lower control electrode layer formed on the first side, an insulation layer formed on the first side between the lower first main electrode layer and the lower control electrode layer and which partly covers the lower first main electrode layer, an upper first main electrode layer which is formed on the lower first main electrode layer, an upper control electrode layer which is formed on the lower control electrode layer and the insulation layer and extends on the insulation layer partially above the lower first main electrode layer, and a second main electrode layer formed on a second side of the semiconductor chip.

Abstract: In a composite device of the laminate type having a laminate structure of a composite ceramic layer and a dielectric ceramic layer, the composite ceramic layer including a layer portion having the same composition as the dielectric ceramic layer and a plurality of particle portions formed on the surface of the layer portion. The particle portions are made from magnetic ceramic material. This prevents the ceramic layers of the device from cracking and separating when fired.

Abstract: A method of fabricating a thin film transistor array substrate is provided.

Abstract: A protective disk for protecting a semiconductor wafer during processing includes an adhesive layer configured to adhere to the semiconductor wafer and a support layer coupled to the adhesive layer configured to provide strength and stiffness to the semiconductor wafer during processing. In one aspect of the invention, the protective disk is soluble in a mildly alkaline or mildly acidic solution. In another aspect, the adhesive layer comprises a high molecular weight polymer. In another aspect, the support layer comprises a polymer and a filler. The present invention may enable a robust, cost-effective, high-volume, automated process for thinning semiconductor wafers below 150 ?m, and for subsequent process steps of stress relief and transfer to a dicing frame for die singulation. Additionally, the invention enables use of existing toolsets and processes to produce thinner substrates than conventionally achievable.

Abstract: A multilayer ceramic circuit board comprises a core of high conductivity material such as metal and an overlying layer of electrically insulating ceramic having an outer surface. In accordance with the invention, a circuit board for receiving a high power component is provided with a thermal spreading layer on or near the outer surface and one or more thermal vias through the ceramic to thermally couple the spreading layer to the core. The vias and the spreading layer comprise electrically insulating thermally conductive materials. The resulting structure provides rapid heat dissipation for a high power component formed or mounted on or near the spreading layer.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.

Abstract: A laminated radiation member includes a radiation plate, an insulation substrate bonded to the upper surface of the radiation plate and an electrode provided on the upper surface of the insulation substrate. The laminated radiation member is made by a method including the steps of surface treating a bonding surface of the radiation plate and/or the insulation substrate, interposing ceramic particles surface treated to assure wettability with a hard solder or a metal between the radiation plate and the insulation substrate, disposing a hard solder above and/or below the ceramic particles, heating the hard solder to a temperature higher than the melting point of the solder, penetrating the molten hard solder into spaces between the ceramic particles to react the ceramic particles with the solder to produce a metal base composite material, and bonding the radiation plate and the insulation substrate with the metal base composite material.

Abstract: A packaging substrate is formed of an array of packaging units. Each packaging unit includes a chip pad on which a chip is carried, a plurality of pins arranged around the chip pad and spaced from one another and the chip pad by an open space, an insulative member filling up the open space and forming with the pins and the chip pad a platform, and lead wires located at the insulative member for connecting pins directly or through a passive component.

Abstract: An electronic component arrangement includes a discrete electronic component having first and second terminals and a centre-exposed pad. A substrate has a first electrical conductor electrically connected to the first terminal, a second electrical conductor electrically connected to the second terminal, and a third electrical conductor. A thermally conductive element is in direct thermal communication with both the centre-exposed pad of the electronic component and the third electrical conductor of the substrate.

Abstract: An electrical component includes a base having at least a first ceramic section and a second ceramic section. The first ceramic section and the second ceramic section include different materials, which have resistances with negative temperature coefficients. The component also includes first and second contact layers on the base. The first and second ceramic sections are between the first and second contact layers. A plurality of stacks of electrically conductive electrode layers are arranged inside the base. Stacks of electrode layers are electrically connected to the first and second contact layers.

Abstract: This invention relates to the manufacture of a substrate, such as a package substrate or an interposer substrate, of an integrated circuit package. A base structure is formed from a green material having a plurality of via openings therein. The green material is then sintered so that the green material becomes a sintered ceramic material and the base structure becomes a sintered ceramic base structure having the via openings. A conductive via is formed in each via opening of the sintered ceramic base structure. A capacitor structure is formed on the sintered ceramic base structure. The power and ground planes of the capacitor structure are connected to the vias. As such, a capacitor structure can be formed and connected to the vias without the need to drill vias openings in brittle substrates such as silicon substrates.

Abstract: Aspects of the invention provide a package for accommodating a piezoelectric resonator that can include more mounting electrodes than connecting electrodes of the piezoelectric resonator element. The mounting electrodes can be electrically connected with a wiring pattern. In the lower surface of a package body, there can be formed external terminals at the four corners thereof. The external terminals are bonded to a mounting board. The external terminals are electrically connected to the mounting electrodes, respectively. The external terminal is not connected electrically to either of the mounting electrodes. Therefore, positions of the external terminals for operating the piezoelectric resonator can be changed based on whether a pair of connecting electrodes of the piezoelectric vibration element is bonded to the mounting electrodes, or it is connected to the mounting electrodes. Accordingly, it can be possible to easily change positions of external terminals for connecting to a circuit on a board.

Abstract: This application discloses an apparatus comprising a substrate including a plurality of conducting layers and a nanocomposite inter-layer dielectric (ILD) sandwiched between the conducting layers, wherein the nanocomposite ILD layer comprises a nanocomposite including a polymer having a plurality of nanoclay particles dispersed therein, the nanoclay particles having a high aspect ratio. Also disclosed is an apparatus comprising a substrate having a contact surface and a nanocomposite solder resist layer placed on the contact surface, wherein the solder resist comprises a nanocomposite including a polymer binder having a plurality of nanoclay particles dispersed therein, the nanoclay particles having a high aspect ratio.

Abstract: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.

Abstract: A structural configuration and manufacture method is applied to manufacture electronic circuits on a ceramic substrate including capacitor and inductors for filters. The electronic circuits have strong bonding to securely adhere to the SOG-coated substrate when the SOG is cured at an elevated temperature supplemented with high nitrogen flow during the curing process. The SOG coated ceramic substrate shows excellent layer compatibilities during temperature variations because reduced differences of thermal coefficients between different layers.

Abstract: A ceramic package and a chip resistor obtained by forming, on a plastic ceramic green sheet comprising 100 parts by weight of a ceramic powder mainly composed of borosilicate glass, into which 10 to 30 parts by weight of an acrylic copolymer obtained by polymerizing 100 parts by weight of a (meth)acrylic acid ester and 1 to 10 parts by weight of a monomer having a functional group of a hydroxyl group, acid amide group, or amino group and having a Tg in the range of ?30° C. to +10° C. is compounded, a conductor layer using a plastic conductive paste obtained by compounding, into 100 parts by weight of a conductive powder, 5 to 20 parts a mixture of an acrylic copolymer having a Tg of not more than ?30° C. and an ethylcellulose-based binder, press forming the resultant single layer of ceramic green sheet, and calcining the resultant ceramic green sheet having the integrally formed bottom, opening and opening circumferential edge and a method for producing the same.

Abstract: A surge absorber includes a laminated compact of a first ceramic green sheet having a first internal electrode film extending to both sides thereof, a second ceramic green sheet having an second internal electrode film extending to both end surfaces thereof, and a third ceramic green sheet having a discharge hole. Ground external electrode layers are provided on both sides of the laminate so as to be connected with both ends of the first internal electrode film, and signal external electrode layers are further provided on both end surfaces of the laminated compact so as to be connected with both ends of the second internal electrode film. The laminated compact may also include a resistance element.

Abstract: A chip package is made with the ring or dish interposer and an embedded array capacitor. A computing system is also disclosed that includes the ring or dish interposer and the embedded array capacitor.

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Abstract: An improved back end of the line (BEOL) interconnect structure comprising an ultralow k (ULK) dielectric is provided. The structure may be of the single or dual damascene type and comprises a dense thin dielectric layer (TDL) between a metal barrier layer and the ULK dielectric. Disclosed are also methods of fabrication of BEOL interconnect structures, including (i) methods in which a dense TDL is provided on etched opening of a ULK dielectric and (ii) methods in which a ULK dielectric is placed in a process chamber on a cold chuck, a sealing agent is added to the process chamber, and an activation step is performed.

Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.

Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, a plurality of conductive wires and an insulating material is provided. The substrate has a first surface and a corresponding second surface. The substrate has a slot that penetrates the substrate. The chip is attached to the first surface of the substrate in a position that covers the slot. The conductive wires pass through the slot such that one end of each conductive wire is attached to a contact point on the chip while the other end of the conductive wire is attached to a contact point on the second surface of the substrate. The insulating material fills the space between the chip and the substrate and the slot so that the conductive wires and the bumps are enclosed.

Abstract: A semiconductor-producing/examining device that can maintain a preferable connection state for a predetermined period of time and that can easily remove a ceramic substrate from a supporting case. The semiconductor producing/examining device includes a ceramic substrate having a conductor layer formed on the surface thereof or inside thereof and a supporting case. An external terminal is connected to the conductor layer. A connection between the conductor layer and the external terminal is performed such that the external terminal is pressed on the conductor layer or the external terminal is pressed on another conductor layer connected to the conductor layer by using the elastic force and the like of an elastic body.

Abstract: A semiconductor built-in millimeter-wave band module includes: an insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a high thermal conductivity substrate made of a dielectric material having thermal conductivity higher than the insulating substrate and laminated on one surface of the insulating substrate; a plurality of wiring patterns formed on the high thermal conductivity substrate and the insulating substrate; a semiconductor device operating at millimeter-wave band, which is arranged inside of the insulating substrate, is packaged on the high thermal conductivity substrate in a face-up manner, and is connected electrically with the wiring patterns; and a distributed constant circuit element and an active element provided on the semiconductor device. In this module, a void is provided inside of the insulating substrate and in the vicinity of a surface of the distributed constant circuit element and the active element.

Abstract: A semiconductor device including a substrate, a semiconductor element mounted on the substrate and a stiffener attached via an adhesive to a surface of the substrate opposite a surface thereof on which the semiconductor element is mounted. The adhesive has a coefficient of thermal expansion smaller than that of the substrate and that of the stiffener, and the modulus of longitudinal elasticity of the adhesive is equal to or larger than 10 GPa. Otherwise, the adhesive has a coefficient of thermal expansion larger than that of the substrate and that of the stiffener, and the modulus of longitudinal elasticity of the adhesive is equal to or smaller than 10 GPa. The height of the stiffener is less than that of the external terminals.

Abstract: A structure and method are provided for dissipating heat from a semiconductor device chip. A first layer of a dielectric material (e.g. polyimide) is formed on a front side of a heat spreader (typically Si). A plurality of openings are formed through this first layer; the openings are filled with metal (typically Cu), thereby forming metal studs extending through the first layer. A second layer of metal is formed on the backside of the device chip. The first layer and the second layer are then bonded in a bonding process, thereby forming a bonding layer where the metal studs contact the second layer. The bonding layer thus provides a thermal conducting path from the chip to the heat spreader.

Abstract: A phased-array antenna system and other types of radio frequency (RF) devices and systems using microelectromechanical switches (“MEMS”) and low-temperature co-fired ceramic (“LTCC”) technology and a method of fabricating such phased-array antenna system and other types of radio frequency (RF) devices are disclosed. Each antenna or other type of device includes at least two multilayer ceramic modules and a MEMS device fabricated on one of the modules. Once fabrication of the MEMS device is completed, the two ceramic modules are bonded together, hermetically sealing the MEMS device, as well as allowing electrical connections between all device layers. The bottom ceramic module has also cavities at the backside for mounting integrated circuits. The internal layers are formed using conducting, resistive and high-k dielectric pastes available in standard LTCC fabrication and low-loss dielectric LTCC tape materials.

Abstract: A semiconductor device includes a semiconductor constructing body which has a semiconductor substrate, a plurality of external connection electrodes formed on the semiconductor substrate, and heat dissipation columnar electrodes. Upper interconnections are mounted on one side of the semiconductor constructing body and connected to the external connection electrodes of the semiconductor constructing body. A heat dissipation layer is mounted on one side of the semiconductor constructing body and made of the same material as that of the upper interconnections.

Abstract: The present invention provides a package substrate which comprises a substrate defined by top and bottom surfaces and having a plurality of perforations; a resin insulation layer configured to implement a multi-level structure disposed on both surfaces of the substrate; a built-up wiring layer implementing the multi-level structure disposed on the resin insulation layer on both surfaces of the substrate; and a semiconductor chip mounting region provided on the top or the bottom surface of the substrate; wherein, a perforation exists on any straight line connecting from the center of the substrate to an arbitrary point on a periphery of the substrate.

Abstract: A method and apparatus for a backsided and recessed optical package connection is described. The method includes the formation of a substrate having a top surface layer and an opposed layer, including one or more recessed portions. Following formation of the substrate, leads of a lead unit are coupled to one or more of the recessed portions of the substrate. Next, one or more optical electronic components are mounted onto the top surface of the substrate. Once the optoelectric components are mounted to the top surface of the substrate, a cap is attached to the top surface of the substrate to encapsulate the one or more optical electronic components and form an optoelectronic package.

Abstract: The present invention relates to a power module in which an insulated circuit board is fixed to one main surface of a heat discharge plate. It is an object thereof to provide a power module in which the heat discharge characteristics are improved without any marked warping being generated, and that has an extended heat cycle longevity. In the power module 10 of the present invention, a square insulated circuit board 12 is fixed to one main surface of a heat discharge plate 11. The heat discharge plate 11 is formed of an Al based alloy plate having a thickness A of 3 to 10 mm, and the insulated circuit board 12 having a side B of 30 mm or less in length is brazed directly onto the heat discharge plate 11. It is-preferable that the brazing material used is one or two or more brazing materials selected from Al—Si, Al—Ge, Al—Cu, Al—Mg, and Al—Mn based brazing materials.

Abstract: A multilayer ceramic substrate in which an outer metal pad is anchored to the substrate by a single metal-filled via in the first ceramic layer adjacent to the metal pad. In turn, this single metal-filled via is anchored to the substrate by a larger, single metal-filled via in the next ceramic layer adjacent to the first ceramic layer. Preferably, the metal-filled vias and metal pad are 100 volume percent metal.

Abstract: A ceramic multilayer substrate includes a plurality of ceramic substrates being stacked vertically, each substrate having a designated thickness; pattern layers formed on surfaces of the ceramic substrates so as to form circuit elements; external terminal vertically formed on side surfaces of the stacked ceramic substrates; and internal connection parts, each of which is formed on a part of one of the pattern layers, is connected to one of the external terminals so as to exchange signals with the outside, and is broad enough to surround at least partially the connected external terminal.

Abstract: A method for preparing a non-thermal plasma reactor substrate includes disposing electrical vias on green stage first and second ceramic plates; filling the electrical vias with conductive material; and forming electrical contact via cover pads; disposing conductive material on the first ceramic plate to form an electrode plate having a main electrode portion and a terminal lead for electrically connecting the main electrode portion to the electrical vias; laminating the electrode plate and the second ceramic plate together, embedding the electrode therebetween; co-firing the plates to form a laminated co-fired embedded-conductor element; stacking a plurality of the laminated co-fired embedded-conductor elements to form a multi-cell stack, the filled electrical vias aligning in the stack to provide an electrical bus for connecting alternating elements in the stack; and disposing spacers with matching vias and via cover pads between adjacent pairs of elements to form exhaust gas passages.

Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.

Abstract: A hermetically sealed, opto-electronic array housing assembly having a ceramic base, electrical connectors, a metal can, and a glass window. The glass window can support a micro-lens array. The metal can receives the glass window. The electrical impedance of the electrical connectors is beneficially carefully controlled to enable high-speed data communications. A multi-element optical fiber connector can provide for optical communications to and/or from an opto-electronic array contained within the housing.

Abstract: An insulating ceramic composition includes a mixture of a ceramic powder containing MgAl2O4 and a glass powder containing 30-60% by mole of silicon oxide on the basis of SiO2 and 20-55% by mole of magnesium oxide on the basis of MgO, and the ceramic powder further includes Mg2SiO4 and TiO2. The insulating ceramic composition can be fired at 1000° C. and co-sintered with Ag and Cu. An insulating ceramic obtained by sintering the insulating ceramic composition has a high Q-factor and is therefore suitable for ceramic multilayer substrates used at high frequencies.

Abstract: A ball grid array electronic package is attached to a substrate by means of solder balls and solder paste. Connection is made between a contact on the ball grid array and a solder ball by means of a first joining medium, such as a solder paste. Connection is made between a solder ball and a contact arranged on the substrate by means of a second joining medium. The contact arranged on the substrate is substantially quadrilateral in shape, and preferably substantially square in shape. Connection to the substrate, e.g., using round solder balls, is much more easily detected, e.g., by x-ray, than when using round pads, especially those having a smaller diameter than the balls.

Abstract: The invention provides a surface mounting type electronic circuit unit that is suitable for miniaturization. Thin film circuit elements including capacitors, resistors, and inductance elements are formed on an alumina substrate, a semiconductor bare chip of a diode and a transistor is fixed by means of wire bonding, and part of the capacitors is formed non-rectangular having rectangles projected from one side of another rectangle.

Abstract: The invention relates to an electronic component including a housing and a first substrate having at least one integrated circuit, a multiplicity of contact surfaces arranged in an arbitrary distribution on the surface of the first substrate. A second substrate forms a housing and is mechanically joined to the surface of the first substrate in a surface-to-surface contact, via an insulating joining layer. The second substrate has contact connection surfaces that are surface-to-surface connected to the contact surfaces of the first substrate in an electrically conductive manner. The second substrate has symmetrically arranged external contact surfaces that are conductively connected to the contact connection surfaces via through-contacts in the second substrate.

Abstract: A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.