With Heat Sink Patents (Class 257/706)
  • Patent number: 11462476
    Abstract: An electronic device is disclosed. In an embodiment an electronic device includes at least one first carrier and at least one semiconductor chip, wherein the first carrier has a cavity in which the semiconductor chip is arranged.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 4, 2022
    Assignee: TDK ELECTRONICS AG
    Inventors: Thomas Feichtinger, Johann Pichler, Nele Reimer, Markus Koini, Manfred Schweinzger
  • Patent number: 11437296
    Abstract: A semiconductor package in an aspect of the present invention includes a metal board, a first frame, a second frame, and a bond. The metal board has an upper surface including a mount on which a semiconductor device is mountable. The first frame has a side surface facing a side surface of the metal board and has a smaller thermal expansion coefficient than the metal board. The second frame is on upper surfaces of the metal board and the first frame and surrounds the mount, and has a smaller thermal expansion coefficient than the metal board. The bond is between the metal board and the first frame, between the metal board and the second frame, and between the first frame and the second frame. The semiconductor package includes an alloy layer between the metal board and the bond.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 6, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Hiroshi Matsumoto, Hiroki Ito, Takashi Kimura
  • Patent number: 11417630
    Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Digvijay A. Raorane, Ravindranath Vithal Mahajan, Mitul Bharat Modi
  • Patent number: 11404346
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 2, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Kyu Kim, Jung-Ho Park, Jong Youn Kim, Yeon Ho Jang, Jae Gwon Jang
  • Patent number: 11398414
    Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chia-Pin Chiu, Pooya Tadayon, Joe F. Walczyk, Chandra Mohan Jha, Weihua Tang, Shrenik Kothari, Shankar Devasenathipathy
  • Patent number: 11367669
    Abstract: A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including electrodes on a front surface side and a back surface side thereof; and a graphite plate having an anisotropic thermal conductivity, the graphite plate of which one end is connected to the front surface side of the semiconductor device and the other end is connected to the insulating substrate, wherein heat of the front surface side of the semiconductor device is transferred to the insulating substrate through the graphite plate. There is provide an inexpensive power module capable of reducing a stress and capable of exhibiting cooling performance not inferior to that of the double-sided cooling structures.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 21, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Maiko Hatano, Takukazu Otsuka, Hirotaka Otake, Tatsuya Miyazaki
  • Patent number: 11330706
    Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a component embedded in the stack so that a gap of less than 100 ?m, in particular less than 60 ?m, remains between at least one sidewall of the component and a sidewall of an adjacent one of the layer structures or a further component embedded in the stack; and a filler medium including filler particles, wherein the filler medium at least partially fills the gap. In addition, a method of manufacturing a component carrier is provided.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 10, 2022
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Seok Kim Tay, Mikael Tuominen
  • Patent number: 11302597
    Abstract: A semiconductor device is provided with a heat dissipating face side skirt portion, which is a frame-form projection, on a heat dissipating face of a lead frame. Because of this, creepage distance increases with a small increase in an amount of resin, and insulating properties improve. Also, the heat dissipating face side skirt portion is molded via two transfer molding steps, wettability of the second molding resin with respect to a first molding resin and the lead frame increases, and adhesion improves. Furthermore, an end face of an inner lead is exposed in an element sealing portion on a mounting face side, and covered with a second thin molded portion molded using the second molding resin, whereby heat generated in a semiconductor element can efficiently be caused to escape from faces of both a first thin molded portion and the second thin molded portion, because of which heat dissipation improves.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanobu Kajihara, Katsuhiko Omae, Takashi Nagao, Masayuki Funakoshi, Norio Emi, Atsuki Fujita, Yuki Okabe
  • Patent number: 11297727
    Abstract: A power electronic component including a surface adapted to be attached to a heatsink, the surface forming a bottom surface of the power electronic component, one or more power electronic semiconductor chips mounted on a substrate above the bottom surface, and a housing enclosing the one or more power electronic semiconductor chips. The power electronic component includes a thermal insulator disposed above the one or more power electronic semiconductor chips, such that the bottom surface and the thermal insulator are on the opposite sides of the one or more power electronic semiconductor chips.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 5, 2022
    Assignee: ABB Schweiz AG
    Inventors: Jorma Manninen, Mika Silvennoinen, Joni Pakarinen
  • Patent number: 11289398
    Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°<?<90°. The heat spreader is disposed over the substrate, wherein the semiconductor device is disposed between the heat spreader and the substrate. The adhesive layer is surrounding the semiconductor device and attaching the heat spreader onto the substrate, wherein the adhesive layer has a first opening misaligned with one of corners of the semiconductor device closest to the first opening.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Patent number: 11276628
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 15, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Cristina Somma
  • Patent number: 11264304
    Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Liang Chen, Chi-Yang Yu, Kuan-Lin Ho, Yu-Min Liang
  • Patent number: 11264301
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • Patent number: 11258270
    Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 22, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
  • Patent number: 11244875
    Abstract: A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasutaka Shimizu
  • Patent number: 11239182
    Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via thin film deposition (TFD) instrumentation and techniques in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 1, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Richard Korneisel, Nathaniel P. Wyckoff, Brandon C. Hamilton, Jacob R. Mauermann, Carlen R. Welty
  • Patent number: 11239224
    Abstract: A power conversion device provided with a switching circuit unit including a plurality of upper-arm switching elements connected to positive electrode wiring and a plurality of lower-arm switching elements connected to negative electrode wiring. The power conversion device includes a first semiconductor module incorporating a plurality of the upper-arm switching elements connected together in parallel, a second semiconductor module incorporating a plurality of the lower-arm switching elements connected together in parallel, and a third semiconductor module incorporating the upper-arm switching elements connected together in series and the lower-arm switching elements connected together in series.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 1, 2022
    Assignee: DENSO CORPORATION
    Inventors: Kazuma Fukushima, Yuu Yamahira, Ryota Tanabe, Tetsuya Matsuoka, Kosuke Kamiya, Taijiro Momose
  • Patent number: 11201130
    Abstract: A semiconductor device includes a base plate; a metal plate above the base plate; a bonding material between the base plate and metal plate, bonding the metal plate to the base plate; an insulating plate on the metal plate; a circuit member on the insulating plate; a semiconductor element mounted on the circuit member; and a sealing material to seal a space on the base plate. The metal plate includes a bottom surface area along a periphery, exposed from the bonding material. The base plate includes a groove-shaped first recess formed along the periphery of the metal plate and faces the bottom surface area. The base plate also includes a groove-shaped second recess that is spaced apart from the first recess and that is formed on the inner side relative to the first recess. The bonding material is disposed in at least a part of the second recess.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 14, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hirotaka Oomori, Takashi Tsuno
  • Patent number: 11195740
    Abstract: An assembly comprising a device wafer received in a recess of a carrier wafer. A device wafer comprising a protrusion terminating at an active surface bearing integrated circuitry, the protrusion surrounded by a peripheral flat extending to an outer periphery of the device wafer. A method of wafer thinning using the previously described carrier wafer and device wafer. Various implementations of a carrier wafer having a recess are also disclosed, as are methods of fabrication.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Kyle K. Kirby
  • Patent number: 11177189
    Abstract: A module includes a substrate, a first component on a first main surface of the substrate and from which heat is to be dissipated, a sealing resin layer that encloses the first component, and a heat-dissipating member that includes a first and a second heat-dissipating portions. The first heat-dissipating portion is disposed in the sealing resin layer, spaced apart from an upper surfaces of the first component, and includes a first overlap portion that overlaps an upper surfaces of the first component when viewed in plan in a direction perpendicular to the first main surface. The second heat-dissipating portion extends from an undersurface of the first overlap portion to the upper surface of the first component. An area of the second heat-dissipating portion on a surface of the first overlap portion including the undersurface is smaller than an area of the first overlap portion.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Yoshitaka Matsukawa
  • Patent number: 11171073
    Abstract: The present disclosure relates to a switching semiconductor device and a cooling apparatus thereof. The cooling apparatus of the switching semiconductor device of the present disclosure comprises a first heat dissipation plate configured to facilitate heat dissipation of a surface of the semiconductor device at an installation space, and a second heat dissipation plate disposed inside the installation space along a thickness direction of the first heat dissipation plate. The installation space is formed in a predetermined size at the surface of the semiconductor device, and the second heat dissipation plate is configured to contact the first heat dissipation plate so as to allow heat exchange. Accordingly, a heat dissipation area may be increased without increasing a size of the installation space.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 9, 2021
    Assignee: LG Electronics Inc.
    Inventors: Kyeonghwan Kim, Junho Ahn
  • Patent number: 11171072
    Abstract: A heat dissipation substrate includes a substrate, a heat conducting element, an insulating filling material, a first circuit layer, and a second circuit layer. The substrate has a first surface, a second surface opposite the first surface, and a through groove communicating the first surface with the second surface. The heat conducting element is disposed in the through groove. The heat conducting element includes an insulating material layer and at least one metal layer. The insulating filling material is filled in the through groove for fixing the heat conducting element into the through groove. The first circuit layer is disposed on the first surface of the substrate and exposes a portion of the heat conducting element. The second circuit layer is disposed on the second surface of the substrate. The first circuit layer and the metal layer are respectively disposed on two opposite sides of the insulating material layer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 9, 2021
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chien-Hung Wu, Bo-Yu Huang, Chia-Wei Chang, Tzu-Shih Shen
  • Patent number: 11139253
    Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chui Woo Kim, Sang Min Yong, Yang Gyoo Jung
  • Patent number: 11094913
    Abstract: A flexible organic light emitting diode (OLED) display panel is provided, including: a flexible base and an organic light emitting layer, a thin film encapsulating layer, a polarizer, a glass cover, and a sealing, heat-dissipation glue sequentially formed on the flexible base. The sealing, heat-dissipation glue is formed on sidewalls of the OLED display panel to prevent moisture from entering into the OLED display panel. The sealing, heat-dissipation glue includes heat absorbing particles; the heat absorbing particles are configured for absorbing heat generated by the OLED display panel.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 17, 2021
    Inventor: Xuesi Qin
  • Patent number: 11062970
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Patent number: 11039537
    Abstract: An electronic component embedded substrate includes a core member including a first wiring layer, a first insulating layer covering the first wiring layer and having a first through-portion, a second wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and having a second through-portion exposing at least a portion of the second wiring layer; a first electronic component disposed in the first through-portion; a second electronic component disposed in the second through-portion; and an insulating resin covering at least a portion of each of the first electronic component and the second electronic component. The second wiring layer includes a first wiring pattern having a portion covered with the second insulating layer, and a second wiring pattern having a portion covered with the insulating resin. The second electronic component is connected to the second wiring pattern.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Yoon Lee, Tae Seong Kim
  • Patent number: 11011448
    Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
  • Patent number: 11008424
    Abstract: Disclosed are exemplary embodiments of systems and methods for controllably changing (e.g., weaken, strengthen, eliminate, add, customize, alter, etc.) surface tack of thermal interface materials. Also disclosed are exemplary embodiments of thermal interface material assemblies, which include coatings configured to change surface tack of the thermal interface materials.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 18, 2021
    Inventors: Jingbo Shen, Mandy Feng, Jingqi Zhao
  • Patent number: 11004776
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 11, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Rammil Seguido
  • Patent number: 10974360
    Abstract: A first diamond layer made of polycrystalline diamonds and doped with foreign atoms, is arranged on a metal surface of a machining tool, and is used to detect the degree of wear of an undoped polycrystalline second diamond layer, which is arranged on the doped diamond layer and forms a functional region of the machining tool, wherein at least one physical parameter is detected continuously or periodically during operation of the tool, and wherein a change in the parameter indicates the degree of wear of the undoped second diamond layer. The doped diamond layer forms an “intelligent stop layer” for the tool because as a result of change in the transition from the undoped to the doped layer, the conductivity of the system changes, for example, and this change can be used to form a stop signal for the machine drive before the tool and the machined workpiece are damaged.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 13, 2021
    Assignee: Guehring KG
    Inventor: Immo Garrn
  • Patent number: 10969840
    Abstract: Disclosed herein are embodiments of heat spreaders with interlocked inserts, and related devices and methods. In some embodiments, a heat spreader may include: a frame formed of a first material, wherein the frame includes an opening, a projection of the frame extends into the opening, and the projection has a top surface, a side surface, and a bottom surface; a recess having at least one sidewall formed by the frame; and an insert formed of a second material different from the first material, wherein the insert is disposed in the frame and in contact with the top surface, the side surface, and the bottom surface of the projection.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Aravindha R. Antoniswamy, Syadwad Jain, Zhizhong Tang, Wei Hu
  • Patent number: 10950520
    Abstract: An electronic package is provided. A heat dissipator is bonded via a thermal interface layer to an electronic component disposed on a carrier. The heat dissipator has a concave-convex structure to increase a heat-dissipating area of the thermal interface layer. Therefore, the heat dissipator has a better heat-dissipating effect.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Wen-Shan Tsai, En-Li Lin, Kaun-I Cheng, Wei-Ping Wang
  • Patent number: 10893616
    Abstract: Disclosed is a production method of a multi-layered printed wiring board, including the following steps 1 to 3: Step 1: a step of laminating, on a substrate with inner layer circuit, a metal foil with adhesive layer including a support, a metal foil having a thickness of 3 ?m or less and ? or less relative to the thickness of the inner layer circuit, and an organic adhesive layer having a thickness of 10 ?m or less in this order, via an organic insulating resin layer such that the organic insulating resin layer and the organic adhesive layer are opposed to each other, and then releasing the support to form a laminated sheet (a) having the metal foil as an outer layer metal foil layer; Step 2: a step of irradiating the laminated sheet (a) with a laser to bore the outer layer metal foil layer, the organic adhesive layer, and the organic insulating resin layer to form a bored laminated sheet (b) having a blind via hole; and Step 3: a step of forming an outer layer circuit connected with the inner layer circui
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: January 12, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Hitoshi Onozeki, Tsubasa Inoue, Katsuji Yamagishi, Hiroshi Shimizu
  • Patent number: 10881030
    Abstract: An example electrical and liquid coolant midplane includes an electrical midplane having a ring bus bar assembly, a liquid coolant manifold, and a heat transfer device. The ring bus bar assembly is to receive power from power supply units of the computing system and provide the power to computing components installed in the computing system. The liquid coolant manifold includes four segments connected together as a rectangular ring, the liquid coolant manifold including first liquid connectors facing in a first direction and second liquid connectors facing in a second direction opposite the first direction. The heat transfer device is in contact with the ring bus bar assembly and one of the segments of the liquid coolant manifold, to thermally couple the ring bus bar assembly with the manifold to provide liquid cooling to the ring bus bar assembly.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 29, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Harvey J. Lunsman, Steven Dean, Mike Kubisiak, Michael Scott, Robert Mascia
  • Patent number: 10879192
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan
  • Patent number: 10847437
    Abstract: An object is to provide a technique capable of increasing a heat radiation property in radiating a heat generated in a shunt resistance. A semiconductor device includes: a container body having a space with an opening; a semiconductor chip, a shunt resistance, and a circuit pattern disposed in the space in the container body; a partition member; a first cover; and a second cover. The partition member separates the space in the container body into a first space and a second space. The first cover covers a part of the opening corresponding to the first space, and the second cover covers a part of the opening corresponding to the second space. At least one hole through which the second space and outside of the container body are communicated with each other is formed in the second cover or by the second cover.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daichi Otori
  • Patent number: 10818569
    Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: October 27, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Se Man Oh, Kyoung Yeon Lee, Sang Hyeon Lee, Min Cheol Shin
  • Patent number: 10818704
    Abstract: Disclosed is a method for manufacturing a thin film transistor, and a thin film transistor, relating to the technical field of liquid crystal display.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: October 27, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Songshan Li
  • Patent number: 10796978
    Abstract: A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard McVicker, Sri M. Sri-Jayantha
  • Patent number: 10775028
    Abstract: A complex device that integrates a beam shaping aperture in a printed circuit board of the complex device (e.g., scanner or barcode reader or optical module) is provided. The complex device has a light-emitting diode pattern projection system. The pattern projection system includes one or more light-emitting diodes and a printed circuit board. The printed circuit board has one or more apertures and one or more receptacles. The one or more receptacles are positioned behind the aperture and receive the one or more light-emitting diodes. The printed circuit board with receptacle offer self-alignment for the light emitting diodes. The beam shaping aperture in front of the light-emitting diodes allows light to pass through the aperture that is part of the printed circuit board layer of the complex device.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: September 15, 2020
    Assignee: DATALOGIC IP TECH S.R.L.
    Inventors: Federico Canini, Anna Guagliumi, Davide Bottazzi
  • Patent number: 10777965
    Abstract: Provided is a laser apparatus and a light source apparatus that can reduce the footprint and realize space-saving. The laser apparatus has a bottom plate; a semiconductor laser element mounted on the bottom plate; and a terminal unit that is provided so as to face upward with respect to the bottom plate and enables external electrical connection.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 15, 2020
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yuta Ishige, Etsuji Katayama, Atsushi Oguri, Hajime Mori
  • Patent number: 10763231
    Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dibyajat Mishra, Ashok Prabhu, Tomoko Noguchi, Luu Thanh Nguyen, Anindya Poddar, Makoto Yoshino, Hau Nguyen
  • Patent number: 10764989
    Abstract: An integrated circuit package having excellent heat dissipation is described. An integrated circuit die is attached to a substrate and the substrate is mounted on a printed circuit board (PCB) wherein there is a gap between a surface of the die facing the PCB and the PCB. A thermal enhanced layer is formed within the gap wherein heat travels from the die through the thermal enhanced layer to the PCB.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 1, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Tung Ching Lui, Baltazar Canete, Rajesh Aiyandra
  • Patent number: 10756002
    Abstract: A packaged device, having a package, including a first dissipative region, a second dissipative region, a first connection element and a second connection element. A die of semiconductor material is arranged within the package, carried by the first dissipative region. The first and second dissipative regions extend at a distance from each other, and the first and second connection elements extend at a distance from each other between the first and second dissipative regions. The first dissipative region, the second dissipative region, the first connection element, and the second connection element are hollow and form a circuit containing a cooling liquid.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 25, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cristiano Gianluca Stella, Francesco Salamone
  • Patent number: 10745561
    Abstract: A filler for a heat transfer member includes: a core material which is made of an inorganic material or metal material having a thermal conductivity of 15 W/mK or more, and transfers heat; and an insulating film which includes a silicon oxide film and a diamond-like carbon film having electrical insulation properties, and covers the core material. The dielectric breakdown voltage of the filler is 500 V or more.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 18, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Koji Nakanishi
  • Patent number: 10741465
    Abstract: A circuit module (301) includes a first substrate (201), a first module (101), a sealing resin portion (3), and a conductive material film (7). The first substrate (201) has a first principal surface (201a). The first module (101) is mounted on the first principal surface (201a). The sealing resin portion (3) is formed on the first principal surface (201a) and covers the first module (101). The conductive material film (7) covers a side of the sealing resin portion (3). The first module (101) includes a conductive material portion and a device which may produce heat and which is mounted on the conductive material portion. The conductive material portion connects with the conductive material film (7) on the side of the sealing resin portion (3).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 11, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsuhiko Fujikawa, Shingo Funakawa, Kazushige Sato, Nobumitsu Amachi
  • Patent number: 10741468
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10727160
    Abstract: Thermal management technology is disclosed. A thermal management component in accordance with the present disclosure can comprise a heat spreader having a plurality of microchannels. The thermal management component can also comprise a plurality of fins directly coupled to the heat spreader to provide surface area for heat transfer. In another aspect, a thermal management component can comprise a heat spreader having a plurality of microchannels, and an inlet port and an outlet port in fluid communication with the plurality of microchannels. The thermal management component can also comprise a plurality of fins coupled to the heat spreader to provide surface area for heat transfer. Additionally, the thermal management component can comprise a fluid conduit thermally coupled to the plurality of fins and fluidly coupled to the outlet port and the inlet port to facilitate flow of a heat transfer fluid through the microchannels and the fluid conduit.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Devdatta P. Kulkarni, Richard J. Dischler, Je-Young Chang
  • Patent number: 10705548
    Abstract: An air cavity package having a supplemental heat generator for generating heat and a pressure greater than atmospheric pressure within the air cavity package. The supplemental heat generator may be maintained at a constant or variable temperature. The supplemental heat generator may be selectively activated based on a predetermined parameter by a user or by a processor. The supplemental heat generator may be an RF and or other chip capable of generating heat or a conductive wire.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 7, 2020
    Assignee: RJR Technologies, Inc.
    Inventors: Raymond S. Bregante, Alex Elliott
  • Patent number: 10700046
    Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 30, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Dale A Rickard, Jason F Ross, John T Matta, Richard J Ferguson, Alan F Dennis, Joseph R Marshall, Jr., Daniel L Stanley