With Heat Sink Patents (Class 257/706)
  • Patent number: 10354936
    Abstract: An electronic component includes a substrate having a principal surface, a chip arranged at the principal surface of the substrate, a sealing resin sealing the chip on the principal surface of the substrate, and a heat dissipation member formed on the sealing resin.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: July 16, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Yusuke Harada, Yasuhiro Fuwa
  • Patent number: 10352551
    Abstract: This invention relates to the field of lighting modules employing light emitting diodes (LEDs), and more particularly to LED modules suitable for exposed lens plate luminaires. There is herein provided an LED module having a printed circuit board comprising at least two layers, wherein the interface between two layers at a side surface of the printed circuit board is covered by a protrusion of an optically transmissive cover plate. The same said optically transmissive cover plate is also adapted to cover at least one LED positioned in or on the printed circuit board.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: July 16, 2019
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Robert Van Asselt, Mark Johannes Antonius Verhoeven, Joris Jan Vrehen, Gerardus Franciscus Cornelis Maria Lijten, Laurens Bax, Chris Van Den Eerenbeemd
  • Patent number: 10347555
    Abstract: An electronic device has a substrate 10, an electronic element 80 provided on the substrate 10 and a sealing part 20 for sealing the electronic element 80. The sealing part 20 has an insertion part 22 for inserting a fastening member 90. The insertion part 22 is provided in a sealing recessed part 25 recessed compared with a circumferential region. At least side surface and the sealing recessed part 25 of the sealing part 20 are exposed to the outside.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 9, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Hideki Kamada
  • Patent number: 10347807
    Abstract: Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 9, 2019
    Assignee: BRIDGELUX INC.
    Inventor: R. Scott West
  • Patent number: 10331161
    Abstract: A power supply board includes: a first board including a top surface on which a processor is capable of being mounted, a bottom surface located on an opposite side of the top surface, and a plurality of first through holes and a plurality of second through holes capable of being electrically connected with the processor by penetrating through the first board from the top surface to the bottom surface; a second board arranged at a position distant from the bottom surface of the first board and provided with a power supply device; a first conductor mounted on the bottom surface of the first board and electrically connects the plurality of first through holes and the power supply device, and a second conductor mounted on the bottom surface of the first board and electrically connects the plurality of second through holes and the power supply device.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 25, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yuki Kanai, Takashi Imamoto
  • Patent number: 10325829
    Abstract: A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard McVicker, Sri M. Sri-Jayantha
  • Patent number: 10319663
    Abstract: A semiconductor memory device includes a housing having a wall, a circuit board located in the housing and spaced from the wall and extending along the surface of the wall, a memory located on the circuit board, a heat conduction member interposed, and compressed, between the wall and the memory. The wall includes an uneven region comprising contact portions contacting the heat conduction member and recess portions located between the contact portions. The recess portions are recessed inwardly of the wall from the ends of the contact portions in a direction away from the location of the memory.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 11, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Sawanaka
  • Patent number: 10319657
    Abstract: A circuit package panel containing a packaging of epoxy mold compounds and a circuit device in the packaging, wherein the packaging comprises, at least one hybrid layer of a first epoxy mold compound and a second epoxy mold compound of a different composition.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 11, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chien-Hua Chen, Michael W Cumbie
  • Patent number: 10312186
    Abstract: A method for forming a packaged electronic device includes providing a substrate comprising a lead and a pad. The method includes attaching a thermally conductive structure to the pad and attaching an electronic component to one of the thermally conductive structure or the pad. The method includes electrically coupling the electronic component to the lead, and forming a package body that encapsulates the electronic component and at least portions of the lead, the pad, and the thermally conductive structure, wherein the package body has a first major surface and a second major surface opposite to the first major surface, and one of the first bottom surface of the thermally conductive structure or the bottom surface of the pad is exposed in the first major surface of the package body.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Amkor Technology Inc.
    Inventors: Takahiro Yada, Toru Takahashi
  • Patent number: 10290592
    Abstract: A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 14, 2019
    Assignee: INTEL CORPORATION
    Inventors: John J Beatty, Suzana Prstic, Vipul V Mehta
  • Patent number: 10290561
    Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Edvin Cetegen, Omkar G. Karhade, Kedar Dhane, Chandra M. Jha
  • Patent number: 10283431
    Abstract: The present invention is a bonded body in which an aluminum member constituted by an aluminum alloy, and a metal member constituted by copper, nickel, or silver are bonded to each other. The aluminum member is constituted by an aluminum alloy in which a Si concentration is set to be in a range of 1 mass % to 25 mass %. A Ti layer is formed at a bonding portion between the aluminum member and the metal member, and the aluminum member and the Ti layer, and the Ti layer and the metal member are respectively subjected to solid-phase diffusion bonding.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: May 7, 2019
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo
  • Patent number: 10284105
    Abstract: A power converter (1) includes: planar semiconductor modules (10) each having a resin sealing part (16) in which a semiconductor element (11), conductive members (12, 13, and 14), and a signal terminal (15) are sealed with a resin; a cooler (20) that holds the plurality of semiconductor modules (10) in a laminated manner; and a cover (30) that covers the semiconductor modules and the cooler, wherein at least a part of the resin sealing part (16) and the cooler (20) are supported by support media (41 and 42) that extend from the cover (30) so that facing parts of the resin sealing part and the cooler with respect to the cover (30) is positioned in proximity to the cover, and the conductive members and the signal terminal protrude from the resin sealing part in a direction away from the cover.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 7, 2019
    Assignee: Honda Motor Co., Ltd.
    Inventors: Takahiro Hagimoto, Takahiro Uneme, Yuko Yamada
  • Patent number: 10276474
    Abstract: A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a front surface of the insulating substrate connected to one semiconductor element, and a metal portion on a rear surface of the insulating substrate; a metal plate joined to the metal portions of the plurality of insulating circuit boards; and a joint member joining the plurality of insulating circuit boards to the metal plate. The metal plate has a front surface in which the insulating circuit boards are arranged apart from each other, and a rear surface including first regions corresponding to positions of the metal portions and second regions other than the first regions. At least a part of a surface of each of the first regions has a surface work-hardened layer, and the second regions have a hardness different from that of the surface work-hardened layer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Ryoichi Kato, Yoshitaka Nishimura, Fumihiko Momose
  • Patent number: 10272437
    Abstract: Provided is a PCR heating block having heaters repeatedly arranged thereon is capable of preventing the radial thermal distribution generated from the individual heaters and the non-uniform heat superposition between the adjacent heaters improve the PCR yield and further capable of requiring no separate temperature controlling mechanism to achieve the miniaturization and integration of a device. Furthermore, a PCR device is capable of amplifying a plurality of nucleic acid samples at the same time and rapidly by using a PCR heating block on which heater units are repeatedly arranged and a plate-shaped PCR reaction unit and also capable of measuring successively generated optical signals electrochemical signals to in real time check the nucleic acid amplification.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: April 30, 2019
    Assignee: NANOBIOSYS INC.
    Inventors: Sung-Woo Kim, Jung-Hwan Lee, Duck-Joong Kim
  • Patent number: 10269679
    Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Liang Chen, Chi-Yang Yu, Kuan-Lin Ho, Yu-Min Liang
  • Patent number: 10228735
    Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a die disposed on a substrate; a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is disposed on a backside of the die disposed on a package substrate. A lid comprising an outer surface is disposed on the first surface of the cooling solution, wherein the lid includes a plurality of fins disposed on an inner surface of the lid. A solder is disposed between the outer surface of the lid and the first surface of the cooling solution.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Devdatta P. Kulkarni, Richard J. Dischler, Je-Young Chang
  • Patent number: 10216067
    Abstract: The IP Camera of the present invention includes a housing, a heat conducting component, a base and a supporting structure. The heat conducting component is disposed inside the housing to directly contact a heat generating component. The base can be put on or fixed onto a supporting plane, so as to hold a weight of the IP Camera by the supporting plane. An end of the supporting structure extends through the housing to directly contact the heat generating component, and the other end of the supporting structure extends into the base. The heat conducting component and the supporting structure are used to be an uninterrupted heat conduction path between the heat generating component and the base, and a coefficient of heat conductivity of the uninterrupted heat conduction path is greater than 5W/m*K, so that the IP Camera has preferred heat dissipating efficiency.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: February 26, 2019
    Assignee: Sercomm Corporation
    Inventors: Chia-An Chen, Shao-Chun Hung
  • Patent number: 10180725
    Abstract: The present application relates generally to haptic feedback actuators and their construction and use in touch based systems. The haptic feedback actuators are suitably bilayer structures including at least two materials having different thermal coefficients, allowing the structure to deflect from a first position to a second position in response to heating and/or cooling of the structure.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 15, 2019
    Assignee: IMMERSION CORPORATION
    Inventor: Vahid Khoshkava
  • Patent number: 10181433
    Abstract: A first surface of a heat source is spaced from a support by a first gap, in a thermal path from the first surface to the support. A second surface of the heat source, opposite to the first surface, is spaced by a second gap from a heat sink, in a thermal path from the second surface to the heat sink. The thermal path to the support provides a first thermal resistance, based on a gap spacing of the first gap and the thermal path to the heat sink provides a second thermal resistance, based on a gap spacing of the second gap.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 15, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Erin Elizabeth Hurbi, Michael Nikkhoo
  • Patent number: 10170389
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10160690
    Abstract: The present invention provides a silicon nitride circuit board in which metal plates are attached on front and rear sides of a silicon nitride substrate having a three-point bending strength of 500 MPa or higher, with attachment layers interposed therebetween, wherein assuming that a thickness of the metal plate on the front side is denoted by t1, and a thickness of the metal plate on the rear side is denoted by t2, at least one of the thicknesses t1 and t2 is 0.6 mm or larger, a numerical relation: 0.10?|t1?t2|?0.30 mm is satisfied, and warp amounts of the silicon nitride substrate in a long-side direction and a short-side direction both fall within a range from 0.01 to 1.0 mm. Due to above configuration, TCT properties of the silicon nitride circuit board can be improved even if the thicknesses of the front and rear metal plates are large.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 25, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Hiromasa Kato, Noboru Kitamori
  • Patent number: 10157815
    Abstract: A semiconductor device includes: a sealing body that seals a first semiconductor element and a second semiconductor element; first heat-radiating members exposed at a front surface of the sealing body; second heat-radiating members exposed at a back surface of the sealing body; first signal terminals electrically connected to the first semiconductor element, and projecting from a top surface of the sealing body in a first direction; and second signal terminals electrically connected to the second semiconductor elements, and projecting from the top surface of the sealing body in the first direction. The top surface of the sealing body includes a first inclined surface, a second inclined surface, and a boundary line or a boundary range located therebetween. The boundary line or the boundary range includes at least part of a minimum creepage path between the first signal terminals and the second signal terminals.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: December 18, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Keita Hatasa, Makoto Imai, Tomomi Okumura
  • Patent number: 10153224
    Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: December 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rahul Agarwal, Luke England, Haojun Zhang
  • Patent number: 10132571
    Abstract: A knockdown heat dissipation unit includes at least one combination body and multiple heat pipes. The combination body has two opposite connection sections. The heat pipes are respectively connected with the connection sections of the combination body to form a large area of thermal contact face. According to the structural design of the knockdown heat dissipation unit, the number of the heat pipes can be increased or reduced according to the heat dissipation requirement of a user. Also, the number of the heat pipes can be flexibly adjusted according to the size of a heat source to enhance the heat dissipation effect.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: November 20, 2018
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Ming-Han Yu, Chung-Hua Liao, Wen-Jui Chuang
  • Patent number: 10098221
    Abstract: A heat transfer assembly may be used to provide a thermal conduit from a module mounted on a circuit board through the circuit board, allowing a thermal path away from the module. The heat transfer assembly generally includes a thermally conductive base with at least one raised thermal pedestal accessible through at least one heat transfer aperture in the circuit board and in thermal contact with the module. In an embodiment, the heat transfer assembly is used in a remote PHY device (RPD) in an optical node, for example, in a CATV/HFC network. The RPD includes an enclosure having a base with at least one raised thermal pedestal in thermal contact with an optical module (e.g., an optical transmitter or transceiver) on a circuit board through at least one heat transfer aperture in the circuit board.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 9, 2018
    Assignee: Applied Optoelectronics, Inc.
    Inventors: Rafael Celedon, Mark Siejka, Michael Jones
  • Patent number: 10064287
    Abstract: In an embodiment, a method includes arranging a first carrier on a first major surface of a circuit board such that an electronic component arranged on the first carrier is positioned in an aperture in the circuit board and spaced apart from side walls of the aperture, and arranging a second carrier on a second major surface of the circuit board such that the second carrier covers the electronic component and the aperture, the second major surface of the circuit board opposing the first major surface of the circuit board. The electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact pad arranged on a first major surface of the dielectric core layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: August 28, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 10050018
    Abstract: A method is provided. The method includes providing a first wafer having a plurality of first dummy pads exposed along a first surface of the first wafer. The first dummy pads contact a first metallization layer of the first water. The method also includes providing a second wafer having a plurality of second dummy pads exposed along a first surface of the second wafer. The second dummy pads contact a second metallization layer of the second wafer. The method also includes bonding the first wafer to the second wafer in a manner that the first surface of the first wafer contacts the first surface of the second wafer and the plurality of first dummy pads are interleaved with the plurality of second dummy pads but do not contact the plurality of second dummy pads.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Zhi-Yang Wang, Sheng-Chau Chen, Cheng-Hsien Chou
  • Patent number: 10037932
    Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 31, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
  • Patent number: 10032646
    Abstract: An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 24, 2018
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Vage Oganesian, Kimitaka Endo
  • Patent number: 10020242
    Abstract: An electronics cooling arrangement includes a housing configured to contain a coolant and an electronic device disposed within the housing. The electronic device has a passageway with at least one inlet and at least one outlet and is configured to allow fluid flowing between the inlet and the outlet to cool the electronic device.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 10, 2018
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Shin Katsumata, Charles Shepard
  • Patent number: 10014232
    Abstract: The present invention provides a packaging shell and a power module having the same. The packaging shell mainly comprises an accommodating recess for receiving a substrate disposed with a plurality of electronic devices/components, so as to make the substrate be further assembled with a heat sink through the support of the packaging shell. Most importantly, in the present invention, the accommodating recess has a stepped surface for contacting with the substrate, and the stepped surface is a curve surface having a flatness difference. By such design, the compressional force generated when assembling the packaging shell, the heat sink and the system circuit board can be uniformly transmitted to substrate via the curve surface structure; such that the compressional force is avoid from being concentrated to a certain point on the substrate, and then the substrate is protected from being ruptured due to the action of the concentrated compressional force.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: July 3, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Xianming Wang, Shouyu Hong
  • Patent number: 10008454
    Abstract: A semiconductor device includes a semiconductor die having a top side and a bottom, active side. During assembly of the semiconductor device, a metal film is sputtered over the top and side surfaces of the die, and then a mold compound is formed over the metal film. The metal film can provide both heat dissipation and EMI shielding. The device may be assembled using a wafer level assembly process.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 26, 2018
    Assignee: NXP B.V.
    Inventor: Chung Hsiung Ho
  • Patent number: 9989221
    Abstract: Provided is an insulated radiating rubber molded article that can be pre-installed in an electrical apparatus such as an LED package, can improve handling properties during attachment work, and moreover can exert superior insulating characteristics and radiating characteristics. To achieve the objective, the insulated radiating rubber molded article, which, by means of being interposed between a base and the electrical apparatus when attaching the electrical apparatus, which emits heat alongside the operation thereof, to the base, promotes radiating from the electrical apparatus and electrically insulates the electrical apparatus from the base, is characterized by having a 3D shape by means of being integrally provided with: a flat surface section disposed between the electrical apparatus and the base; and a lateral surface section disposed around the electrical apparatus.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: June 5, 2018
    Assignee: NOK Corporation
    Inventor: Hiroki Yamamoto
  • Patent number: 9991434
    Abstract: A semiconductor device includes an insulating substrate,a semiconductor element disposed on an upper surface of the substrate, a heat dissipation member, and a metal bonding layer that bonds the lower surface of the substrate to the upper surface of the heat dissipation member, and the area of the upper surface of the heat dissipation member is larger than the area of the lower surface of the substrate, and the metal bonding layer contacts the whole of the lower surface of the substrate and has an area larger than the area of the lower surface of the substrate, and the heat conductivity of the metal bonding layer is higher than the heat conductivity of the heat dissipation member.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 5, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Masatsugu Ichikawa, Satoshi Shichijo, Takehito Shimatsu
  • Patent number: 9991245
    Abstract: A semiconductor package comprising: a semiconductor chip; a connection pillar that is disposed adjacent to the semiconductor chip; a first heat dissipation layer disposed on the semiconductor chip; and a second heat dissipation layer disposed on the first heat dissipation layer, the second heat dissipation layer including a first protrusion extending beyond a perimeter of the semiconductor chip and extending towards the connection pillar.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Choon Kim, Donghan Kim, Jikho Song, Mitsuo Umemoto, Inho Choi
  • Patent number: 9974190
    Abstract: In an embodiment, a method includes arranging a first carrier on a first major surface of a circuit board such that an electronic component arranged on the first carrier is positioned in an aperture in the circuit board and spaced apart from side walls of the aperture, and arranging a second carrier on a second major surface of the circuit board such that the second carrier covers the electronic component and the aperture, the second major surface of the circuit board opposing the first major surface of the circuit board. The electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact pad arranged on a first major surface of the dielectric core layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 9954459
    Abstract: Between smoothing capacitor connected between connection conductors for positive and negative poles and semiconductor power modules constituting inverter, a circuit inductance might be increased due to imbalance of current circuit loops. Phase arms each formed by a series combination of semiconductor power modules are stacked, and the group of semiconductor power modifies connected with positive connection conductor and the group of the semiconductor power modules connected with negative connection conductor are arranged in the same direction. There is formed an interspace between the arrangement of semiconductor power modules for positive pole and the arrangement of semiconductor power modules for negative pole. Connection conductors for positive and negative poles extend in a parallel state with an insulator interposed between connection conductors, through the interspace.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: April 24, 2018
    Assignee: MEIDENSHA CORPORATION
    Inventor: Takato Endo
  • Patent number: 9947612
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Rammil Seguido
  • Patent number: 9941260
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: April 10, 2018
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Chi-Chin Lien, Nai-Wei Liu, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Patent number: 9892996
    Abstract: A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 13, 2018
    Assignee: Rohm Co., Ltd.
    Inventor: Akihiro Kimura
  • Patent number: 9887154
    Abstract: A semiconductor device includes an insulating substrate including a substrate, a metal pattern formed on an upper surface of the substrate, and a metal film formed on a lower surface of the substrate, a semiconductor element fixed on the metal pattern, a case surrounding the metal pattern and having a contact portion maintained in contact with the upper surface of the substrate, and an adhesive with which the case and a portion of the upper surface of the substrate outside a portion maintained in contact with the contact portion are bonded together, wherein a plurality of through holes are formed in a peripheral portion of the case, the through holes extending vertically through the case, and wherein the metal film exists in at least part of a place right below the contact portion.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: February 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Takahashi, Yoshitaka Otsubo
  • Patent number: 9875990
    Abstract: A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 23, 2018
    Assignee: SK hynix Inc.
    Inventors: Hyung Ju Choi, Ki Yong Lee, Jong Hyun Kim, Hyoung Min Im
  • Patent number: 9871006
    Abstract: A semiconductor module including an insulated circuit substrate having a substrate, a circuit layer on a front surface of the substrate, and a metal layer on a back surface of the substrate; a semiconductor element electrically connected to the circuit layer; a cooling unit having a ceiling board bonded to the metal layer, a bottom board opposite the ceiling board, a side wall connecting a periphery of the ceiling board and a periphery of the bottom board, and a fin connecting the ceiling board and bottom board, where thickness of the ceiling board is at least 0.5 mm and at most 2.0 mm and total thickness of the ceiling board and bottom board is at least 3 mm and at most 6 mm; and a solder layer that bonds together the metal layer and the ceiling board by melting at a temperature of at least 200° C. and at most 350° C.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 16, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Takafumi Yamada, Hiromichi Gohara
  • Patent number: 9865532
    Abstract: An electrical device comprising a ribbed molded body housing an electrical component is provided. The ribbed molded body includes at least one surface or portion having a plurality of ribs along at least a portion of the surface. The electrical component may be a passive or active electrical component. The electrical component may be connected to a lead frame and molded into the ribbed molded body.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 9, 2018
    Assignee: Vishay Dale Electronics, LLC
    Inventors: Darin Glenn, Scott Blackburn
  • Patent number: 9859159
    Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 2, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Dyi-Chung Hu, Yin-Po Hung, Ra-Min Tain, Yu-Hua Chen
  • Patent number: 9860988
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2014
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Fay Hua, Hong Xie, Gregorio R. Murtagian, Amit Abraham, Alan C. Mcallister, Ting Zhong
  • Patent number: 9859185
    Abstract: A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim projection may be used in conjunction with a pedestal in order to further reduce the thermal stress produced from the mismatch of thermal properties between the copper heat-sink metal and the ceramic frame. The copper heat-sink with a shim projection may also be part of the semiconductor package along with a lead frame, the ceramic frame, a semiconductor device, a capacitor, a wire bond and a ceramic lid or an encapsulation. The copper heat-sink, the ceramic frame and the lead frame are all chosen to be cost effective, and chosen such that the packaging process for the semiconductor device is able to achieve a smaller size while maintaining high reliability, low cost, and suitability for volume manufacturing.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 2, 2018
    Assignee: Kyocera International, Inc.
    Inventors: Satoru Tomie, Mark Eblen, Eiji Watanabe, Eiji Tanaka
  • Patent number: 9851087
    Abstract: A light emitting device includes: a substrate; one or more LED (light emitting diode) elements mounted on a substrate; and a radiator unit made of metal paste and arranged on a rear surface opposite to a principal surface on which the one or more LED elements are mounted. The height Ta of the radiator unit from a rear surface is less than thickness Tb of substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: December 26, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Masashi Funakoshi
  • Patent number: 9847299
    Abstract: A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material. According to this structure, the reliability of a bond between the interposer and the chip component of the semiconductor package can be ensured while achieving a small size.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 19, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuichiro Teshima, Toshiyuki Nakaiso, Yutaka Takeshima