With Heat Sink Patents (Class 257/706)
  • Patent number: 12002729
    Abstract: A electronic package and a method of manufacturing the same are provided. The electronic package includes an electronic component, a thermal spreading element, and an encapsulant. The electronic component has a first surface. The thermal spreading element is disposed over the electronic component and has a first surface facing the first surface of the electronic component. The encapsulant covers the electronic component and has a first surface closer to the first surface of the thermal spreading element than the first surface of the electronic component.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: June 4, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Patent number: 11997801
    Abstract: A printed circuit board includes: a core portion including a cavity in one surface thereof; first and second penetration holes disposed in a bottom surface of the cavity and penetrating through the core portion; an electronic component disposed in the cavity; and an insulating material filling the cavity and each of the first and second penetration holes, wherein a sidewall of the cavity is higher than the electronic component.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: May 28, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Woo Seok Yang, Jae Han Park, Jung Hyun Cho
  • Patent number: 11984326
    Abstract: Provided are a heat dissipating substrate and a preparation method thereof, which can form a precise pattern in a thick electrode metal plate and improve insulating strength and peel strength. heat dissipating substrate for semiconductor may include: an electrode metal plate having a plurality of electrode patterns which are electrically insulated from each other by a pattern space formed therebetween; a metal base disposed under the electrode metal plate, and configured to diffuse heat conducted from the electrode metal plate; an insulating layer formed between the electrode metal plate and the metal base; and an insulating material filled portion configured to fill the pattern space and a peripheral portion outside an electrode pattern group composed of the plurality of electrode patterns, and support the electrode patterns while brought in direct contact with side surfaces of the plurality of electrode patterns.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 14, 2024
    Assignee: IMH INC.
    Inventor: Jong Eun Lee
  • Patent number: 11955348
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 9, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11929303
    Abstract: Provided is a semiconductor device having excellent heat dissipation capacity and electromagnetic wave suppression effect. A semiconductor device 1 includes a semiconductor element 30; a conductive cooling member 40 provided above the semiconductor element 30, a conductive thermally conductive member 10 that is provided between the semiconductor element 30 and the cooling member 40 and contains a cured resin. The conductive thermally conductive member 10 is connected to a ground 60 in the substrate 50 to electrically connect the cooling member 40 and the ground 60.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 12, 2024
    Assignee: Dexerials Corporation
    Inventors: Yusuke Kubo, Sergey Bolotov
  • Patent number: 11901299
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
  • Patent number: 11869776
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 9, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11855009
    Abstract: A chip package is provided. The chip package includes a substrate and a semiconductor chip over the substrate. The chip package also includes an upper plate extending across edges of the semiconductor chip. The chip package further includes a first support structure connecting a first corner portion of the substrate and a first corner of the upper plate. In addition, the chip package includes a second support structure connecting a second corner portion of the substrate and a second corner of the upper plate. The upper plate has a side edge connecting the first support structure and the second support structure, and the side edge extends across opposite edges of the semiconductor chip.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Chin-Hua Wang, Kuang-Chun Lee, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 11829826
    Abstract: A process for manufacturing a transaction card includes forming an opening in a card body of the transaction card; inserting an electronic component into the opening; and disposing a non-conductive material about the electronic component. A transaction card includes a molded electronic component.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: November 28, 2023
    Assignee: CompoSecure, LLC
    Inventor: Adam Lowe
  • Patent number: 11805223
    Abstract: Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: October 31, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Pierpaolo Lombardo, Michele Vaiana
  • Patent number: 11792928
    Abstract: In one aspect, a PCB is provided. The PCB includes at least one insulating layer, a blind slot, and at least one via. The at least on insulating layer includes a first surface and a second surface opposite the first surface. The blind slot is plated and formed in the at least one insulating layer, where the blind slot partially extends from the first surface to the second surface, and where the blind slot includes a conductive plating bonded along a major surface of the blind slot. The at least one via is electrically conductive and filled, where the at least one via is coupled with and extends between the conductive plating of the blind slot and the second surface of the at least one insulating layer.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: October 17, 2023
    Assignee: Acleap Power Inc.
    Inventors: John Andrew Trelford, Robert Joseph Roessler, Jose Daniel Rogers, Arturo Silva, Alok Lohia
  • Patent number: 11784459
    Abstract: A light emitting element mounting package includes a plate-like substrate and a base that protrudes from a front surface of the substrate and has a mounting surface on which a light emitting element is mounted. A power supply terminal is provided on the front surface of the substrate, and the power supply terminal is arranged in a direction that is opposite to a direction where an emitting surface of the light emitting element is oriented. The light emitting element mounting package further includes a wiring conductor inside the substrate, wherein the wiring conductor extends to a side of the power supply terminal where one end thereof is positioned at a side of the power supply terminal with respect to the emitting surface of the light emitting element and the other end thereof is electrically connected to the power supply terminal.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: October 10, 2023
    Assignee: KYOCERA Corporation
    Inventors: Sentarou Yamamoto, Youji Furukubo, Masanori Okamoto, Toshifumi Higashi
  • Patent number: 11749586
    Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: September 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sonkwan Hwang, Taeseong Kim, Hoonjoo Na, Kwangjin Moon, Hyungjun Jeon
  • Patent number: 11725990
    Abstract: A thermographic sensor is proposed. The thermographic sensor includes a plurality of sensing elements each comprising at least one thermo-couple. The thermographic sensor is integrated on a semiconductor on insulator body that is patterned to define a grid suspended from a substrate; for each sensing element, the grid has a frame with the cold joint of the thermo-couple, a plate with the hot joint of the thermo-couple and one or more arms sustaining the plate from the frame. The frames include one or more conductive layers of thermally conductive material for thermally equalizing the cold joints with the substrate. Moreover, each sensing element may also include a processing circuit for the thermo-couple that is integrated on the corresponding frame. A thermographic device including the thermographic sensor and a corresponding signal processing circuit, and a system including one or more thermographic devices are also proposed.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 15, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Maria Eloisa Castagna, Giuseppe Bruno
  • Patent number: 11664241
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 30, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11616017
    Abstract: An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 28, 2023
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Yingjiang Pu, Hunt Hang Jiang, Xiuhong Guo
  • Patent number: 11615998
    Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat dissipation device in thermal contact with the integrated circuit device, wherein a first portion of the heat dissipation device extends into the substrate and wherein a second portion of the heat dissipation device extends over the substrate. In one embodiment, the heat dissipation device may comprise the first portion of the heat dissipation device formed from metallization within the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Johanna Swan, Feras Eid, Adel Elsherbini
  • Patent number: 11587797
    Abstract: A semiconductor device includes a metal base plate, a case component, and a metal component. The metal component is fixed to the case component. A partial region of the metal component is exposed from the case component. The partial region is bonded to the base plate in a bonding portion. In the bonding portion, a surface of the partial region and a surface of the base plate are in direct contact with each other and integrated.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: February 21, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masayuki Mafune
  • Patent number: 11557541
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
  • Patent number: 11502020
    Abstract: An electronic device includes a chip package module which includes a chip carrier substrate, a chip, a thermal conductive unit, and an encapsulant laver. The chip is electrically connected to the chip carrier substrate. The thermal conductive unit has a first thermal conductive surface connected to the chip, and a second thermal conductive surface opposite to the first thermal conductive surface. The thermal conductive unit has a thermal conductivity greater than that of the chip. The encapsulant layer covers the chip and partially covers the thermal conductive unit in such a manner that the second thermal conductive surface is exposed from the encapsulant layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: November 15, 2022
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventor: Chia-Shuai Chang
  • Patent number: 11488883
    Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
  • Patent number: 11462476
    Abstract: An electronic device is disclosed. In an embodiment an electronic device includes at least one first carrier and at least one semiconductor chip, wherein the first carrier has a cavity in which the semiconductor chip is arranged.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 4, 2022
    Assignee: TDK ELECTRONICS AG
    Inventors: Thomas Feichtinger, Johann Pichler, Nele Reimer, Markus Koini, Manfred Schweinzger
  • Patent number: 11437296
    Abstract: A semiconductor package in an aspect of the present invention includes a metal board, a first frame, a second frame, and a bond. The metal board has an upper surface including a mount on which a semiconductor device is mountable. The first frame has a side surface facing a side surface of the metal board and has a smaller thermal expansion coefficient than the metal board. The second frame is on upper surfaces of the metal board and the first frame and surrounds the mount, and has a smaller thermal expansion coefficient than the metal board. The bond is between the metal board and the first frame, between the metal board and the second frame, and between the first frame and the second frame. The semiconductor package includes an alloy layer between the metal board and the bond.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 6, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Hiroshi Matsumoto, Hiroki Ito, Takashi Kimura
  • Patent number: 11417630
    Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Digvijay A. Raorane, Ravindranath Vithal Mahajan, Mitul Bharat Modi
  • Patent number: 11404346
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 2, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Kyu Kim, Jung-Ho Park, Jong Youn Kim, Yeon Ho Jang, Jae Gwon Jang
  • Patent number: 11398414
    Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chia-Pin Chiu, Pooya Tadayon, Joe F. Walczyk, Chandra Mohan Jha, Weihua Tang, Shrenik Kothari, Shankar Devasenathipathy
  • Patent number: 11367669
    Abstract: A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including electrodes on a front surface side and a back surface side thereof; and a graphite plate having an anisotropic thermal conductivity, the graphite plate of which one end is connected to the front surface side of the semiconductor device and the other end is connected to the insulating substrate, wherein heat of the front surface side of the semiconductor device is transferred to the insulating substrate through the graphite plate. There is provide an inexpensive power module capable of reducing a stress and capable of exhibiting cooling performance not inferior to that of the double-sided cooling structures.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 21, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Maiko Hatano, Takukazu Otsuka, Hirotaka Otake, Tatsuya Miyazaki
  • Patent number: 11330706
    Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a component embedded in the stack so that a gap of less than 100 ?m, in particular less than 60 ?m, remains between at least one sidewall of the component and a sidewall of an adjacent one of the layer structures or a further component embedded in the stack; and a filler medium including filler particles, wherein the filler medium at least partially fills the gap. In addition, a method of manufacturing a component carrier is provided.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 10, 2022
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Seok Kim Tay, Mikael Tuominen
  • Patent number: 11302597
    Abstract: A semiconductor device is provided with a heat dissipating face side skirt portion, which is a frame-form projection, on a heat dissipating face of a lead frame. Because of this, creepage distance increases with a small increase in an amount of resin, and insulating properties improve. Also, the heat dissipating face side skirt portion is molded via two transfer molding steps, wettability of the second molding resin with respect to a first molding resin and the lead frame increases, and adhesion improves. Furthermore, an end face of an inner lead is exposed in an element sealing portion on a mounting face side, and covered with a second thin molded portion molded using the second molding resin, whereby heat generated in a semiconductor element can efficiently be caused to escape from faces of both a first thin molded portion and the second thin molded portion, because of which heat dissipation improves.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanobu Kajihara, Katsuhiko Omae, Takashi Nagao, Masayuki Funakoshi, Norio Emi, Atsuki Fujita, Yuki Okabe
  • Patent number: 11297727
    Abstract: A power electronic component including a surface adapted to be attached to a heatsink, the surface forming a bottom surface of the power electronic component, one or more power electronic semiconductor chips mounted on a substrate above the bottom surface, and a housing enclosing the one or more power electronic semiconductor chips. The power electronic component includes a thermal insulator disposed above the one or more power electronic semiconductor chips, such that the bottom surface and the thermal insulator are on the opposite sides of the one or more power electronic semiconductor chips.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 5, 2022
    Assignee: ABB Schweiz AG
    Inventors: Jorma Manninen, Mika Silvennoinen, Joni Pakarinen
  • Patent number: 11289398
    Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°<?<90°. The heat spreader is disposed over the substrate, wherein the semiconductor device is disposed between the heat spreader and the substrate. The adhesive layer is surrounding the semiconductor device and attaching the heat spreader onto the substrate, wherein the adhesive layer has a first opening misaligned with one of corners of the semiconductor device closest to the first opening.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Patent number: 11276628
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 15, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Cristina Somma
  • Patent number: 11264304
    Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Liang Chen, Chi-Yang Yu, Kuan-Lin Ho, Yu-Min Liang
  • Patent number: 11264301
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • Patent number: 11258270
    Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 22, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
  • Patent number: 11244875
    Abstract: A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasutaka Shimizu
  • Patent number: 11239224
    Abstract: A power conversion device provided with a switching circuit unit including a plurality of upper-arm switching elements connected to positive electrode wiring and a plurality of lower-arm switching elements connected to negative electrode wiring. The power conversion device includes a first semiconductor module incorporating a plurality of the upper-arm switching elements connected together in parallel, a second semiconductor module incorporating a plurality of the lower-arm switching elements connected together in parallel, and a third semiconductor module incorporating the upper-arm switching elements connected together in series and the lower-arm switching elements connected together in series.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 1, 2022
    Assignee: DENSO CORPORATION
    Inventors: Kazuma Fukushima, Yuu Yamahira, Ryota Tanabe, Tetsuya Matsuoka, Kosuke Kamiya, Taijiro Momose
  • Patent number: 11239182
    Abstract: An integrated circuit (IC) package incorporating controlled induced warping is disclosed. The IC package includes an electronic substrate having an active side upon which semiconducting dies and functional circuits have been lithographed or otherwise fabricated, leading to an inherent warping in the direction of the active side. One or more corrective layers may be deposited to the opposing, or inactive, side of the semiconducting die via thin film deposition (TFD) instrumentation and techniques in order to induce corrective warping of the electronic substrate back toward the horizontal (e.g., in the direction of the inactive side) to a desired degree.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 1, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Richard Korneisel, Nathaniel P. Wyckoff, Brandon C. Hamilton, Jacob R. Mauermann, Carlen R. Welty
  • Patent number: 11201130
    Abstract: A semiconductor device includes a base plate; a metal plate above the base plate; a bonding material between the base plate and metal plate, bonding the metal plate to the base plate; an insulating plate on the metal plate; a circuit member on the insulating plate; a semiconductor element mounted on the circuit member; and a sealing material to seal a space on the base plate. The metal plate includes a bottom surface area along a periphery, exposed from the bonding material. The base plate includes a groove-shaped first recess formed along the periphery of the metal plate and faces the bottom surface area. The base plate also includes a groove-shaped second recess that is spaced apart from the first recess and that is formed on the inner side relative to the first recess. The bonding material is disposed in at least a part of the second recess.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 14, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hirotaka Oomori, Takashi Tsuno
  • Patent number: 11195740
    Abstract: An assembly comprising a device wafer received in a recess of a carrier wafer. A device wafer comprising a protrusion terminating at an active surface bearing integrated circuitry, the protrusion surrounded by a peripheral flat extending to an outer periphery of the device wafer. A method of wafer thinning using the previously described carrier wafer and device wafer. Various implementations of a carrier wafer having a recess are also disclosed, as are methods of fabrication.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Kyle K. Kirby
  • Patent number: 11177189
    Abstract: A module includes a substrate, a first component on a first main surface of the substrate and from which heat is to be dissipated, a sealing resin layer that encloses the first component, and a heat-dissipating member that includes a first and a second heat-dissipating portions. The first heat-dissipating portion is disposed in the sealing resin layer, spaced apart from an upper surfaces of the first component, and includes a first overlap portion that overlaps an upper surfaces of the first component when viewed in plan in a direction perpendicular to the first main surface. The second heat-dissipating portion extends from an undersurface of the first overlap portion to the upper surface of the first component. An area of the second heat-dissipating portion on a surface of the first overlap portion including the undersurface is smaller than an area of the first overlap portion.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Yoshitaka Matsukawa
  • Patent number: 11171073
    Abstract: The present disclosure relates to a switching semiconductor device and a cooling apparatus thereof. The cooling apparatus of the switching semiconductor device of the present disclosure comprises a first heat dissipation plate configured to facilitate heat dissipation of a surface of the semiconductor device at an installation space, and a second heat dissipation plate disposed inside the installation space along a thickness direction of the first heat dissipation plate. The installation space is formed in a predetermined size at the surface of the semiconductor device, and the second heat dissipation plate is configured to contact the first heat dissipation plate so as to allow heat exchange. Accordingly, a heat dissipation area may be increased without increasing a size of the installation space.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 9, 2021
    Assignee: LG Electronics Inc.
    Inventors: Kyeonghwan Kim, Junho Ahn
  • Patent number: 11171072
    Abstract: A heat dissipation substrate includes a substrate, a heat conducting element, an insulating filling material, a first circuit layer, and a second circuit layer. The substrate has a first surface, a second surface opposite the first surface, and a through groove communicating the first surface with the second surface. The heat conducting element is disposed in the through groove. The heat conducting element includes an insulating material layer and at least one metal layer. The insulating filling material is filled in the through groove for fixing the heat conducting element into the through groove. The first circuit layer is disposed on the first surface of the substrate and exposes a portion of the heat conducting element. The second circuit layer is disposed on the second surface of the substrate. The first circuit layer and the metal layer are respectively disposed on two opposite sides of the insulating material layer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 9, 2021
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chien-Hung Wu, Bo-Yu Huang, Chia-Wei Chang, Tzu-Shih Shen
  • Patent number: 11139253
    Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chui Woo Kim, Sang Min Yong, Yang Gyoo Jung
  • Patent number: 11094913
    Abstract: A flexible organic light emitting diode (OLED) display panel is provided, including: a flexible base and an organic light emitting layer, a thin film encapsulating layer, a polarizer, a glass cover, and a sealing, heat-dissipation glue sequentially formed on the flexible base. The sealing, heat-dissipation glue is formed on sidewalls of the OLED display panel to prevent moisture from entering into the OLED display panel. The sealing, heat-dissipation glue includes heat absorbing particles; the heat absorbing particles are configured for absorbing heat generated by the OLED display panel.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 17, 2021
    Inventor: Xuesi Qin
  • Patent number: 11062970
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Patent number: 11039537
    Abstract: An electronic component embedded substrate includes a core member including a first wiring layer, a first insulating layer covering the first wiring layer and having a first through-portion, a second wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and having a second through-portion exposing at least a portion of the second wiring layer; a first electronic component disposed in the first through-portion; a second electronic component disposed in the second through-portion; and an insulating resin covering at least a portion of each of the first electronic component and the second electronic component. The second wiring layer includes a first wiring pattern having a portion covered with the second insulating layer, and a second wiring pattern having a portion covered with the insulating resin. The second electronic component is connected to the second wiring pattern.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Yoon Lee, Tae Seong Kim
  • Patent number: 11008424
    Abstract: Disclosed are exemplary embodiments of systems and methods for controllably changing (e.g., weaken, strengthen, eliminate, add, customize, alter, etc.) surface tack of thermal interface materials. Also disclosed are exemplary embodiments of thermal interface material assemblies, which include coatings configured to change surface tack of the thermal interface materials.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 18, 2021
    Inventors: Jingbo Shen, Mandy Feng, Jingqi Zhao
  • Patent number: 11011448
    Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
  • Patent number: 11004776
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 11, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Rammil Seguido