With Heat Sink Patents (Class 257/706)
  • Patent number: 11139253
    Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chui Woo Kim, Sang Min Yong, Yang Gyoo Jung
  • Patent number: 11094913
    Abstract: A flexible organic light emitting diode (OLED) display panel is provided, including: a flexible base and an organic light emitting layer, a thin film encapsulating layer, a polarizer, a glass cover, and a sealing, heat-dissipation glue sequentially formed on the flexible base. The sealing, heat-dissipation glue is formed on sidewalls of the OLED display panel to prevent moisture from entering into the OLED display panel. The sealing, heat-dissipation glue includes heat absorbing particles; the heat absorbing particles are configured for absorbing heat generated by the OLED display panel.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 17, 2021
    Inventor: Xuesi Qin
  • Patent number: 11062970
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Patent number: 11039537
    Abstract: An electronic component embedded substrate includes a core member including a first wiring layer, a first insulating layer covering the first wiring layer and having a first through-portion, a second wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and having a second through-portion exposing at least a portion of the second wiring layer; a first electronic component disposed in the first through-portion; a second electronic component disposed in the second through-portion; and an insulating resin covering at least a portion of each of the first electronic component and the second electronic component. The second wiring layer includes a first wiring pattern having a portion covered with the second insulating layer, and a second wiring pattern having a portion covered with the insulating resin. The second electronic component is connected to the second wiring pattern.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Yoon Lee, Tae Seong Kim
  • Patent number: 11008424
    Abstract: Disclosed are exemplary embodiments of systems and methods for controllably changing (e.g., weaken, strengthen, eliminate, add, customize, alter, etc.) surface tack of thermal interface materials. Also disclosed are exemplary embodiments of thermal interface material assemblies, which include coatings configured to change surface tack of the thermal interface materials.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 18, 2021
    Inventors: Jingbo Shen, Mandy Feng, Jingqi Zhao
  • Patent number: 11011448
    Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
  • Patent number: 11004776
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 11, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Rammil Seguido
  • Patent number: 10974360
    Abstract: A first diamond layer made of polycrystalline diamonds and doped with foreign atoms, is arranged on a metal surface of a machining tool, and is used to detect the degree of wear of an undoped polycrystalline second diamond layer, which is arranged on the doped diamond layer and forms a functional region of the machining tool, wherein at least one physical parameter is detected continuously or periodically during operation of the tool, and wherein a change in the parameter indicates the degree of wear of the undoped second diamond layer. The doped diamond layer forms an “intelligent stop layer” for the tool because as a result of change in the transition from the undoped to the doped layer, the conductivity of the system changes, for example, and this change can be used to form a stop signal for the machine drive before the tool and the machined workpiece are damaged.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 13, 2021
    Assignee: Guehring KG
    Inventor: Immo Garrn
  • Patent number: 10969840
    Abstract: Disclosed herein are embodiments of heat spreaders with interlocked inserts, and related devices and methods. In some embodiments, a heat spreader may include: a frame formed of a first material, wherein the frame includes an opening, a projection of the frame extends into the opening, and the projection has a top surface, a side surface, and a bottom surface; a recess having at least one sidewall formed by the frame; and an insert formed of a second material different from the first material, wherein the insert is disposed in the frame and in contact with the top surface, the side surface, and the bottom surface of the projection.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Aravindha R. Antoniswamy, Syadwad Jain, Zhizhong Tang, Wei Hu
  • Patent number: 10950520
    Abstract: An electronic package is provided. A heat dissipator is bonded via a thermal interface layer to an electronic component disposed on a carrier. The heat dissipator has a concave-convex structure to increase a heat-dissipating area of the thermal interface layer. Therefore, the heat dissipator has a better heat-dissipating effect.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Wen-Shan Tsai, En-Li Lin, Kaun-I Cheng, Wei-Ping Wang
  • Patent number: 10893616
    Abstract: Disclosed is a production method of a multi-layered printed wiring board, including the following steps 1 to 3: Step 1: a step of laminating, on a substrate with inner layer circuit, a metal foil with adhesive layer including a support, a metal foil having a thickness of 3 ?m or less and ? or less relative to the thickness of the inner layer circuit, and an organic adhesive layer having a thickness of 10 ?m or less in this order, via an organic insulating resin layer such that the organic insulating resin layer and the organic adhesive layer are opposed to each other, and then releasing the support to form a laminated sheet (a) having the metal foil as an outer layer metal foil layer; Step 2: a step of irradiating the laminated sheet (a) with a laser to bore the outer layer metal foil layer, the organic adhesive layer, and the organic insulating resin layer to form a bored laminated sheet (b) having a blind via hole; and Step 3: a step of forming an outer layer circuit connected with the inner layer circui
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: January 12, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Hitoshi Onozeki, Tsubasa Inoue, Katsuji Yamagishi, Hiroshi Shimizu
  • Patent number: 10879192
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan
  • Patent number: 10881030
    Abstract: An example electrical and liquid coolant midplane includes an electrical midplane having a ring bus bar assembly, a liquid coolant manifold, and a heat transfer device. The ring bus bar assembly is to receive power from power supply units of the computing system and provide the power to computing components installed in the computing system. The liquid coolant manifold includes four segments connected together as a rectangular ring, the liquid coolant manifold including first liquid connectors facing in a first direction and second liquid connectors facing in a second direction opposite the first direction. The heat transfer device is in contact with the ring bus bar assembly and one of the segments of the liquid coolant manifold, to thermally couple the ring bus bar assembly with the manifold to provide liquid cooling to the ring bus bar assembly.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 29, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Harvey J. Lunsman, Steven Dean, Mike Kubisiak, Michael Scott, Robert Mascia
  • Patent number: 10847437
    Abstract: An object is to provide a technique capable of increasing a heat radiation property in radiating a heat generated in a shunt resistance. A semiconductor device includes: a container body having a space with an opening; a semiconductor chip, a shunt resistance, and a circuit pattern disposed in the space in the container body; a partition member; a first cover; and a second cover. The partition member separates the space in the container body into a first space and a second space. The first cover covers a part of the opening corresponding to the first space, and the second cover covers a part of the opening corresponding to the second space. At least one hole through which the second space and outside of the container body are communicated with each other is formed in the second cover or by the second cover.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daichi Otori
  • Patent number: 10818704
    Abstract: Disclosed is a method for manufacturing a thin film transistor, and a thin film transistor, relating to the technical field of liquid crystal display.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: October 27, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Songshan Li
  • Patent number: 10818569
    Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: October 27, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Se Man Oh, Kyoung Yeon Lee, Sang Hyeon Lee, Min Cheol Shin
  • Patent number: 10796978
    Abstract: A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard McVicker, Sri M. Sri-Jayantha
  • Patent number: 10777965
    Abstract: Provided is a laser apparatus and a light source apparatus that can reduce the footprint and realize space-saving. The laser apparatus has a bottom plate; a semiconductor laser element mounted on the bottom plate; and a terminal unit that is provided so as to face upward with respect to the bottom plate and enables external electrical connection.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 15, 2020
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yuta Ishige, Etsuji Katayama, Atsushi Oguri, Hajime Mori
  • Patent number: 10775028
    Abstract: A complex device that integrates a beam shaping aperture in a printed circuit board of the complex device (e.g., scanner or barcode reader or optical module) is provided. The complex device has a light-emitting diode pattern projection system. The pattern projection system includes one or more light-emitting diodes and a printed circuit board. The printed circuit board has one or more apertures and one or more receptacles. The one or more receptacles are positioned behind the aperture and receive the one or more light-emitting diodes. The printed circuit board with receptacle offer self-alignment for the light emitting diodes. The beam shaping aperture in front of the light-emitting diodes allows light to pass through the aperture that is part of the printed circuit board layer of the complex device.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: September 15, 2020
    Assignee: DATALOGIC IP TECH S.R.L.
    Inventors: Federico Canini, Anna Guagliumi, Davide Bottazzi
  • Patent number: 10764989
    Abstract: An integrated circuit package having excellent heat dissipation is described. An integrated circuit die is attached to a substrate and the substrate is mounted on a printed circuit board (PCB) wherein there is a gap between a surface of the die facing the PCB and the PCB. A thermal enhanced layer is formed within the gap wherein heat travels from the die through the thermal enhanced layer to the PCB.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 1, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Tung Ching Lui, Baltazar Canete, Rajesh Aiyandra
  • Patent number: 10763231
    Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dibyajat Mishra, Ashok Prabhu, Tomoko Noguchi, Luu Thanh Nguyen, Anindya Poddar, Makoto Yoshino, Hau Nguyen
  • Patent number: 10756002
    Abstract: A packaged device, having a package, including a first dissipative region, a second dissipative region, a first connection element and a second connection element. A die of semiconductor material is arranged within the package, carried by the first dissipative region. The first and second dissipative regions extend at a distance from each other, and the first and second connection elements extend at a distance from each other between the first and second dissipative regions. The first dissipative region, the second dissipative region, the first connection element, and the second connection element are hollow and form a circuit containing a cooling liquid.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 25, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cristiano Gianluca Stella, Francesco Salamone
  • Patent number: 10745561
    Abstract: A filler for a heat transfer member includes: a core material which is made of an inorganic material or metal material having a thermal conductivity of 15 W/mK or more, and transfers heat; and an insulating film which includes a silicon oxide film and a diamond-like carbon film having electrical insulation properties, and covers the core material. The dielectric breakdown voltage of the filler is 500 V or more.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 18, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Koji Nakanishi
  • Patent number: 10741465
    Abstract: A circuit module (301) includes a first substrate (201), a first module (101), a sealing resin portion (3), and a conductive material film (7). The first substrate (201) has a first principal surface (201a). The first module (101) is mounted on the first principal surface (201a). The sealing resin portion (3) is formed on the first principal surface (201a) and covers the first module (101). The conductive material film (7) covers a side of the sealing resin portion (3). The first module (101) includes a conductive material portion and a device which may produce heat and which is mounted on the conductive material portion. The conductive material portion connects with the conductive material film (7) on the side of the sealing resin portion (3).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 11, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsuhiko Fujikawa, Shingo Funakawa, Kazushige Sato, Nobumitsu Amachi
  • Patent number: 10741468
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10727160
    Abstract: Thermal management technology is disclosed. A thermal management component in accordance with the present disclosure can comprise a heat spreader having a plurality of microchannels. The thermal management component can also comprise a plurality of fins directly coupled to the heat spreader to provide surface area for heat transfer. In another aspect, a thermal management component can comprise a heat spreader having a plurality of microchannels, and an inlet port and an outlet port in fluid communication with the plurality of microchannels. The thermal management component can also comprise a plurality of fins coupled to the heat spreader to provide surface area for heat transfer. Additionally, the thermal management component can comprise a fluid conduit thermally coupled to the plurality of fins and fluidly coupled to the outlet port and the inlet port to facilitate flow of a heat transfer fluid through the microchannels and the fluid conduit.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Devdatta P. Kulkarni, Richard J. Dischler, Je-Young Chang
  • Patent number: 10705548
    Abstract: An air cavity package having a supplemental heat generator for generating heat and a pressure greater than atmospheric pressure within the air cavity package. The supplemental heat generator may be maintained at a constant or variable temperature. The supplemental heat generator may be selectively activated based on a predetermined parameter by a user or by a processor. The supplemental heat generator may be an RF and or other chip capable of generating heat or a conductive wire.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 7, 2020
    Assignee: RJR Technologies, Inc.
    Inventors: Raymond S. Bregante, Alex Elliott
  • Patent number: 10700046
    Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 30, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Dale A Rickard, Jason F Ross, John T Matta, Richard J Ferguson, Alan F Dennis, Joseph R Marshall, Jr., Daniel L Stanley
  • Patent number: 10672695
    Abstract: This document discusses, among other things, a multi-layer molded substrate having layers with a graded coefficients of thermal expansions (CTEs) to optimize thermal performance of the multi-layer molded substrate with first and second structures attached to top and bottom surfaces of the multi-layer molded substrate, respectively.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Rahul N. Manepalli
  • Patent number: 10672626
    Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Aditya S. Vaidya, Nachiket R. Raravikar, Eric J. Li
  • Patent number: 10667442
    Abstract: An electronic device having a shield structure is disclosed. The shield structure includes a conductive heat diffusion plate that is provided in a position facing a mounting surface of an electronic circuit board on which electronic components, such as a CPU, are mounted, and diffuses heat generated from the CPU, etc.; and a conductive sponge-like member that is firmly fixed to at least either the mounting surface of the electronic circuit board or a surface of the conductive heat diffusion plate which faces the mounting surface of the electronic circuit board, and is provided to separate the CPU, etc. which generate electromagnetic wave noise from antennas.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: May 26, 2020
    Assignee: LENOVO SINGAPORE PTE LTD
    Inventors: Munefumi Nakata, Seiji Yamasaki
  • Patent number: 10651108
    Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Zhizhong Tang, Syadwad Jain, Wei Hu, Michael A. Schroeder, Rajen S. Sidhu, Carl L. Deppisch, Patrick Nardi, Kelly P. Lofgreen, Manish Dubey
  • Patent number: 10629452
    Abstract: A manufacturing method of a chip package structure is provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 21, 2020
    Assignees: NIKO SEMICONDUCTOR CO., LTD., SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Chih-Cheng Hsieh, Hsiu-Wen Hsu
  • Patent number: 10607859
    Abstract: A heat sink can be attached to a heat-producing electronic device by aligning an adhesive material to a surface of the heat sink, applying the adhesive material to the surface to form an outer perimeter and applying, within the outer perimeter, a thermally conductive material to the surface. The surface of the heat sink and a surface of the heat-producing electronic device can then be aligned, and the heat sink can be assembled to the heat-producing electronic device by bringing the heat-producing electronic device surface into contact with the adhesive material. The heat sink can then be affixed to the heat-producing electronic device by applying a compressive force to the assembly to activate the adhesive material.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karl Stathakis, Phillip V. Mann, Mark K. Hoffmeyer
  • Patent number: 10600717
    Abstract: A semiconductor device includes a first semiconductor element, a first heat dissipation plate connected to the first semiconductor element, a sealing body that integrally holds the first semiconductor element and the first heat dissipation plate, and a first terminal that is electrically connected to the first semiconductor element and protrudes from the sealing body. The first heat dissipation plate has an insulating substrate, an inner conductor layer, and an outer conductor layer. The outer conductor layer is exposed on a first main surface of the sealing body. The first terminal protrudes from a first side surface adjacent to the first main surface of the sealing body. On the first main surface of the sealing body, at least one first groove extending in a direction along the first side surface is provided in a range located between the outer conductor layer and the first side surface.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 24, 2020
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Shingo Tsuchimochi
  • Patent number: 10573618
    Abstract: A package structure includes a metal carrier, a conductive adhesive layer disposed on the metal carrier, a conductive post disposed on the conductive adhesive layer, a semiconductor chip disposed on the conductive adhesive layer and laterally spaced from the conductive post, and a redistribution layer disposed on the conductive post and the semiconductor chip. The semiconductor chip includes a first terminal at an upper surface of the semiconductor chip. The first terminal of the semiconductor chip is electrically connected to the bottom surface of the semiconductor chip through the redistribution layer, the conductive post and the conductive adhesive layer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 25, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Shiau-Shi Lin
  • Patent number: 10566260
    Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
  • Patent number: 10535615
    Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Srikant Nekkanty, Rajendra C. Dias, Patrick Nardi
  • Patent number: 10535616
    Abstract: A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Yu-Hsiang Hu, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10529643
    Abstract: A semiconductor device that reduces the deformation of a metal base due to pressure during transfer molding, to thereby suppress the occurrence of cracks in an insulating layer to achieve high electrical reliability. The semiconductor device includes: a metal member provided, on its lower surface, with a projection and a depression, and a projecting peripheral portion surrounding the projection and the depression and having a height greater than or equal to a height of the projection of the projection and the depression; an insulating layer formed on an upper surface of the metal member; a metal layer formed on an upper surface of the insulating layer; a semiconductor element joined to an upper surface of the metal layer; and a sealing resin to seal the semiconductor element, the metal layer, the insulating layer and the metal member.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kei Yamamoto, Hodaka Rokubuichi, Dai Nakajima, Kiyofumi Kitai, Yoichi Goto
  • Patent number: 10529645
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10504808
    Abstract: A semiconductor module includes a case. The case includes a bottom part, a case frame, and a case lid. An inner electrode and a stud bolt are provided inside the case. A head part of the stud bolt is tapered, and a tubular part has an inner diameter that increases downward so as to keep a constant distance from the sides of the head part. With this structure, even if the stud bolt is pulled up, the tubular part can hold down the head part. Therefore, the stud bolt can be prevented from being loosened or detached by the force applied from a terminal fixing screw when an external connection terminal is attached or removed.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 10, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Fumihito Kawahara, Koji Yamada
  • Patent number: 10498195
    Abstract: A power tool and a printed circuit board assembly (“PCBA”) for the power tool. The PCBA includes, for example, a printed circuit board (“PCB”), a heat sink, a spacer between the PCB and the heat sink, and a gap pad. The PCB and the heat sink are fastened to one another via fasteners so the spacer absorbs excess forces torsional forces from torques applied to the fasteners. The gap pad is placed within an opening or recess of the spacer to contact one or more FETs on the PCB. In some embodiments, the PCBA includes a second heat sink or rigid member on the opposite side of the PCB than the spacer to further distribute excess torsional forces from torques applied to the fasteners.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 3, 2019
    Assignee: MILWAUKEE ELECTRIC TOOL CORPORATION
    Inventors: Matthew J. Mergener, Daniel R. Ertl
  • Patent number: 10497616
    Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 10494119
    Abstract: A power distribution connector is provided, which includes an electrically conductive bus bar configured to conduct electricity between a power-supplying node and an opposing power-consuming node, and has a set of surfaces between the opposing nodes and a thermally conductive polymer having a first surface abutting at least a portion of a subset of the bus bar surfaces and a second surface spaced from the first surface.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 3, 2019
    Assignee: GE Aviation Systems Limited
    Inventor: Michael James Smith
  • Patent number: 10490489
    Abstract: Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 26, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Stuart B. Molin, Laxminarayan Sharma
  • Patent number: 10483181
    Abstract: An integrated circuit chip is mounted to a front face of a support plate. An encapsulation cap in then mounted to the support plate. The encapsulation cap includes a front wall and a peripheral wall having an end edge at least partly facing a peripheral zone of the support plate. The support plate and the encapsulation cap delimit a chamber in which the integrated circuit chip is situated. To mount the encapsulation cap, a bead of glue is inserted between the peripheral zone and the end edge of the peripheral wall of the encapsulation cap. A peripheral outer face of the encapsulation cap includes a recess extending from the end edge which locally uncovers a part of the bead of glue. A local hardening of the glue at the recess is performed as a first attachment step. Further hardening of the remainder of the glue is then performed.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Nicolas Mastromauro
  • Patent number: 10480994
    Abstract: A microchip has a rear face attached to a front mounting face of a support plate. An encapsulation cover for the microchip is mounted to the support plate. The encapsulation cover includes a front wall, a peripheral wall extending from the front wall and an inside partition extending from the front wall and between opposite sides of the peripheral wall. The inside partition passes locally above the microchip to delimit two cavities. A bonding material is interposed between encapsulation cover and the support plate and microchip. An end part of the inside partition of the cover, adjacent to the front face of the microchip, include an accumulation and containment recess that is configured to at least partly receive the bonding material.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Jean-Michel Riviere
  • Patent number: 10480770
    Abstract: A lamp is disclosed, which has a lamp housing, having an end wall and a side wall, a lighting means device arranged in a housing interior having a lighting means carrier and at least one lighting means arranged thereon, an insulation component formed from an electrically insulating material having a main portion and an edging portion, wherein the main portion is arranged between the end wall and the lighting means device and wherein the edging portion extends from the main portion in such a way that the edging portion is arranged between the lighting means device and the side wall of the lamp housing.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: November 19, 2019
    Assignee: H4X e.U.
    Inventor: Andreas Hierzer
  • Patent number: 10457001
    Abstract: A method for forming a matrix composite layer on a workpiece and a workpiece with a matrix composite layer are disclosed. In an embodiment the method includes forming a wall around a metallic surface such that the wall extends in a vertical direction from a plane formed by the metallic surface, and depositing a filler material in a walled area on the metallic surface. The method further includes depositing a plastic material on the filler material and performing a vacuum treatment of the filler material and the plastic material thereby forming a matrix composite layer disposed on the metallic surface.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Jagen Krishnan, Sanjay Kumar Murugan, Hong Lim Lee