Entirely Of Metal Except For Feedthrough Patents (Class 257/708)
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Publication number: 20100072608Abstract: A semiconductor device is disclosed which includes a metal base, a semiconductor chip, a lead, and a sealant. The semiconductor chip has an opposite pair of first and second electrode surfaces and a side surface. The semiconductor chip is fixed on the metal base with the first electrode surface solder-connected to the metal base. The lead is solder-connected to the second electrode surface of the semiconductor chip. The sealant seals, at least, the side surface of the semiconductor chip and solders connecting the metal base, the semiconductor chip, and the lead. Further, the lead has a small-cross-section portion which has a smaller cross-sectional area perpendicular to the longitudinal direction of the lead than other portions of the lead adjacent to the small-cross-section portion.Type: ApplicationFiled: September 21, 2009Publication date: March 25, 2010Applicant: DENSO CORPORATIONInventor: Shigekazu Kataoka
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Patent number: 7663228Abstract: An electronic component includes an electronic element, a conductive first base portion, a conductive second base portion, an insulator and a terminal. An electronic element is to be mounted on the electronic element mounting portion. The electronic element mounting portion is mounted on the first base portion. The insulator insulates the first base portion from the second base portion and couples the first base portion to the second base portion. The terminal is provided on the first base portion and is insulated from the first base portion.Type: GrantFiled: March 27, 2007Date of Patent: February 16, 2010Assignee: Eudyna Devices Inc.Inventors: Yoshihiro Tateiwa, Kakushi Nakagawa
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Patent number: 7641709Abstract: Discontinuous diamond particulate containing metal matrix composites of high thermal conductivity and methods for producing these composites are provided. The manufacturing method includes producing a thin reaction formed and diffusion bonded functionally graded interactive SiC surface layer on diamond particles. The interactive surface converted SiC coated diamond particles are then disposed into a mold and between the particles and permitted to rapidly solidify under pressure. The surface conversion interactive SiC coating on the diamond particles achieves minimal interface thermal resistance with the metal matrix which translates into good mechanical strength and stiffness of the composites and facilitates near theoretical thermal conductivity levels to be attained in the composite. Secondary working of the diamond metal composite can be performed for producing thin sheet product.Type: GrantFiled: October 8, 2007Date of Patent: January 5, 2010Assignee: Materials and Electrochemical Research (MER) CorporationInventors: Sion M. Pickard, James C. Withers, Raouf O. Loutfy
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Patent number: 7582964Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.Type: GrantFiled: November 19, 2007Date of Patent: September 1, 2009Assignee: Kyocera America, Inc.Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
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Publication number: 20090146291Abstract: A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell transistors have channel lengths that extend in a first direction, and the package further includes a supporting substrate having an upper surface on which the semiconductor chip is affixed. The supporting substrate is configured to bend in response to a temperature increase in a manner that applies a tensile stress to the channel regions of the semiconductor chip in the first direction. Related methods are also disclosed.Type: ApplicationFiled: December 4, 2008Publication date: June 11, 2009Inventors: Hee-Soo Kang, Choong-Ho Lee, Hye-Jin Cho
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Patent number: 7521794Abstract: A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the device, and methods of fabricating the device and package are provided. In one embodiment, the semiconductor device comprises a thick thermally conductive plane (e.g., copper plane) mounted on a thin support substrate and interfaced with a die. Thermally conductive via interconnects extending through the substrate conduct heat generated by the die from the conductive plane to conductive balls mounted on traces on the opposing side of the substrate. In another embodiment, the semiconductor devices comprises a thick thermally conductive plane (e.g., copper foil) sandwiched between insulative layers, with signal planes (e.g., traces, bonding pads) disposed on the insulative layers, a die mounted on a first signal plane, and solder balls mounted on bonding pads of a second signal plane.Type: GrantFiled: August 31, 2006Date of Patent: April 21, 2009Assignee: Micron Technology, Inc.Inventors: Pak Hong Yee, Teck Kheng Lee
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Patent number: 7504670Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.Type: GrantFiled: June 7, 2006Date of Patent: March 17, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Satoshi Shiraishi, Yoichi Kazama
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Patent number: 7477519Abstract: A heat spreading member is received on a predetermined surface of an electronic component. The heat spreading member extends larger than the predetermined surface. A contact piece is contacted with the heat spreading member over a contact area smaller than the predetermined surface. The contact piece serves to realize concentration of an urging force applied to the heat spreading member. The heat spreading member is thus reliably urged against the electronic component. The concentration of the urging force serves to prevent the heat spreading member and the electronic component from camber even if heat is applied to the heat spreading member and the electronic component. Separation is thus avoided between the heat spreading member and the electronic component. The heat spreading member reliably keeps contacting with the electronic component, so that the electronic component package is allowed to enjoy improvement in heat radiation.Type: GrantFiled: October 28, 2005Date of Patent: January 13, 2009Assignee: Fujitsu LimitedInventor: Hideo Kubo
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Publication number: 20090001554Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.Type: ApplicationFiled: June 26, 2007Publication date: January 1, 2009Applicant: INFINEON TECHNOLOGIES AGInventor: Ralf Otremba
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Publication number: 20090001555Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.Type: ApplicationFiled: June 26, 2008Publication date: January 1, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Hideko ANDO
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Publication number: 20080246141Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern.Type: ApplicationFiled: June 12, 2008Publication date: October 9, 2008Applicant: Kabushiki Kaisha ToshibaInventor: Kazutaka Takagi
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Patent number: 7365423Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.Type: GrantFiled: April 20, 2007Date of Patent: April 29, 2008Assignee: International Rectifier CorporationInventor: Mark Pavier
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Patent number: 7332802Abstract: A package for semiconductor light emitting element is described. The package includes a first metal substrate having a cup shaped recess portion, an insulating member having a first cup shaped opening, provided on the first metal substrate, and a second metal substrate having a second cup shaped opening, provided on the insulating member with being electrically insulated from the first metal substrate, having a cavity in the inner surface.Type: GrantFiled: June 22, 2005Date of Patent: February 19, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Kuniaki Konno
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Patent number: 7329957Abstract: A method of manufacturing a circuit device includes the steps of preparing a conductive foil, forming conductive patterns in convex shapes by forming an isolation trench on a surface of the conductive foil, covering the surface of the conductive foil with a resin film so as to form the resin film covering the isolation trench thicker than the resin film covering upper surfaces of the conductive patterns, exposing the upper surfaces of the conductive patterns out of the resin film by removing the resin film, electrically connecting the conductive pattern exposed out of the resin film to a circuit element, forming sealing resin to seal the circuit element, and removing a rear surface of the conductive foil until the conductive patterns are mutually isolated.Type: GrantFiled: March 21, 2005Date of Patent: February 12, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Jun Sakano, Kouji Takahashi, Yusuke Igarashi
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Patent number: 7298046Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.Type: GrantFiled: January 10, 2003Date of Patent: November 20, 2007Assignee: Kyocera America, Inc.Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
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Patent number: 7295436Abstract: A power supply housing (12) is mounted inside of a computer housing (10). Housing (12). It includes components (34) that generate heat when the computer is being used. The power supply housing (12) is sealed in order to make it leak proof. A radiator is positioned outside of the power supply housing (12). It includes a coil assembly having an inlet and an outlet. The inlet is connected to an outlet leading out from the power supply housing (12). The outlet is connected to the inlet of the power supply housing (12). During use of the computer, a cooling fluid is circulated through the coil assembly of the radiator and the power supply housing (12). A fan is positioned outwardly of the radiator and is used to cool the cooling fluid when it is in the coil assembly of the radiator.Type: GrantFiled: December 10, 2005Date of Patent: November 13, 2007Inventor: Kioan Cheon
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Patent number: 7279023Abstract: Discontinuous diamond particulate containing metal matrix composites of high thermal conductivity and methods for producing these composites are provided. The manufacturing method includes producing a thin reaction formed and diffusion bonded functionally graded interactive SiC surface layer on diamond particles. The interactive surface converted SiC coated diamond particles are then disposed into a mold and between the particles and permitted to rapidly solidify under pressure. The surface conversion interactive SiC coating on the diamond particles achieves minimal interface thermal resistance with the metal matrix which translates into good mechanical strength and stiffness of the composites and facilitates near theoretical thermal conductivity levels to be attained in the composite. Secondary working of the diamond metal composite can be performed for producing thin sheet product.Type: GrantFiled: October 2, 2003Date of Patent: October 9, 2007Assignee: Materials and Electrochemical Research (MER) CorporationInventors: Sion M. Pickard, James C. Withers, Raouf O. Loutfy
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Patent number: 7276788Abstract: A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.Type: GrantFiled: August 25, 1999Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7259450Abstract: A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.Type: GrantFiled: April 25, 2003Date of Patent: August 21, 2007Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Eugene H. Cloud, Larry D. Kinsman
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Patent number: 7242028Abstract: A light source that utilizes light emitting diodes that emit white light is disclosed. The diodes are mounted on an elongate member having at least two surfaces upon which the light emitting diodes are mounted. The elongate member is thermally conductive and is utilized to cool the light emitting diodes. In the illustrative embodiment, the elongate member is a tubular member through which a heat transfer medium flows.Type: GrantFiled: November 8, 2004Date of Patent: July 10, 2007Assignee: Optolum, Inc.Inventor: Joel M. Dry
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Patent number: 7242085Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.Type: GrantFiled: September 22, 2004Date of Patent: July 10, 2007Assignee: NEC Electronics CorporationInventor: Futoshi Hosoya
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Patent number: 7235877Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.Type: GrantFiled: September 21, 2005Date of Patent: June 26, 2007Assignee: International Rectifier CorporationInventor: Mark Pavier
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Patent number: 7221048Abstract: A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage structures.Type: GrantFiled: February 1, 2005Date of Patent: May 22, 2007Assignee: Infineon Technologies AGInventors: Frank Daeche, Jochen Dangelmaier, Stefan Paulus, Bernd Stadler, Horst Theuss, Michael Weber
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Patent number: 7205652Abstract: An electronic assembly includes a first substrate and a second substrate. The first substrate includes a first surface having a first plurality of conductive traces formed on an electrically non-conductive layer. The second substrate includes a first surface having a second plurality of conductive traces formed thereon and a second surface having a third plurality of conductive traces formed thereon. A first electronic component is electrically coupled to one or more of the plurality of conductive traces on the first surface of the second substrate. At least one of a plurality of conductive interconnects is incorporated within each solder joint that electrically couples one or more of the conductive traces formed on the second surface of the second substrate to one or more of the conductive traces formed on the first substrate.Type: GrantFiled: March 23, 2005Date of Patent: April 17, 2007Assignee: Delphi Technologies, IncInventors: M. Ray Fairchild, Dwadasi H. R. Sarma, Derek B. Workman, Daniel R. Harshbarger
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Patent number: 7170171Abstract: Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or otherwise disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures, such as solder balls, are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures or fabricated on the surface of the semiconductor device or other substrate. For example, stereolithographic techniques may be used to form the rings.Type: GrantFiled: March 9, 2005Date of Patent: January 30, 2007Assignee: Micron Technology, Inc.Inventor: Ford B. Grigg
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Patent number: 7145230Abstract: The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.Type: GrantFiled: December 30, 2004Date of Patent: December 5, 2006Assignee: NEC Electronics CorporationInventor: Futoshi Hosoya
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Patent number: 7112881Abstract: A semiconductor device allowing simplification of a fabrication process is provided. This semiconductor device comprises a first insulator film, consisting of a single material, formed to be in contact with the upper surface of a semiconductor chip including a circuit, a first wire formed to be in contact with the upper surface of the first insulator film and a second wire formed to extend along the side surface and the lower surface of the semiconductor chip and connected to the lower surface of the first wire exposed by partially removing the first insulator film.Type: GrantFiled: September 22, 2004Date of Patent: September 26, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Takayuki Kaida, Ryu Shimizu, Mitsuru Okigawa, Tetsuya Miwa, Takashi Noma
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Patent number: 7098533Abstract: A printed circuit board (PCB) with a heat dissipation element, a method for manufacturing the PCB, and a semiconductor package using the PCB dissipates heat generated from the semiconductor chip and reduces a printed circuit board height. The PCB includes a heat sink panel, an alloy panel attached to one surface of the heat sink panel serving to ground and to dissipate heat, a circuit pattern layer having via holes formed on one surface of the alloy panel and electrically coupled to the alloy panel, and a cavity formed by perforating the circuit pattern layer and the alloy panel. A semiconductor chip is on the heat sink panel in the cavity and electrically coupled to the circuit pattern layer. The alloy panels with the circuit patterns can be manufactured in pairs with an insulation carrier therebetween. A plurality of dissipation protrusions can be formed on the surface of the alloy panel or the surface of the heat sink panel to couple the same.Type: GrantFiled: September 7, 2004Date of Patent: August 29, 2006Assignee: LG Electronics Inc.Inventors: Sung Gue Lee, Yong Il Kim
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Patent number: 7087937Abstract: A light emitting diode (LED) packaging comprising a stacked substrate, a main body, and an LED die is provided. The stacked substrate includes a heat spreader and a first circuit board. The first circuit board is stacked on the heat spreader. Two channels penetrate the first circuit board and the heat spreader. An upper opening of the channel is smaller than a lower opening thereof. The main body is formed on the first circuit board and has a through hole to expose part of the first circuit board. The main body further has at least two extended portion filling the channels for fixing the main body on the stacked substrate. The LED die is located in the through hole and electrically connected to the first circuit board.Type: GrantFiled: July 20, 2005Date of Patent: August 8, 2006Assignee: Lustrous Technology Ltd.Inventor: Chia Chi Liu
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Patent number: 7081661Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.Type: GrantFiled: March 13, 2002Date of Patent: July 25, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa
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Patent number: 7071551Abstract: A semiconductor-producing/examining device that can maintain a preferable connection state for a predetermined period of time and that can easily remove a ceramic substrate from a supporting case. The semiconductor producing/examining device includes a ceramic substrate having a conductor layer formed on the surface thereof or inside thereof and a supporting case. An external terminal is connected to the conductor layer. A connection between the conductor layer and the external terminal is performed such that the external terminal is pressed on the conductor layer or the external terminal is pressed on another conductor layer connected to the conductor layer by using the elastic force and the like of an elastic body.Type: GrantFiled: May 28, 2001Date of Patent: July 4, 2006Assignee: Ibiden Co., Ltd.Inventors: Yasuji Hiramatsu, Yasutaka Ito
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Patent number: 7049695Abstract: A structure and method are provided for dissipating heat from a semiconductor device chip. A first layer of a dielectric material (e.g. polyimide) is formed on a front side of a heat spreader (typically Si). A plurality of openings are formed through this first layer; the openings are filled with metal (typically Cu), thereby forming metal studs extending through the first layer. A second layer of metal is formed on the backside of the device chip. The first layer and the second layer are then bonded in a bonding process, thereby forming a bonding layer where the metal studs contact the second layer. The bonding layer thus provides a thermal conducting path from the chip to the heat spreader.Type: GrantFiled: January 14, 2005Date of Patent: May 23, 2006Assignee: International Business Machines CorporationInventor: H. Bernhard Pogge
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Patent number: 7012192Abstract: A terminal assembly for active implantable medical devices includes a structural pad, in the form of a substrate or attached wire bond pad, for convenient attachment of wires from the circuitry inside the implantable medical device.Type: GrantFiled: March 30, 2005Date of Patent: March 14, 2006Inventors: Robert A. Stevenson, Richard L. Brendel, Christine Frysz, Haytham Hussein, Scott Knappen
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Patent number: 6992382Abstract: A method and apparatus for cooling an electronics chip with a cooling plate having integrated micro channels and manifold/plenum made in separate single-crystal silicon or low-cost polycrystalline silicon. Forming the microchannels in the cooling plate is more economical than forming the microchannels directly into the back of the chip being cooled. In some embodiments, the microchannels are high-aspect-ratio grooves formed (e.g., by etching) into a polycrystalline silicon cooling base, which is then attached to a cover (to contain the cooling fluid in the grooves) and to the back of the chip.Type: GrantFiled: December 29, 2003Date of Patent: January 31, 2006Assignee: Intel CorporationInventors: Gregory M. Chrysler, Ravi Prasher
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Patent number: 6963130Abstract: A semiconductor package has a printed circuit board, an integrated circuit chip on the printed circuit board with an exposed semiconductor die, and a rigid structure secured to the printed circuit board and enclosing the exposed semiconductor die. The exposed surface of the semiconductor die placed is in thermal contact with an inner surface of the rigid structure with a compressible material.Type: GrantFiled: September 8, 2004Date of Patent: November 8, 2005Assignee: Volterra Semiconductor CorporationInventor: Ognjen Djekic
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Patent number: 6882040Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.Type: GrantFiled: April 28, 2004Date of Patent: April 19, 2005Assignee: NEC Electronics CorporationInventor: Futoshi Hosoya
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Patent number: 6879033Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.Type: GrantFiled: July 3, 2003Date of Patent: April 12, 2005Assignee: NEC Electronics CorporationInventor: Futoshi Hosoya
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Patent number: 6867491Abstract: An integrated circuit chip package having a metal substrate core having two or more electrically isolated regions, wherein the electrically isolated regions of the metal substrate core may be coupled with voltage rails of an integrated circuit chip.Type: GrantFiled: December 19, 2001Date of Patent: March 15, 2005Assignee: Intel CorporationInventors: John Guzek, Dustin Wood
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Patent number: 6861745Abstract: A method and apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein, is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond layer and to electrically communicate with the semiconductor device. The heat produced from the semiconductor device and thermally conducting through the conductive pads is thermally conducted to the heat sink or diamond layer and away from the interconnections, i.e., solder bump connections, between a semiconductor device and a carrier substrate in a flip-chip assembly. As a result, thermal fatigue is substantially prevented in a flip-chip assembly.Type: GrantFiled: January 23, 2002Date of Patent: March 1, 2005Assignee: Micron Technology, Inc.Inventors: Salman Akram, Alan G. Wood
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Patent number: 6853066Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.Type: GrantFiled: April 28, 2004Date of Patent: February 8, 2005Assignee: NEC Electronics CorporationInventor: Futoshi Hosoya
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Patent number: 6853082Abstract: An integrated circuit device and methods of producing such device. The device has a substrate, e.g., silicon. An insulating layer is formed overlying the substrate. A copper metal layer is overlying the insulating layer. The device also has an etch stop layer overlying the copper metal layer and an interlayer dielectric material overlying the etch stop layer. The interlayer dielectric material includes an upper surface. A plurality of via openings are defined within a region of the interlayer dielectric layer from the upper surface through the etch stop layer to the copper metal layer. The device has a copper fill material within each of the plurality of via openings to define a plurality of copper structure extending from the upper surface through the etch stop layer to the copper metal layer. A first barrier metal layer is overlying each of the plurality of copper structures to define a first electrode of a capacitor structure.Type: GrantFiled: February 6, 2004Date of Patent: February 8, 2005Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Zhen Chen, Wong Chen Shih
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Patent number: 6853068Abstract: A semiconductor package has a printed circuit board, an integrated circuit chip on the printed circuit board with an exposed semiconductor die, and a rigid structure secured to the printed circuit board and enclosing the exposed semiconductor die. The exposed surface of the semiconductor die placed is in thermal contact with an inner surface of the rigid structure with a compressible material.Type: GrantFiled: May 22, 2002Date of Patent: February 8, 2005Assignee: Volterra Semiconductor CorporationInventor: Ognjen Djekic
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Patent number: 6847110Abstract: A method and apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein, is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond layer and to electrically communicate with the semiconductor device. The heat produced from the semiconductor device and thermally conducting through the conductive pads is thermally conducted to the heat sink or diamond layer and away from the interconnections, i.e., solder bump connections, between a semiconductor device and a carrier substrate in a flip-chip assembly. As a result, thermal fatigue is substantially prevented in a flip-chip assembly.Type: GrantFiled: February 12, 2003Date of Patent: January 25, 2005Assignee: Micron Technology, Inc.Inventors: Salman Akram, Alan G. Wood
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Patent number: 6841857Abstract: An electronic component and a system carrier having a heat conduction block, on which overlapping inner flat conductor ends are fixed mechanically and insulated electrically by an organoceramic layer (6). In addition, methods of producing the system carrier and the electronic component are encompassed.Type: GrantFiled: July 18, 2002Date of Patent: January 11, 2005Assignee: Infineon Technologies AGInventors: Gottfried Beer, Robert Bergmann, Heng Wan Jenny Hong
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Patent number: 6816375Abstract: A new heat sink apparatus and method that simplify the assembly of the heat sink and thermal stud. The new heat sink assembly uses a spring retainer that, in most cases, can use existing socket mounting screws. A spring clip presses a thermal stud against the back of an electrical device package. The present invention is especially useful for attaching a spatial light modulator to a printed circuit board since it provides a simple, reliable heat sink without blocking the light path to and from the device.Type: GrantFiled: August 1, 2002Date of Patent: November 9, 2004Assignee: Texas Instruments IncorporatedInventor: Satyan Kalyandurg
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Liquid crystal display devices having fill holes and electrical contacts on the back side of the die
Patent number: 6809337Abstract: A method of fabricating LCOS devices and testing them at the wafer-scale to identify known-bad dice, to facilitate completing fabrication of only known-good dice. A wafer-scale transparent electrode glass is temporarily placed over the wafer, and liquid crystal material is injected into the LCOS device cavities through fill holes extending through the wafer. After removing the glass and separating the wafer into dice, only the good dice have their die-scale glass attached, liquid crystal material re-injected, solder bumps affixed, and substrate attached.Type: GrantFiled: April 22, 2002Date of Patent: October 26, 2004Assignee: Intel CorporationInventor: Paul Winer -
Publication number: 20040207074Abstract: Metal MEMS structures are fabricated from metal substrates, preferably titanium, utilizing micromachining processes with a new deep etching procedure to provide released microelectromechanical devices. The deep etch procedure includes metal anisotropic reactive ion etching utilizing repetitive alternating steps of etching and side wall protection. Variations in the timing of the etching and protecting steps produces walls of different roughness and taper. The metal wafers can be macomachined before forming the MEMS structures, and the resulting wafers can be stacked and bonded in packages.Type: ApplicationFiled: April 14, 2004Publication date: October 21, 2004Applicant: The Regents of the University of CaliforniaInventors: Noel C. MacDonald, Marco F. Aimi
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Patent number: 6806563Abstract: A chip package comprises a substrate with a composite capacitor/stiffener on the substrate. In one embodiment of the present invention, the substrate comprises a plurality of dielectric layers and a plurality of metallic layers interlaced with the dielectric layers. One of the metallic layers is on a surface of the substrate. Another dielectric layer is adhered onto the one metallic layer. A metallic plate is adhered onto the other dielectric layer, opposite the one metallic layer. The metallic plate is electrically connected to power or ground. The one metallic layer is electrically connected to ground or power, respectively, such that the metallic plate, the other dielectric layer and the one metallic layer form a capacitor. The one metallic layer is joined to a respective one of the plurality of dielectric layers in a same manner as another of the plurality of metallic layers is joined to another, respective one of the plurality of dielectric layers.Type: GrantFiled: March 20, 2003Date of Patent: October 19, 2004Assignee: International Business Machines CorporationInventors: James Patrick Libous, Joseph Maryan Milewski
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Patent number: 6806567Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conducting filled gel elastomer material or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material is applied between a die surface and the inside attachment surface of a cap-style heat sink to eliminate overpressure on the die/substrate interface.Type: GrantFiled: April 12, 2001Date of Patent: October 19, 2004Assignee: Micron Technology, Inc.Inventor: David R. Hembree
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Patent number: 6784537Abstract: A semiconductor device of a surface-mounting type has a mount surface and includes a semiconductor chip having a first surface, a second surface, a heat-generating portion located nearer to the second surface than the first surface and that generates heat during operation, and at least one patterned electrode formed on the second surface. A resin covers the semiconductor chip and an electrode terminal is extracted from the first surface of the semiconductor chip. A mounting face of the electrode terminal and a surface of the at least one patterned electrode are exposed to be substantially flush with a plane of the mount surface, and a perimeter of the at least one patterned electrode is surrounded by the resin.Type: GrantFiled: September 10, 2002Date of Patent: August 31, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Koji Moriguchi