Entirely Of Metal Except For Feedthrough Patents (Class 257/708)
-
Patent number: 6773964Abstract: There exist a need in the art for an IC package that prevents the popcorn effect through every process step in forming an electronic device, as well as during operation of the device. This need is met by an integrated circuit package and a method of manufacturing an integrated circuit package which, during dispensing of an adhesive layer includes at least one via formed by dispensing the adhesive layer in a pattern such that it enables the release of vapor trapped in the integrated circuit package after the attachment of the heat spreader.Type: GrantFiled: September 30, 2002Date of Patent: August 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: Xuejun Fan
-
Patent number: 6762935Abstract: An electronic apparatus is provided with an electric part which can be attached to an outer wall of the apparatus body. The electric part has terminals for accomplishing electric connection of the electric part with the apparatus body, and a heat radiating structure for radiating heat generated in the apparatus body. The heat radiating structure is formed by an uneven wall structure, a heat radiating member, a fan and so forth. Accordingly, the electric part can be attached to the electronic apparatus from the outside thereof, and heat generated in the apparatus body of the electronic apparatus can be radiated by the heat radiating structure arranged in the electric parts, so that an electronic part arranged in the electronic apparatus can operate normally without being excessively heated.Type: GrantFiled: July 31, 2001Date of Patent: July 13, 2004Assignee: Fujitsu LimitedInventor: Shigeru Hidewasa
-
Patent number: 6753596Abstract: A resin-sealed semiconductor device includes a metallic plate and a semiconductor element soldered thereto. The metallic plate has a semiconductor element mounting region formed on one surface thereof and a plurality of squared recesses defined lengthwise and crosswise in the one surface at approximately regular intervals at locations other than the semiconductor element mounting region.Type: GrantFiled: May 13, 2003Date of Patent: June 22, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Dai Nakajima, Kiyoshi Ishida, Taketoshi Shikano
-
Patent number: 6744134Abstract: A semiconductor package singulation process is disclosed. The process comprises the step of using at least a portion of a reference fiducial formed on at least one package in a semiconductor package panel comprising a plurality of interconnected packages, the fiducial used to monitor and to control the semiconductor package singulation process.Type: GrantFiled: January 4, 2002Date of Patent: June 1, 2004Assignee: Micron Technology, Inc.Inventors: Jay Roberts, Gregory M. Chapman, John VanNortwick, Zane Drussel
-
Publication number: 20040061217Abstract: A semiconductor package which is improved in thinness and heat radiation and a method for making the same. The package includes a semiconductor chip electrically connected to leads of a leadframe via input and output bond pads. The leadframe may have a ground ring formed therein. The leads and semiconductor chip are at least partially encapsulated by an encapsulant. The semiconductor chip and leads have bottom surfaces which are externally exposed to improve heat radiation and reduce the thickness of the package. The package is made by placing the leadframe having leads onto adhesive tape, affixing a semiconductor chip into an open space on the leadframe, pressurizing the leadframe and chip downwardly for securement to the adhesive tape, electrically connecting input bond pads and output bond pads on the chip to the leads; at least partially encapsulating the leads and semiconductor chip; removing the tape from the bottom surfaces of the leads and chip; and cutting the leadframe to form the package.Type: ApplicationFiled: September 19, 2003Publication date: April 1, 2004Inventors: Jae Hun Ku, Jae Hak Yee
-
Publication number: 20040046247Abstract: A package for encasing one or more semiconductor devices includes a composite base component with opposing first and second surfaces formed from a mixture of metallic powders. A first metallic powder is copper or a copper-base alloy and a second metallic powders is a metal or metal alloy with a coefficient of thermal expansion less than that of copper. There is sufficient copper or copper-base alloy present for the composite base to preferably have a coefficient of thermal expansion of at least 9×10−6/° C. A ring frame formed from a nickel/iron-based alloy having a plurality of interconnections extending through sidewalls thereof is bonded to the composite base by a braze with a melting temperature in excess of 700° C. In an alternative embodiment, the composite base brazed to a frame formed from a ceramic having a coefficient of thermal expansion in excess of 8×10−6/° C.Type: ApplicationFiled: September 3, 2003Publication date: March 11, 2004Applicant: Olin Corporation, a corporation of the Commonwealth of VirginiaInventor: Steven A. Tower
-
Patent number: 6696747Abstract: A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.Type: GrantFiled: October 13, 2000Date of Patent: February 24, 2004Assignee: Amkor Technology, Inc.Inventors: Tae Heon Lee, Mu Hwan Seo
-
Publication number: 20040021216Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.Type: ApplicationFiled: July 3, 2003Publication date: February 5, 2004Inventor: Futoshi Hosoya
-
Patent number: 6680530Abstract: In packaging integrated circuits for high speed (multi-gigabit) applications, chip carriers having signal paths between the substrate board and the chips at the top with a number of evenly divided vertical steps produces frequency properties that are sufficiently good that it is possible to run signals through the package, rather than by means of connectors attached to the top surface of the carrier.Type: GrantFiled: August 12, 2002Date of Patent: January 20, 2004Assignee: International Business Machines CorporationInventors: Edward R. Pillai, Warren D. Dyckman
-
Patent number: 6670704Abstract: A device (1,21,28, 36, 37, 86, 103, 121, 128) for electronic packaging, the device including a discrete solid body having a pair of opposing generally parallel major surfaces, the solid body having a body portion of a porous valve metal oxide based material with a pair of exterior surfaces respectively constituting portions of the major surfaces and extending inward from one major surface towards the other major surface, the body portion having one or more electrically insulated valve metal conductive traces of from about 10 &mgr;m to about 400 &mgr;m thickness in a direction from one major surface to the other major surface embedded therein, one or more of said traces having a trace portion divergingly extending inward from an exterior surface constituting a portion of one of said major surfaces.Type: GrantFiled: February 9, 2001Date of Patent: December 30, 2003Assignee: Micro Components Ltd.Inventors: Shimon Neftin, Uri Mirsky
-
Patent number: 6664624Abstract: A source electrode, a gate electrode, and a drain electrode formed on a front face active region of a semiconductor substrate in a shape of teeth of a comb are covered with an insulating film such as polyimede etc., as well as all of the upper surface and the side surfaces of the insulating film are covered with a metal protective film. Via hole receiving pads connected to the source electrode, the gate electrode, and the drain electrode are respectively connected to bonding pads on a reveres face of the semiconductor substrate through via holes.Type: GrantFiled: May 30, 2002Date of Patent: December 16, 2003Assignee: Fujitsu-Quantum Devices LimitedInventor: Hitoshi Haematsu
-
Patent number: 6649937Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.Type: GrantFiled: March 26, 2002Date of Patent: November 18, 2003Assignee: Intel CorporationInventors: Damion T. Searls, Prateek J. Dujari, Bin Lian
-
Patent number: 6646339Abstract: A semiconductor package which is improved in thinness and heat radiation and a method for making the same. The package includes a semiconductor chip electrically connected to leads of a leadframe via input and output bond pads. The leadframe may have a ground ring formed therein. The leads and semiconductor chip are at least partially encapsulated by an encapsulant. The semiconductor chip and leads have bottom surfaces which are externally exposed to improve heat radiation and reduce the thickness of the package. The package is made by placing the leadframe having leads onto adhesive tape, affixing a semiconductor chip into an open space on the leadframe, pressurizing the leadframe and chip downwardly for securement to the adhesive tape, electrically connecting input bond pads and output bond pads on the chip to the leads; at least partially encapsulating the leads and semiconductor chip; removing the tape from the bottom surfaces of the leads and chip; and cutting the leadframe to form the package.Type: GrantFiled: October 13, 2000Date of Patent: November 11, 2003Assignee: Amkor Technology, Inc.Inventors: Jae Hun Ku, Jae Hak Yee
-
Patent number: 6624523Abstract: A structure of a heat spreader substrate. A first heat spreader has a first upper surface, a corresponding first lower surface and an opening. A second heat spreader has a second upper surface and a corresponding second lower surface. The second heat spreader is fit tightly into the opening. The second lower surface and the first lower surface are coplanar. A thickness of the second heat spreader is smaller than that of the first heat spreader. A chip is located on the second upper surface. A substrate is located on the first upper surface of the first heat spreader, and the opening is exposed by the substrate.Type: GrantFiled: June 15, 2001Date of Patent: September 23, 2003Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shin-Hua Chao, Kuan-Neng Liao
-
Publication number: 20030173661Abstract: A contact structure for establishing electrical connection with contact targets. The contact structure is formed of a contactor carrier and a plurality of contactors. The contactor has an upper end oriented in a vertical direction, a straight beam portion oriented in a direction opposite to the upper end and having a lower end which functions as a contact point for electrical connection with a contact target, a return portion returned from the lower end and running in parallel with the straight beam portion to create a predetermined gap therebetween, a diagonal beam portion provided between the upper end and the straight beam portion to function as a spring.Type: ApplicationFiled: April 11, 2003Publication date: September 18, 2003Applicant: Advantest Corp.Inventors: Yu Zhou, David Yu, Robert Edward Aldaz, Theodore A. Khoury
-
Publication number: 20030153128Abstract: A semiconductor device is disclosed in which a heat sink is difficult to warp and which is inexpensive.Type: ApplicationFiled: January 28, 2003Publication date: August 14, 2003Applicant: Hitachi, Ltd.Inventor: Mamoru Ito
-
Patent number: 6555903Abstract: A package structure of a hybrid device in an optical signal transmitter comprises an assembly of a surface emitting laser (SEL), photodiodes, an IC and a passive device, and its application. The package structure further comprises a submount to reduce parasitic capacitance and increase coupling efficiency of the device to the optical fiber, and an electric connect region is formed on the submount to shorten the length of wire and improve the yield. A combination of the SEL and the pair of photodiodes can further applies on a duplexer of single optical fiber.Type: GrantFiled: December 19, 2000Date of Patent: April 29, 2003Assignee: TrueLight CorporationInventors: Yun-Sen Lin, Chang-Cherng Wu, Chao-Fang Li, Meng-Nan Ho
-
Patent number: 6534861Abstract: A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.Type: GrantFiled: November 15, 1999Date of Patent: March 18, 2003Assignee: Substrate Technologies IncorporatedInventor: Abram M. Castro
-
Patent number: 6498294Abstract: The present invention relates to a package for a high-frequency device, in which the characteristic impedance can be matched while a gap between the casing and each terminal is maintained wide enough to avoid contact. In the package for a high-frequency device, each metallic terminal is hermetically fixed to a conductive casing and is electrically insulated from the conductive casing by glass. Each metallic terminal extends in parallel with a side wall of the conductive casing while it is separated from the side wall. Each metallic terminal is also flanked by a pair of conductive protruding portions that are formed on a side wall of the conductive casing and extend in the longitudinal direction of each metallic terminal. The conductive protruding portions are formed on either side of each metallic terminal and serve to match the characteristic impedance.Type: GrantFiled: April 20, 2000Date of Patent: December 24, 2002Assignee: Fujitsu Quantum Devices LimitedInventors: Ryo Kuwahara, Kouichi Iwaida
-
Patent number: 6495913Abstract: A semiconductor clamped-stack assembly (32) has at least two clamped stacks, each of these clamped stacks having a plurality of power semiconductor components (8) and a plurality of heat sinks (6), which are arranged in series along a horizontally extending axial direction (A). According to the invention, power semiconductor components (8) from different clamped stacks are assigned to one another and are located in a common mounting plane, which is perpendicular to the axial directions (A) of the clamped stacks (31). Mutually associated power semiconductor components (8) can be removed from the clamped-stack assembly or, respectively, inserted into the clamped-stack assembly in a common mounting direction, which lies in the mounting plane. Mutually associated power semiconductor components (8) are preferably mounted on a common plate (14). As a result, they can be dismantled when the clamped-stack assembly (32) is loosened, without further power semiconductor components or heat sinks having to be dismantled.Type: GrantFiled: July 24, 2001Date of Patent: December 17, 2002Assignee: ABB Industrie AGInventor: Horst Grüning
-
Patent number: 6495914Abstract: A metal base substrate for mounting a plurality of bare semiconductor chip devices thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of these recesses is smaller than the length of said projection, and the recesses have a higher surface smoothness than said main surfaces of said metal substrate. The metal base substrate is partially chemically etched to form the projection, and the first main surface of the substrate is mechanically worked to form at least the recesses. The conductive projection is isolated from the portion on which the bare semiconductor chip devices are mounted, of the base substrate, and the conductive projection acts as a terminal that can be electrically connected to the outside on the first and second main surfaces of the base substrate.Type: GrantFiled: February 10, 2000Date of Patent: December 17, 2002Assignee: Hitachi, Ltd.Inventors: Kenji Sekine, Hiroji Yamada, Matsuo Yamasaki, Osamu Kagaya, Kiichi Yamashita
-
Patent number: 6492739Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: March 25, 2002Date of Patent: December 10, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
-
Patent number: 6489677Abstract: An optical semiconductor device module includes an optical semiconductor device package, an optical semiconductor device such as a laser diode accommodated in the package, and a cooling area on an inner face of a metal bottom plate of the package and operable to cool the optical semiconductor device. A groove permitting molten solder to flow therein is formed in at least part of the solder joint area on the inner face of the metal bottom plate.Type: GrantFiled: May 3, 2001Date of Patent: December 3, 2002Assignee: The Furukawa Electric Co., Ltd.Inventors: Takahiro Okada, Toshio Kimura
-
Patent number: 6489634Abstract: A microelectronic device structure includes a package flange with a body having a body upper surface, a substantially circular body interior sidewall defining an opening in the body upper surface, and a substantially circular inlay made of CVD diamond. The inlay is received into the substantially circular opening and has an inlay exterior sidewall which is adjacent to the body interior sidewall and is brazed thereto. The inlay has an inlay upper surface that is substantially coplanar with the body upper surface. A microelectronic device is affixed to the inlay upper surface.Type: GrantFiled: August 22, 2001Date of Patent: December 3, 2002Assignee: The Boeing CompanyInventors: Christopher Schaffer, Steven R. Burkhart, Bartley J. Price
-
Patent number: 6455925Abstract: A transistor package comprises a first layer in which a thermally conductive flange is integrated into a dielectric substrate layer, a transistor attached to the flange, and input and output contacts coupled to the transistor. The transistor package is attached to a circuit board such that its input and output contacts are electrically coupled to associated conductors on the circuit board. In one embodiment, the transistor package further comprises additional dielectric layers, bonded to the bottom layer, in which a top layer forms a lid covering the transistor. The layers intermediate the bottom and top layers have central areas cut away where the layers overlap the transistor, thereby forming an interior chamber in the package. Impedance matching networks may also be provided to couple the transistor input and output terminals to their respective contacts, where the matching networks tune the input and output impedances of the package.Type: GrantFiled: March 27, 2001Date of Patent: September 24, 2002Assignee: Ericsson Inc.Inventor: Steven J. Laureanti
-
Patent number: 6433423Abstract: A microchip (3) is mounted to a chip carrier (1) in such a way as to avoid an earth fault between the chip (3) and the carrier (1). When mounting chips, the chip (3) is placed on a chip carrier (1) that includes an electrically and thermally conductive element (13). The element includes a surface (17) and a recess (15) arranged relative to the surface. The microwave chip (3) is arranged at the surface (17) of the electrically and thermally conductive element (13) by means of a fixing or bonding substance (19), which is disposed at least partially in the recess (15). When mounting the chip, the chip (3) is positioned so that an earth plane (3d) of the microwave chip (3) will lie level with the surface (17) of the electrically and thermally conductive element (13). The chip carrier (1) is suitable for a chip mounting process and can be produced both readily and inexpensively.Type: GrantFiled: December 15, 2000Date of Patent: August 13, 2002Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventors: Leif Bergstedt, Torbjörn Nilsson
-
Patent number: 6429509Abstract: A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnect with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules. A process for making the device is further disclosed. To preserve structural integrity of a wafer containing such die during manufacturing, a through-hole via formed as part of the interconnect is filled with an inert material during operations associated with subsequent active device formation on such die.Type: GrantFiled: May 3, 1999Date of Patent: August 6, 2002Assignee: United Microelectronics CorporationInventor: Min-Chih John Hsuan
-
Patent number: 6404065Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.Type: GrantFiled: July 31, 1998Date of Patent: June 11, 2002Assignee: I-XYS CorporationInventor: Kang Rim Choi
-
Patent number: 6403882Abstract: A chip package includes a die having an active surface and an inactive surface. An adhesive is formed on the inactive surface where the adhesive has a low Young's modulus of elasticity. The low Young's modulus of elasticity may be 10,000 psi or less; 1,000 psi or less; or, preferably, about 1,000 psi. Further, the adhesive may include a thermal conducting material. A protective plate is coupled to the inactive surface using the adhesive and a chip carrier is coupled to the active surface of the die.Type: GrantFiled: June 30, 1997Date of Patent: June 11, 2002Assignee: International Business Machines CorporationInventors: William Tze-You Chen, Michael Anthony Gaynes, Eric Arthur Johnson, Tien Yue Wu
-
Patent number: 6400015Abstract: An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.Type: GrantFiled: March 31, 2000Date of Patent: June 4, 2002Assignee: Intel CorporationInventors: David Fraser, Brian Doyle
-
Patent number: 6392308Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: February 28, 2001Date of Patent: May 21, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
-
Patent number: 6384474Abstract: With a housing for accommodating a planar power transistor, a chip of the power transistor is arranged hermetically sealed inside the housing, and metallized areas on the chip lead out of the housing by way of electric terminals. At least in some areas, the housing is formed by at least one of the electric power terminals.Type: GrantFiled: June 1, 2000Date of Patent: May 7, 2002Assignee: Robert Bosch GmbHInventor: Rainer Topp
-
Patent number: 6365961Abstract: A high-frequency input/output feedthrough comprises a lower dielectric substrate in which are formed a bottom face ground layer, side ground layers, a line conductor and cofacial ground layers (formed on both sides of the line conductor on one and the same face of the lower dielectric substrate); and an upper dielectric substrate joined to the lower dielectric substrate so that portions of the line conductor and cofacial ground layers are sandwiched between the lower and upper dielectric substrate. In order to suppress return and insertion losses of signal in millimeter wave range due to a difference in transmission mode to improve transmission characteristics, the upper dielectric substrate is made thicker than the lower dielectric substrate. The width of the portion of the line conductor which is sandwiched between the lower dielectric substrate and the upper dielectric substrate is smaller than that of another portion. The cofacial ground layers are projected toward the line conductor.Type: GrantFiled: January 18, 2000Date of Patent: April 2, 2002Assignee: Kyocera CorporationInventor: Satoru Tomie
-
Publication number: 20020030266Abstract: A semiconductor device comprising a substrate including a metal portion and a resin portion and having a plurality of through holes formed in the resin portion, conductive members formed within the through holes, a semiconductor chip attached to one surface of the substrate, and a plurality of solder balls attached to the other surface of the substrate. The semiconductor chip and solder balls are electrically connected through the conductive members.Type: ApplicationFiled: September 4, 2001Publication date: March 14, 2002Applicant: Seiko Epson CorporationInventor: Akihiro Murata
-
Patent number: 6333519Abstract: A semiconductor apparatus of the type includes a plurality of semiconductor devices arranged in a matrix and each having a principal electrode, an insulating layer coating the semiconductor devices, and a plurality of pixel electrodes (conductor film patterns) each disposed on the insulating film and connected to the principal electrode of semiconductor device through a contact hole formed in the insulating layer.Type: GrantFiled: August 10, 1999Date of Patent: December 25, 2001Assignee: Canon Kabushiki KaishaInventor: Toru Nakazawa
-
Patent number: 6326936Abstract: In an electrode device for addressing a functional element a layer of electrical isolating materials is provided between first and second electrodes intersecting without direct physical or electrical contact and forming a bridge structure. Over both electrodes an electrical conducting or semiconducting contact layer of organic material is provided and contacts both electrodes electrically. In an electrode device with detecting, information storing and/or information indicating function an electrically addressable functional element is provided adjacent to or in the intersection between the electrodes. In an electrode device including two or more electrode device, the electrodes form patterned layers of row and column electrodes in a 2-dimensional matrix, wherein the contact layer forms a patterned or integrated global layer and functional elements which each registers with an electrode intersection in the matrix, are provided in one or more patterned or non-patterned layers.Type: GrantFiled: March 18, 1999Date of Patent: December 4, 2001Assignee: Thin Film Electronics ASAInventors: Olle Werner Inganas, Danilo Pede, Magnus Granström, Geirr Ivarsson Leistad
-
Patent number: 6320270Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat- radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: February 9, 2000Date of Patent: November 20, 2001Assignee: Hitachi, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
-
Patent number: 6319739Abstract: Warpage-free post-mold curing (PMC) of encapsulated device arrays, e.g., TSOPs, is performed without requiring placement of heavy metal weights on the arrays by utilization of molding/encapsulant materials having reduced coefficients of thermal expansion (CTE) and increased flexural moduli at both high and low temperature. Good lead co-planarity is maintained subsequent to PMC as a result of better matching of the encapsulant/molding material properties with those of the IC chip, lead frame, and substrate (e.g., Cu or Cu-based).Type: GrantFiled: April 6, 2000Date of Patent: November 20, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Jeffrey James Pollock
-
Patent number: 6319829Abstract: A semiconductor chip interposer increases fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE. The semiconductor chip interposer includes a thin metal plate having a plurality of through holes, the thin metal plate having a TCE intermediate the relatively high TCE and the relatively low TCE. An insulation coating on the thin metal plate is also included on walls of the through holes. An electrical conductive material fills each of the insulated through holes for electrical interconnection between the first component and the second component.Type: GrantFiled: August 18, 1999Date of Patent: November 20, 2001Assignee: International Business Machines CorporationInventors: Robert W. Pasco, Srinivasa S. N. Reddy, Rao V. Vallabhaneni
-
Patent number: 6314639Abstract: A dense semiconductor flip-chip device is provided with a heat sink/spreading/dissipating member which is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Dice are bonded to the paddles by e.g. conventional die attach methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.Type: GrantFiled: February 23, 1998Date of Patent: November 13, 2001Assignee: Micron Technology, Inc.Inventor: David J. Corisis
-
Patent number: 6303974Abstract: In a housing of a semiconductor device there are provided a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the semiconductor housing. Electrically conductive contact pin arrangements project from electrically insulated channels in the preformed sub-assembly, an inward end of each of the pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip. There is a sheet of electrically conductive material, resting on a base level of an inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of the pin arrangements.Type: GrantFiled: December 7, 1998Date of Patent: October 16, 2001Assignee: Westcode Semiconductors LimitedInventors: Robert Charles Irons, Kevin Robert Billett, Michael John Evans
-
Patent number: 6297959Abstract: A heating element (IC, transistor or the like) is placed on a printed circuit board and silicon grease is coated on the surface of the printed circuit board side of the heating element. The projection portion of a radiator with a step portion is inserted into the through hole of the printed circuit board and closely contacted with the lower portion of the heating element through the silicon grease. As a result, heat generated from the heating element is transferred to the projection portion of the radiator through the silicon grease and then transferred to the entirety of the radiator. Excessive silicon grease is collected in a step portion provided at the base of the projection portion of the radiator and prevented from leaking to other portion such as a portion on the board.Type: GrantFiled: November 10, 1999Date of Patent: October 2, 2001Assignee: Pioneer CorporationInventors: Hitoshi Ueno, Shigeru Yoshida
-
Patent number: 6281573Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips. A path for high thermal conduction (low thermal resistance) from the IC chip to the heat exchanger to the ambient air is provided by an electronic module cover, configured as a cap with a heat exchanger formed or attached as a single construction, and made of the same material as the substrate, or made with materials of compatible thermal coefficients of expansion to mitigate the effects of vertical displacement during thermal cycling.Type: GrantFiled: March 31, 1998Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Eugene R. Atwood, Joseph A. Benenati, Giulio DiGiacomo, Horatio Quinones
-
Patent number: 6265774Abstract: Development of Millimeter Wave Devices containing MMIC's is expedited by use of a new package for the MMIC's and associated electrical components that define the functional circuit. The package includes a base plate and a plurality of metal inserts removeably fastened to the base plate. The inserts are spaced apart and contain a profiled edge with the profiled edge in one in confronting spaced relationship with that of another of the inserts. Together with the backplate, the profiled edges define elongated cavities, serving as two of the cavities side walls. The cavities serve as a repository for the MMIC devices and some of the additional components and stripline. Should extraneous resonances be discovered, the insert can be removed and adjusted in size and profile, and replaced, thereby adjusting the cavity without disturbing the electronic components or MMIC's which are secured to the back plate.Type: GrantFiled: November 19, 1998Date of Patent: July 24, 2001Assignee: TRW Inc.Inventors: Michael D. Sholley, Jeffrey B. Mitchell, Gregory K. Barber, Charles E. Gage, Bruce E. Osgood
-
Patent number: 6262362Abstract: The invention discloses a method for making two sided Multi-Chip Modules (MCMs) that will allow most commercially available integrated circuits to meet the thermal and radiation hazards of the spacecraft environment using integrated package shielding technology. The invention describes the technology and methodology to manufacture MCMs that are radiation-hardened, structurally and thermally stable using 3-dimensional techniques allowing for high density integrated circuit packaging in a radiation hardened package.Type: GrantFiled: July 2, 1998Date of Patent: July 17, 2001Assignee: Maxwell Electronic Components Group, Inc.Inventors: David R. Czjakowski, Neil Eggleston, Janet S. Patterson
-
Patent number: 6242694Abstract: A package for housing a photosemiconductor including a plurality of united-inner/outer-portions type leads each of which has an inner lead portion and an outer lead portion continuously formed into one body; a conductive frame having a side wall and an opening provided on the side wall for introducing the inner lead portions of the plurality of united-inner/outer-portions type leads into an inside of the conductive frame; and a ceramic plate which has a side face for stopping up the opening of the side wall of the conductive frame. The ceramic plate has a plurality of through holes on the side face for inserting the inner lead portions of the plurality of united-inner/outer-portions type leads therethrough. The ceramic plate is joined with the conductive frame so that the side face stops up the opening of the conductive frame.Type: GrantFiled: November 18, 1998Date of Patent: June 5, 2001Assignee: Sumitomo Metal (SMI) Electronics Devices Inc.Inventor: Ichiro Muraki
-
Patent number: 6229088Abstract: An electronic enclosure having a cover and a base member reduced in height by providing the necessary height on the decoupling area around and generally in the same vertical space as is occupied by the thickness of glass provided to hermetically seal the enclosure. The glass is formed inside and kept away from the decoupling area by an inner ring fixed to the base member, or by a tool which is removed after the glass has been applied to seal the enclosure.Type: GrantFiled: January 6, 1999Date of Patent: May 8, 2001Assignee: Legacy Technologies, Inc.Inventor: Jack E. Launtz
-
Patent number: 6204563Abstract: A semiconductor device for mounting on an external substrate includes a semiconductor chip, a high thermal elastic internal substrate and a high elastic liquid resin. The semiconductor chip has bump electrodes formed on its main surface. The high thermal elastic internal substrate includes a conductive pattern on one surface and external electrodes on the other surface. The conductive pattern is electrically connected to the bump electrodes. The external electrodes are electrically connected to the conductive pattern and mounted on the external substrate. The high elastic liquid resin covers the surface of the semiconductor chip, the one surface of the internal substrate and the bump electrodes. The internal substrate has a Young modulus of about 8000 to 15000 kg/mm2, which is larger than a Young modulus of the external substrate.Type: GrantFiled: November 17, 1998Date of Patent: March 20, 2001Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Noritaka Anzai, Yoshimi Egawa
-
Patent number: 6204554Abstract: A surface mount semiconductor package includes washing grooves disposed on a bottom surface of a plastic housing. The package also employs locking elements for locking the plastic housing to a metal pad on which a semiconductor device is mounted, where the locking elements include a cross bar between terminals, slots disposed on the metal pad which include barbs and dove-tail grooves disposed on the metal pad. The metal pad includes a waffled surface for improved coupling to a substrate. The package includes terminals having offset portions for providing spaces for the plastic housing material to fill for improved encapsulation of the terminals. The metal pad extends beyond the lateral edges of the plastic housing for improved heat dissipation and for providing a surface to couple to a heatsink.Type: GrantFiled: July 15, 1997Date of Patent: March 20, 2001Assignee: International Rectifier CorporationInventors: Peter R. Ewer, Arthur Woodworth
-
Patent number: 6184575Abstract: An ultra-thin composite package for integrated circuits including a metal base with a cavity to support a die with a molded plastic cap cooperating with the base to encapsulate the die. A lead frame having a thinned inner portion or lead tip areas may also be used to further reduce the package thickness. Package thicknesses of about 20 mils (0.5 mm) or less can be readily achieved using this structure combination.Type: GrantFiled: August 26, 1994Date of Patent: February 6, 2001Assignee: National Semiconductor CorporationInventors: Satya Chillara, Shahram Mostafazadeh