With Specified Means (e.g., Lip) To Seal Base To Cap Patents (Class 257/710)
  • Patent number: 10109588
    Abstract: An electronic component package includes a frame containing a metal or ceramic based material and having a through-hole, an electronic component disposed in the through-hole, an insulating part at least covering upper portions of the frame and the electronic component, a bonding part at least partially disposed between the frame and the insulating part, and a redistribution part disposed at one side of the frame and the electronic component.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung Won Jeong, Young Gwan Ko, Myung Sam Kang, Tae Hong Min
  • Patent number: 10083886
    Abstract: In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sushumna Iruvanti, Shidong Li, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 10043778
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Meng-Tse Chen, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng
  • Patent number: 9991181
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 5, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Walid M. Meliane, Kevin J. Anderson, Tarak A. Railkar
  • Patent number: 9947716
    Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 17, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu, Shu-Ming Chang, Yu-Lung Huang, Chien-Min Lin
  • Patent number: 9935034
    Abstract: A semiconductor module having a plurality of cooling fins and a fixing cooling fin longer than the plurality of cooling fins, the fixing cooling fin having a threaded hole provided in distal end portion thereof, a cooling jacket having a cooling medium passage in which the plurality of cooling fins and the fixing cooling fin are housed, and an opening formed so as to enable a screw to be inserted in the threaded hole, and a screw passed through the opening to be inserted in the threaded hole, the cooling jacket being fixed to the semiconductor module with the screw are provided.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 3, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koichi Ushijima, Khalid Hassan Hussein, Shoji Saito
  • Patent number: 9847317
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Meng-Tse Chen, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng
  • Patent number: 9607172
    Abstract: An apparatus for providing security for an integrated circuit (IC) chip is disclosed. The apparatus may include the IC chip, attached to a surface of a printed circuit board (PCB). The PCB may include a first, electrically insulative, conformal coating layer attached to the PCB surface and to exposed IC chip surfaces. The PCB may also include a Wheatstone bridge circuit to indicate changes to a second, X-ray opaque, optically opaque and electrically resistive, conformal coating layer. The circuit may include four resistors, formed from second conformal coating layer regions, four sets of electrically conductive pads on the PCB, each set electrically connected to a resistor of the four resistors. The circuit may also include a voltage source, connected to two conductive pads and a monitoring device, connected to another two conductive pads and configured to detect a change of resistance of the Wheatstone bridge.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Doyle, Joseph Kuczynski, Kevin A. Splittstoesser, Timothy J. Tofil
  • Patent number: 9368430
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: June 14, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: 9362209
    Abstract: In accordance with the present invention, there is provided a semiconductor package wherein a metal lid of the package is used as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to an internal die mounting pad of either a leadframe or an alternative type of substrate. Appropriate interconnect methods between the lid, the die pad, and the ground connections exterior to the semiconductor package include, but are not restricted to, conductive adhesives, wire bonding, bumps, tabs, or similar techniques.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: June 7, 2016
    Assignee: Amkor Technology, Inc.
    Inventor: Marc Alan Mangrum
  • Patent number: 9343426
    Abstract: An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: May 17, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Pirooz Parvarandeh
  • Patent number: 9299675
    Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: March 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Navas Khan Oratti Kalandar, Boon Yew Low, Kesvakumar V. C. Muniandy
  • Patent number: 9287523
    Abstract: An organic light emitting diode display includes a lower substrate having an organic light emitting diode thereon, an upper substrate on the lower substrate, an encapsulator between the lower substrate and an upper substrate to encapsulate the organic light emitting diode, the organic light emitting diode being encapsulated between the upper substrate and the lower substrate, a plurality of spacers between the lower substrate and the upper substrate, the plurality of spacers being disposed outside the encapsulator, a dummy metal provided between the spacers and the lower substrate, and a reinforcer on the dummy metal, the reinforcer wrapping the spacers.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung-I Yun, Sang-Min Hong
  • Patent number: 9185792
    Abstract: A package substrate including a circuit board and a heat-dissipating element is provided. The circuit board has a through opening adapted for accommodating an electronic element. The heat-dissipating element is disposed at the circuit board and covers one side of the through opening. The heat-dissipating element includes a heat-dissipating plate, an adhesive layer and an antioxidation layer. The heat-dissipating plate has a first surface facing the through opening and a second surface opposite to the first surface. The adhesive layer is disposed on the first surface and the heat-dissipating plate adheres to the circuit board through the adhesive layer. The antioxidation layer is disposed on the second surface. An electronic assembly including the package substrate is also provided.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: November 10, 2015
    Assignee: MUTUAL-TEK INDUSTRIES CO. LTD.
    Inventor: Chih Ming Chang
  • Patent number: 9164118
    Abstract: A sensor unit includes a motion sensor which detects a motion of an object, outputs a detection value, and is mounted on the object through an attachment, a filter which receives the detection value, passes a given frequency band, and is able to change a cutoff frequency of the frequency band, and a control unit which controls the cutoff frequency, wherein the control unit determines the cutoff frequency in accordance with hardness of the attachment.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 20, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Masatoshi Sato
  • Patent number: 9142470
    Abstract: Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: September 22, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Jicheng Yang, Asif Chowdhury, Manolo Mena, Jia Gao, Richard Sullivan, Thomas Goida, Carlo Tiongson, Dipak Sengupta
  • Patent number: 9076674
    Abstract: A method for combinatorially processing a substrate is provided. The method includes providing a substrate disposed on a substrate support. The method further includes rigidly locking a top portion of a sleeve to a bottom portion of a process head of a combinatorial processing device, where the combinatorial processing device is operable to concurrently process different regions of the substrate differently. The method includes raising the substrate and the substrate support to contact a sealing surface of the sleeve with a surface of the substrate and combinatorially processing the different regions of the substrate.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 7, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Satbir Kahlon
  • Patent number: 9041191
    Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.
    Type: Grant
    Filed: November 19, 2011
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9041192
    Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 26, 2015
    Assignee: Broadcom Corporation
    Inventors: Seyed Mahdi Saeidi, Sam Ziqun Zhao
  • Patent number: 9041182
    Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihiko Nagano, Kazuhide Abe, Hiroshi Yamada, Kazuhiko Itaya, Taihei Nakada
  • Patent number: 9040360
    Abstract: Methods for manufacturing multiple bottom port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from panels of substrates, sidewall spacers, and lids. Each MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port disposed in the substrate. The panels are joined together, and each individual substrate, sidewall spacer, and lid cooperate to form an acoustic chamber for its respective MEMS microphone die. The joined panels are then singulated to form individual MEMS microphones.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 26, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9023689
    Abstract: A top-port, surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a sidewall spacer and a lid with an acoustic port, and the MEMS microphone die is lid-mounted and acoustically coupled to the acoustic port. The substrate, the sidewall spacer, and the lid are joined together to form the MEMS microphone, and the substrate, the sidewall spacer, and the lid cooperate to form an acoustic chamber for the lid-mounted MEMS microphone die.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9024432
    Abstract: A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a sidewall spacer and a lid, and the MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port in the substrate. The substrate, the sidewall spacer, and the lid are joined together to form the MEMS microphone, and the substrate, the sidewall spacer, and the lid cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9018747
    Abstract: An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Kyocera Corporation
    Inventor: Michikazu Nagata
  • Patent number: 9018755
    Abstract: A joint structure includes: a ceramic member; a metallized layer formed on a surface of the ceramic member; and a metal member joined to the metallized layer via a brazing material. The metal member includes a base part erected on the metallized layer, and an extended part extended from the base part to define a predetermined gap with respect to the metallized layer. The base part includes an end joined to the metallized layer by a brazing material layer including the brazing material, and a side joined to the metallized layer around the base part by a fillet including the brazing material formed on the metallized layer around the base part. The extended part defines a recess at a position facing the metallized layer on which the fillet is formed.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 28, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Sadahiro Nishimura, Naoki Tsuda
  • Patent number: 9013036
    Abstract: A sealing member is disclosed, which includes a first structure and a second structure. The first structure includes a groove with an opening towards the outside of the sealing member, wherein the second structure is disposed in the groove. The first structure includes a first material, and the second structure includes a second material, wherein the water absorption rate of the second material is greater than the water absorption rate of the first material. Also, an electronic device using the sealing member is disclosed.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 21, 2015
    Assignee: Wistron Corp.
    Inventor: Chih-Feng Yeh
  • Patent number: 9006868
    Abstract: The invention relates to a component and a method for producing said component. The component comprises a substrate (S), a chip (CH), a frame (MF), which is connected to the substrate (S) and on which the chip (CH) bears. A metallic closure layer (ML) encompasses the frame (MF), the substrate (S) and the chip (CH) such that a volume enclosed by the substrate (S), the chip (CH) and the frame (MF) is hermetically sealed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 14, 2015
    Assignee: EPCOS AG
    Inventors: Christian Bauer, Hans Krüger, Jürgen Portmann, Alois Stelzl
  • Patent number: 9006880
    Abstract: The present invention relates to a surface mount package for a micro-electro-mechanical system (MEMS) microphone die and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components that simplifies manufacturing and lowers costs. The surface mount package features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the MEMS microphone die is mechanically attached, providing an interior surface for making electrical connections between the MEMS microphone die and the package, and providing an exterior surface for surface mounting the microphone package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The microphone package has a substrate with metal pads on its top and bottom surfaces, a sidewall spacer, and a lid.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8946886
    Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: February 3, 2015
    Inventors: Ruben Fuentes, August Joseph Miller, Jr.
  • Publication number: 20140332947
    Abstract: Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 13, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Jicheng Yang, Asif Chowdhury, Manolo Mena, Jia Gao, Richard Sullivan, Thomas Goida, Carlo Tiongson, Dipak Sengupta
  • Patent number: 8872331
    Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Takaaki Koen, Yuto Yakubo, Makoto Yanagisawa, Hisashi Ohtani, Eiji Sugiyama, Nozomi Horikoshi
  • Patent number: 8866289
    Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 21, 2014
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edward Kalvesten, Niklas Svedin, Anders Eriksson
  • Patent number: 8853547
    Abstract: A flexible printed circuit board, in particular for the spatial connection of electronic components, includes a carrier foil (1), several bonding surfaces (10) arranged on a solder side (4) of the carrier foil (1), and several soldering surfaces (2) arranged on a bonding side (12) of the carrier foil (1) opposite the solder side. The soldering surfaces (2) are connected to the bonding surfaces (10) via electrical strip conductors, and a stiffening plate (3) is inseparably connected to the carrier foil (1) on the solder side thereof.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: October 7, 2014
    Assignees: Conti Temic microelectronic GmbH, Carl Freudenberg KG
    Inventors: Andreas Voegerl, Tilo Liebl, Gerhard Bauer, Marion Gebhardt, Alexander Wenk, Matthias Wieczorek, Juergen Henniger, Karl-Heinz Baumann
  • Patent number: 8847383
    Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 30, 2014
    Assignee: ATI Technologies ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio, III
  • Patent number: 8829667
    Abstract: An electronic apparatus includes a main board, a semiconductor package, an upper conductive EMI shield member, and a lower conductive EMI shield member. The main board includes a first ground pad. The semiconductor package is spaced apart from and electrically connected to the main board. The upper conductive EMI shield member covers a top surface and a sidewall of the semiconductor package. The lower conductive EMI shield member surrounds a space between the main board and the semiconductor package, and is electrically connected to the upper conductive EMI shield member and the first ground pad.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Woo Park, Wang-Ju Lee, In-Sang Song
  • Patent number: 8829668
    Abstract: There is provided an electronic device in which the deterioration of the device is prevented and an aperture ratio is improved without using a black mask and without increasing the number of masks. In the electronic device, a first electrode (113) is disposed on another layer different from the layer on which a gate wiring (145) is disposed as a gate electrode, and a semiconductor layer of a pixel switching TFT is superimposed on the gate wiring (145) so as to be shielded from a light. Thus, the deterioration of the TFT is suppressed, and a high aperture ratio is realized.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kazutaka Inukai
  • Patent number: 8816485
    Abstract: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventors: Chris Apanius, Robert A. Shick, Hendra Ng, Andrew Bell, Wei Zhang, Phil Neal
  • Patent number: 8816493
    Abstract: A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 ?/?.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 26, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue, Yoshinori Yokoyama, Jun Fujita, Kazuyo Endo, Shinnosuke Soda, Kazuyasu Nishikawa
  • Patent number: 8796697
    Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
  • Patent number: 8786107
    Abstract: A semiconductor module includes a semiconductor having a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on an opposite surface of the semiconductor substrate. A first conductive member is in contact with the first electrode. A second conductive member is in contact with the second electrode. A third conductive member is in contact with the second conductive member and extends along the first conductive member. An insulating member provides insulation between the first conductive member and the third conductive member. The third conductive member is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. The semiconductor device is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 22, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Norimune Orimoto
  • Patent number: 8765530
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 1, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8754519
    Abstract: According to one embodiment, a package for housing semiconductor element includes: a base plate including a top surface and a recessed portion formed as a downwardly-recessed portion of the top surface; a peripheral wall provided on the top surface of the base plate; a lid provided on an upper side of the peripheral wall and forming a semiconductor element housing space in cooperation with the base plate and the peripheral wall; and a feed-through terminal including a bottom end and fixed to the recessed portion so that the bottom end is located at a lower position than the top surface of the base plate except the recessed portion.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hasegawa
  • Patent number: 8742569
    Abstract: In some examples, a semiconductor package can be configured to electrically couple to a printed circuit board. The semiconductor package can include: (a) a lid having one or more first electrically conductive leads; (b) a base coupled to the lid and having one or more second electrically conductive leads electrically coupled to the one or more first electrically conductive leads; (c) one or more first semiconductor devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads; and (d) one or more first micro-electrical-mechanical system devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads. At least one of the lid or the base can have at least one port hole. The one or more first electrically conductive leads can be configured to couple to the printed circuit board. Other embodiments are disclosed.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: June 3, 2014
    Assignee: Ubotic Intellectual Property Co. Ltd.
    Inventors: Chi Kwong Lo, Lik Hang Wan, Ming Wa Tam
  • Patent number: 8729695
    Abstract: In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 20, 2014
    Assignees: Agency for Science, Technology and Research, Seiko Instruments, Inc.
    Inventors: Chirayarikathu Veedu Sankarapillai Premachandran, Rakesh Kumar, Nagarajan Ranganathan, Won Kyoung Choi, Ebin Liao, Yasuyuki Mitsuoka, Hiroshi Takahashi, Ryuta Mitsusue
  • Patent number: 8704360
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 8704361
    Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Asahi Glass Company, Limited
    Inventor: Hiroki Takahashi
  • Patent number: 8697490
    Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 15, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8698287
    Abstract: A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: April 15, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shin Soyano
  • Patent number: 8674498
    Abstract: An MEMS package is proposed, wherein a chip having MEMS structures on its top side is connected to a rigid covering plate and a frame structure, which comprises a polymer, to form a sandwich structure in such a way that a closed cavity which receives the MEMS structures is formed. Solderable or bondable electrical contact are arranged on the rear side of the chip or on the outer side of the covering plate which faces away from the chip, and are electrically conductively connected to at least one connection pad by means of an electrical connection structure.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: March 18, 2014
    Assignee: Epcos AG
    Inventors: Gregor Feiertag, Hans Krüger, Alexander Schmajew
  • Patent number: 8652883
    Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 18, 2014
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini