Abstract: An electronic element housing package includes a bottom substrate, a bank portion, and a conductor part, in which the bottom substrate and the bank portion are an integrated object made of ceramic, the bottom substrate includes a region surrounded by the bank portion as a mounting portion for mounting an electronic element, the conductor part includes a first conductor, a second conductor, and a third conductor, the first conductor is partially exposed on a mounting surface of the bottom substrate and embedded in the bottom substrate, at least a part of the third conductor is disposed on an upper surface of the bank portion and a part thereof is exposed, and the second conductor is present between the first conductor and the third conductor inside the bottom substrate and the bank portion and electrically connects the first conductor and the third conductor.

Abstract: A silver-plated product which has more excellent minute sliding abrasion resistance property than that of conventional silver-plated products, and a method for producing the same. The silver-plated product is produced by electroplating a base material 10 of copper or a copper alloy to form an underlying plating layer 12 of nickel or a nickel alloy, a first silver-plating layer of silver (lower silver-plating layer) 14, a zinc-plating layer 16 of zinc serving as an intermediate plating layer, and a second silver-plating layer of silver (upper silver-plating layer) 18 serving as a surface layer, in this order from the base material 10.

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The first adhesive element has a first electrical resistivity, and the second adhesive element has a second electrical resistivity. The second electrical resistivity is greater than the first electrical resistivity. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.

Abstract: A heat dissipation structure is provided and includes a heat dissipation body and an adjustment channel. A carrying area and an active area adjacent to the carrying area are defined on a surface of the heat dissipation body, the carrying area is used for applying a first heat dissipation material thereonto, and the adjustment channel is formed in the active area, where one end of the adjustment channel communicates with the outside of the heat dissipation structure, and the other end communicates with the carrying area. Therefore, when the heat dissipation body is coupled to the electronic component by the first heat dissipation material, the adjustment channel can adjust a volume of the first heat dissipation material.

Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

Abstract: Disclosed herein are integrated circuit (IC) packages with thermal interface materials (TIMs) with different material compositions, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a die, and TIM, wherein the die is between the TIM and the package substrate along a vertical axis. The TIM may include a first TIM having a first material composition and a second TIM having a second material composition; the first material composition may be different than the second material composition, and the first TIM and the second TIM may be in different locations along a lateral axis perpendicular to the vertical axis.

Abstract: An ambient temperature sensor is provided that may be coupled to a PCB. The ambient temperature sensor includes a package including a first cap and an insulating structure. The insulating structure is formed of thermally insulating material, and the first cap and the insulating structure delimit a first cavity. A semiconductor device is included and generates an electrical signal indicative of a temperature. The semiconductor device is fixed on top of the insulating structure and arranged within the first cavity. The package may be coupled to the PCB so that the insulating structure is interposed between the semiconductor device and the PCB. The insulating structure delimits a second cavity, which extends below the semiconductor device and is open laterally.

Abstract: Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate, and forming a first adhesive element over the substrate. The first adhesive element has a first electrical resistivity. The method also includes forming a second adhesive element over the substrate. The second adhesive element has a second electrical resistivity, and the second electrical resistivity is greater than the first electrical resistivity. The method further includes attaching a protective lid to the substrate through the first adhesive element and the second adhesive element. The protective lid surrounds the chip structure and covers a top surface of the chip structure.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: Disclosed is a circuit assembly, in particular for a motor vehicle. The circuit assembly comprises a circuit board, an electronic component which is arranged on the circuit board and electrically connected to the circuit board via at least one electrical contact point, and a foamed material sealing element which seals off the electronic component and the at least one electrical contact point in media-tight fashion with respect to surroundings.

Abstract: A light-emitting device includes: a substrate comprising a base; a semiconductor laser element disposed on an upper surface of the base; a sealing member located above the base and fixed to the substrate, wherein the sealing member and the substrate define a sealed space in which the semiconductor laser element is located; and a lens member fixed to the sealing member by adhesive, the lens member comprising a lens section through which light emitted from the semiconductor laser element passes. A space between the sealing member and the lens member is open to an area outside the light-emitting device.

Abstract: Methods, systems, devices, and products for constructing a downhole tool electronics module. Methods may include creating a circuit board by metallizing at least part of a first surface on a first side of a substrate to define at least one metallized area on the first surface, wherein the substrate comprises a ceramic material and includes: the first side, including at least (i) the first surface, and (ii) an elevated surface elevated from the first surface, and a second side opposite the first side; flattening at least partially the elevated surface to a predefined first flatness to create a mounting portion by removing material from the elevated surface; attaching an electronics component to the first surface; and mounting the circuit board on an electronics carrier by adhering at least part of the mounting portion to a mounting surface on the electronics carrier.

Abstract: Various systems and methods for configuring a pluggable computing device are described herein. A pluggable computing device may be configured to be compatible with a pluggable host system using a default communication channel to obtain configuration settings and configure a programmable logic device on the pluggable computing device. The pluggable computing device may perform chain of trust processing on the pluggable host system. The pluggable computing device may be disposed on a compute card, which may include a heat sink in a particular configuration.

Abstract: An electronic component includes a first set comprising an interconnect layer and an electronic circuit having a front face and a back face, which is connected to the interconnect layer by the front face, wherein the first set comprises a metal plate having a front face and a back face joined to the back face of the electronic circuit; a coupling agent between the front face of the metal plate and the back face of the electronic circuit, configured to thermally and electrically connect the metal plate to the electronic circuit; and in that the electronic component comprises: one or more layers made of organic materials stacked around the first set and the metal plate using a printed circuit-type technique and encapsulating the electronic circuit; a thermally conductive metal surface arranged at least partially in contact with the back face of the metal plate.

Abstract: A chip scale package structure of heat-dissipating type is provided and includes a board, a die fixed on and electrically coupled to the board, a thermally conductive adhesive sheet adhered to the die, and a package body formed on the board. The die has a heat-output surface arranged away from the board. The thermally conductive adhesive sheet is connected to at least 50% of an area of the heat-output surface. The package body covers and is connected to the die and entire of the surrounding lateral surface of the thermally conductive adhesive sheet. The die is embedded in the board, the thermally conductive adhesive sheet, and the package body. The heat-dissipating surface of the thermally conductive adhesive sheet is exposed from the package body, and a thermal conductivity of the thermally conductive adhesive sheet is at least 150% of a thermal conductivity of the package body.

Abstract: Provided is a display device including: a base substrate; a light-emitting element provided on one surface side of the base substrate; and a sealing film provided covering the light-emitting element, wherein the sealing film includes a first inorganic film and a second inorganic film sequentially provided covering the light-emitting element, and a resin layer provided in an island shape between the first inorganic film and the second inorganic film.

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

Abstract: A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.

Abstract: An acoustic resonator includes: a substrate; a resonant portion including a center portion in which a first electrode, a piezoelectric layer, and a second electrode are sequentially stacked on the substrate, and an extension portion disposed along a periphery of the center portion; and a first metal layer disposed outwardly of the resonant portion to be electrically connected to the first electrode. The extension portion includes a lower insertion layer disposed on an upper surface of the first electrode or a lower surface of the first electrode. The piezoelectric layer includes a piezoelectric portion disposed in the center portion, and a bent portion disposed in the extension portion and extended from the piezoelectric portion at an incline according to a shape of the lower insertion layer. The lower insertion layer is formed of a conductive material extending an electrical path between the first electrode and the first metal layer.

Abstract: A hermetically sealing device has a sealing main-body and a rubber seal adhered to the sealing main-body. The rubber seal includes an inner lip, a slit and an outer lip. The inner lip extends along a periphery of the bored opening, and includes an outer-circumference surface that extends forward and inclines toward an inner-circumference side. The slit is formed on an outer-circumference side relative to the inner lip. An outer-surface-side edge of the bored opening enters the slit. The outer lip is formed on an outer-circumference side relative to the slit that is formed on an outer-circumference side relative to the inner lip, and transforms in such a manner that the outer lip extends toward an outer-circumference side to be hermetically in contact with an outer surface of the periphery of the bored opening.

Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.

Abstract: A wafer carrier for processing a plurality of wafers includes a carrier body which rotatable about a central axis, and a plurality of pockets formed in the carrier body. Each of the pockets has an access opening and an inner periphery surface extending from the access opening to terminate at a floor surface. A lower periphery region of the inner periphery surface has a most distal region which is most distal from the central axis. When the carrier body is rotated about the central axis, a corresponding one of the wafers is less likely to be damaged due to a centrifugal force applied to the corresponding one of the wafers.

Abstract: An electronic component package includes a frame containing a metal or ceramic based material and having a through-hole, an electronic component disposed in the through-hole, an insulating part at least covering upper portions of the frame and the electronic component, a bonding part at least partially disposed between the frame and the insulating part, and a redistribution part disposed at one side of the frame and the electronic component.

Abstract: In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.

Abstract: A semiconductor module having a plurality of cooling fins and a fixing cooling fin longer than the plurality of cooling fins, the fixing cooling fin having a threaded hole provided in distal end portion thereof, a cooling jacket having a cooling medium passage in which the plurality of cooling fins and the fixing cooling fin are housed, and an opening formed so as to enable a screw to be inserted in the threaded hole, and a screw passed through the opening to be inserted in the threaded hole, the cooling jacket being fixed to the semiconductor module with the screw are provided.

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

Abstract: An apparatus for providing security for an integrated circuit (IC) chip is disclosed. The apparatus may include the IC chip, attached to a surface of a printed circuit board (PCB). The PCB may include a first, electrically insulative, conformal coating layer attached to the PCB surface and to exposed IC chip surfaces. The PCB may also include a Wheatstone bridge circuit to indicate changes to a second, X-ray opaque, optically opaque and electrically resistive, conformal coating layer. The circuit may include four resistors, formed from second conformal coating layer regions, four sets of electrically conductive pads on the PCB, each set electrically connected to a resistor of the four resistors. The circuit may also include a voltage source, connected to two conductive pads and a monitoring device, connected to another two conductive pads and configured to detect a change of resistance of the Wheatstone bridge.

Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Abstract: In accordance with the present invention, there is provided a semiconductor package wherein a metal lid of the package is used as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to an internal die mounting pad of either a leadframe or an alternative type of substrate. Appropriate interconnect methods between the lid, the die pad, and the ground connections exterior to the semiconductor package include, but are not restricted to, conductive adhesives, wire bonding, bumps, tabs, or similar techniques.

Abstract: An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.

Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.

Abstract: An organic light emitting diode display includes a lower substrate having an organic light emitting diode thereon, an upper substrate on the lower substrate, an encapsulator between the lower substrate and an upper substrate to encapsulate the organic light emitting diode, the organic light emitting diode being encapsulated between the upper substrate and the lower substrate, a plurality of spacers between the lower substrate and the upper substrate, the plurality of spacers being disposed outside the encapsulator, a dummy metal provided between the spacers and the lower substrate, and a reinforcer on the dummy metal, the reinforcer wrapping the spacers.

Abstract: A package substrate including a circuit board and a heat-dissipating element is provided. The circuit board has a through opening adapted for accommodating an electronic element. The heat-dissipating element is disposed at the circuit board and covers one side of the through opening. The heat-dissipating element includes a heat-dissipating plate, an adhesive layer and an antioxidation layer. The heat-dissipating plate has a first surface facing the through opening and a second surface opposite to the first surface. The adhesive layer is disposed on the first surface and the heat-dissipating plate adheres to the circuit board through the adhesive layer. The antioxidation layer is disposed on the second surface. An electronic assembly including the package substrate is also provided.

Abstract: A sensor unit includes a motion sensor which detects a motion of an object, outputs a detection value, and is mounted on the object through an attachment, a filter which receives the detection value, passes a given frequency band, and is able to change a cutoff frequency of the frequency band, and a control unit which controls the cutoff frequency, wherein the control unit determines the cutoff frequency in accordance with hardness of the attachment.

Abstract: Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin.

Abstract: A method for combinatorially processing a substrate is provided. The method includes providing a substrate disposed on a substrate support. The method further includes rigidly locking a top portion of a sleeve to a bottom portion of a process head of a combinatorial processing device, where the combinatorial processing device is operable to concurrently process different regions of the substrate differently. The method includes raising the substrate and the substrate support to contact a sealing surface of the sleeve with a surface of the substrate and combinatorially processing the different regions of the substrate.

Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: Methods for manufacturing multiple bottom port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from panels of substrates, sidewall spacers, and lids. Each MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port disposed in the substrate. The panels are joined together, and each individual substrate, sidewall spacer, and lid cooperate to form an acoustic chamber for its respective MEMS microphone die. The joined panels are then singulated to form individual MEMS microphones.

Abstract: A top-port, surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a sidewall spacer and a lid with an acoustic port, and the MEMS microphone die is lid-mounted and acoustically coupled to the acoustic port. The substrate, the sidewall spacer, and the lid are joined together to form the MEMS microphone, and the substrate, the sidewall spacer, and the lid cooperate to form an acoustic chamber for the lid-mounted MEMS microphone die.

Abstract: A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a sidewall spacer and a lid, and the MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port in the substrate. The substrate, the sidewall spacer, and the lid are joined together to form the MEMS microphone, and the substrate, the sidewall spacer, and the lid cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.

Abstract: A joint structure includes: a ceramic member; a metallized layer formed on a surface of the ceramic member; and a metal member joined to the metallized layer via a brazing material. The metal member includes a base part erected on the metallized layer, and an extended part extended from the base part to define a predetermined gap with respect to the metallized layer. The base part includes an end joined to the metallized layer by a brazing material layer including the brazing material, and a side joined to the metallized layer around the base part by a fillet including the brazing material formed on the metallized layer around the base part. The extended part defines a recess at a position facing the metallized layer on which the fillet is formed.

Abstract: An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion.