Abstract: A structure is disclosed for connecting an electrically-connectable metal stiffener to a ground connection within a flexible substrate, the stiffener comprising nickel-gold plated stainless steel. In one embodiment the stiffener is secured to the flexible substrate by a non-conducting adhesive which includes an opening over a ground connection, the adhesive opening being filled by a conductive epoxy. A sequence for applying the disclosed materials discloses a method for attaching the stiffening structure to the flexible substrate.

Abstract: A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method are disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabricated. Next, the device chip and the cap are bonded such that a sealed cavity is formed by the device chip and the cap. The bond is accomplished using thermo compression technique. Gold or other suitable metal can be used as a bonding agent. Then or at the same time, caulking agent is reflowed over the bonding agent, over portions of the cap, or both to further seal the cavity. In the resultant device, the sealed cavity is sealed by the bonding agent, the caulking agent, or both. The caulking agent increases hermeticity of the cavity and provides for even higher level of protection of the cavity against adverse environmental conditions.

Abstract: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.

Abstract: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package.

Abstract: A disclosed semiconductor device comprises a substrate, an element on the substrate and a sealing structure for sealing the element. The sealing structure has a structure such that a partition wall made of a metallic material formed on the substrate by a plating method so as to surround the element and a cap portion disposed on the partition wall are bonded via a bonding layer made of an inorganic material.

Abstract: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance.

Abstract: An inductor integrated chip and fabrication method thereof is provided. The inductor integrated chip includes a wafer; an inductor bonded on a surface of the wafer; a circuit element formed on the surface of the wafer and coupled to a first end of the inductor; a packaging wafer connected to the surface of the wafer and packaging the inductor and the circuit element; and a connecting electrode formed on the packaging wafer and connected to a second end of the inductor. The method includes forming an inductor and a circuit element on a surface of a wafer, wherein the circuit element is coupled to a first end of the inductor; forming a connecting electrode on a packaging wafer; and packaging the inductor and the circuit element by joining the wafer and the packaging wafer so as to connect the connecting electrode with a second end of the inductor.

Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.

Abstract: Side terminals 3 at respective corners of a package are higher than side terminals 4 on each side of the package. Thus, even if the side terminals 4 on each side are lower than those according to the conventional art owing to miniaturization or the like, when a device is mounted on a mounting substrate by soldering, a solder fillet 11 of a sufficient size can be formed between each of the corner side terminals 3, which significantly affect reliability, and a corresponding terminal on the mounting substrate. Thus, the device can be more reliably mounted on the mounting substrate by soldering.

Abstract: A semiconductor device including a package (2) having a plurality of wall portions (9a) and a plurality of conductor portions (4), a semiconductor element such as a solid-state image pickup device (1) mounted in an internal space of the base, thin metal wires (5) electrically connecting the semiconductor element and the conductor portions (4) between the wall portions (9a), a resin sealing material (7) implanted in the spaces between the wall portions (9a), and a closing member such as a cover glass (6). The region for connecting the thin metal wires (5) and the wall portion (9a) region overlap each other, so that the device can be reduced in size and in height. The cover glass (6) can not move easily from the correct position because the wall portions (9a) serve as supporting columns, thereby improving the yield.

Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: A cold welded hermetic micro or nano package sealed in an inert atmosphere with optional force maintenance means for ensuring permanent closure. A package cap 410 coated with precursor weld material is sealed to a package base 405 containing integral device 445 then cold welded with an external force mechanism to compress and flow cold seal preform material 435 creating a hermetic peripheral seal in an inert or vacuum atmosphere. Arrays of devices can be sealed with individual caps or arrays of caps which are interconnected.

Abstract: According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

Abstract: The spacer is formed as an elastic member with no ends thereof, which is detachably attached, by exploiting its elastic deformation, onto a printed wiring board to which is fixed an electronic component having a component package, on one of whose surfaces connection terminals are arranged. Since the spacer is attached on the printed wiring board to enclose an electronic component so as to seal a gap formed between the electronic component and a printed wiring board, it is possible to prevent foreign objects entering the gap, so that failures, such as insufficient insulation, caused by such foreign objects are also prevented. Since the spacer is easily removed from the printed wiring board, it is recyclable and economical.

Abstract: An image sensor module is composed of a base, a CCD image sensor, a glass plate, and a frame-shaped moisture permeable member. The base has a depressed chip chamber, in which the CCD image sensor is contained. Top and under surfaces of the moisture permeable member are provided with adhesive layers. The base and the glass plate are attached above and below the moisture permeable member through the adhesive layers, and the chip chamber is sealed. The moisture permeable member has the property to block liquid water while transmit water vapor, and releases the water vapor produced by the heat of the CCD image sensor from the inside to the outside of the chip chamber.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: An apparatus and method includes an integrated circuit disposed in a ball grid array (“BGA”) package having interconnects on at least one corner without signal assignments.

Abstract: A fabrication method of a wafer level packaging cap for covering a device wafer provided with a device thereon, includes forming an insulating layer on a wafer; removing a predetermined part of the insulating layer and exposing an upper surface of the wafer; forming a cap pad extending from an upper surface and the exposed surface of the wafer; forming a cavity on a lower surface of the wafer corresponding to the cap pad; etching a bottom surface of the cavity and exposing the cap pad which is connected to the wafer through the cavity; and forming metal lines extending from the lower surface of the wafer and the cavity, to electrically connect the cap pad which is exposed through the cavity.

Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.

Abstract: Methods of bulk manufacturing high temperature sensor sub-assembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub-assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attaching wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

Abstract: A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.

Abstract: A cap package for MEMS includes a substrate having a connection zone that is grounded, a chip mounted on the substrate, a cap capped on the substrate and provided with a through hole corresponding to the chip, and a conducting glue made of a non-metal material having a resistivity smaller than 102 ?m. The conducting glue is applied on the connection zone of the substrate and sandwiched between the cap and the substrate for electrically connecting the cap with the substrate.

Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A hermetic seal cover capable of inhibiting defects such as voids from generating in sealing a package, and a method of manufacturing the seal cover are provided. The hermetic seal cover comprises: a seal cover main body; a Ni plating layer applied onto a surface of the seal cover main body; and a Au—Sn brazing material layer fusion bonded to a surface of the Ni plating layer, and is characterized by a Ni—Sn ally layer disposed between the Ni plating layer and the Au—Sn brazing material layer. It is preferable if the Ni—Sn alloy layer has a thickness of 0.6-5.0 ?m. It is also preferable if Au—Sn brazing material layer has a Sn content of 20.65-23.5 wt %.

Abstract: A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment, a more thermally conductive material may be positioned over one or more die hot spots, and a less thermally conductive material may be positioned abutting and/or surrounding the more thermally conductive material. The two or more TIMs may comprise a solder and a polymer. The composite TIM may be preformed as one unit or as a plurality of units. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A die-up array integrated circuit (IC) device package and method of making the same is presented. A frame body has opposing first and second surfaces and a central opening that is open at the first and second surfaces. The second frame body surface is mounted to a first stiffener surface. An IC die is mounted to the first stiffener surface within the central opening through the frame body. A planar lid has opposing first and second surfaces. The second lid surface is coupled to the first frame body surface. A first substrate surface is coupled to a second stiffener surface. An array of electrically conductive terminals is coupled to a second substrate surface. The stiffener, frame body, and lid form an enclosure structure substantially enclosing the IC die. The die enclosure spreads heat from the IC die, and shields EMI emanating from and radiating toward the IC die.

Abstract: A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Abstract: A light emitting die package and a method of manufacturing the die package are disclosed. The die package includes a leadframe, at least one light emitting device (LED), a molded body, and a lens. The leadframe includes a plurality of leads and has a top side and a bottom side. A portion of the leadframe defines a mounting pad. The LED device is mounted on the mounting pad. The molded body is integrated with portions of the leadframe and defines an opening on the top side of the leadframe, the opening surrounding the mounting pad. The molded body further includes latches on the bottom side of the leadframe. The lens is coupled to the molded body. A composite lens is used as both reflector and imaging tool to collect and direct light emitted by LED(s) for desired spectral and luminous performance.

Abstract: A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.

Abstract: A micro-electro-mechanical system (MEMS) package having a side double-sealing member and method of manufacturing the MEMS package is disclosed. The MEMS package is formed by forming a metal layer on a base substrate by patterning so that the metal layer surrounds an MEMS element provided on the base substrate, joining a lid glass to the metal layer, and providing a side double-sealing member on a surface of the base substrate and a side surface of the lid glass, thus hermetically sealing the MEMS element from the external environment.

Abstract: A cooling device including a thermally conductive body with a first mating surface, a first solder wettable material disposed in a pattern at a portion of the first mating surface, and a reflowable solder material disposed at the first mating surface. A portion of the solder material is configured to be capable of contacting an adjacently disposed second mating surface, and when melted, to form a single flow front through a bond line gap between the first mating surface of the cooling device and the second mating surface of, for example, a thermal component. A mating surface of the cooling device is positioned adjacent to a mating surface of a thermal component and the solder material is heated at least to its melting point.

Abstract: An electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate. A second signal line connected to an outside connection electrode and a second ground conductor are formed on a second surface of the dielectric substrate. The first ground conductor and the second ground conductor are connected by a plurality of ground conductor via-holes. A substrate-buried signal line connected to the first signal line and the second signal line is provided inside of the dielectric substrate so as to be put between the first ground conductor and the second ground conductor above and below and between the ground conductor via-holes on the right and left.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: A waferscale package system is provided forming a protection structure comprises forming a wafer, fabricating a device element on the wafer, forming a waferscale spacer around the device element, and attaching a waferscale cap to the waferscale spacer to cover the device element, attaching a carrier to the protection structure, and molding an encapsulant around the protection structure to the carrier.

Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.

Abstract: An encapsulation for a device is disclosed. Spacer particles are randomly located in the device region to prevent a cap mounted on the substrate from contacting the active components, thereby protecting them from damage. The spacer particles are fixed to one side of the substrate to prevent any movement.

Abstract: A micro-electro-mechanical system (MEMS) package having a hydrophobic layer is disclosed. The MEMS package includes: a base substrate, with an MEMS element provided on a surface of the base substrate; a lid, spaced apart from the MEMS element provided on the base substrate and covering the MEMS element; a side sealing member provided on a side surface of the base substrate and the surface of the lid, thus hermetically sealing the MEMS element from an external environment; and a hydrophobic layer which covers the part of the side sealing member that is exposed to the external environment, thus removing the hydrophilia from the side sealing member.

Abstract: The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a barrier of transfer mold compound and covering the chip with a transparent lid. In another embodiment of the invention, the perimeter area of a chip, including interconnections such as wire bonds and bond pads, is encapsulated with a liquid dispensed epoxy, and a transparent lid is attached. In yet another embodiment of the invention, chip encapsulation is accomplished with a unitary shell of entirely transparent material. In yet another embodiment of the invention, a substrate-mounted chip and a transparent lid are loaded into a transfer mold that holds them in optimal alignment. The transfer mold is then filled with molding compound.

Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Abstract: A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal space of the housing and an external terminal portion exposed at an outer portion of the housing; an imaging element arranged on the base in the internal space of the housing; connecting members connecting electrodes of the imaging element to the internal terminal portions of the metal lead pieces; and a transparent plate fastened to an upper face of the ribs. The upper face of the ribs is provided with a lower step portion that is lowered along an external periphery, and the transparent plate is fastened to the upper face of the ribs by an adhesive filled at least into the lower step portion.

Abstract: A microdevice (20) having a hermetically sealed cavity (22) to house a microstructure (26). The microdevice (20) comprises a substrate (30), a cap (40), an isolation layer (70), at least one conductive island (60), and an isolation trench (50). The substrate (30) has a top side (32) with a plurality of conductive traces (36) formed thereon. The conductive traces (36) provide electrical connection to the microstructure (26). The cap (40) has a base portion (42) and a sidewall (44). The sidewall (44) extends outwardly from the base portion (42) to define a recess (46) in the cap (40). The isolation layer (70) is attached between the sidewall (44) of the cap (40) and the plurality of conductive traces (36). The conductive island (60) is attached to at least one of the plurality of conductive traces (36). The isolation trench (50) is positioned between the cap (40) and the conductive island (60) and may be unfilled or at least partially filled with an electrically isolating material.

Abstract: A plasma display device which has improved performance of heat dissipation and noise/vibration insulation is disclosed. In one embodiment, the plasma display device includes a plasma display panel, a first base member coupled with the plasma display panel, a second base member connected to the first base member, and a thermally conductive cushion member interposed between the first base member and the second base member.

Abstract: A micro-electro-mechanical system (MEMS) package having a metal sealing member is disclosed. The MEMS package is formed by forming a metal layer on a substrate by patterning so that the metal layer surrounds an MEMS element provided on the substrate; joining a lid to the metal layer; providing a side sealing member on a side surface of the substrate; and covering the lid and the substrate with a metal sealing member, thus hermetically sealing the MEMS element from the external environment.

Abstract: A fluid-cooled electronic assembly including a base having a fluid inlet and a fluid outlet therein, a cap attached to the base to form a fluid containment chamber therebetween, wherein the fluid containment chamber is in fluid communication with the fluid inlet and the fluid outlet, and an electronic device disposed within the fluid containment chamber and connected to the base, the electronic device having a plurality of microchannels adapted to receive a cooling fluid flow therethrough, wherein the cap is shaped to direct a fluid flow from the fluid inlet to the microchannels such that a pressure drop between the fluid inlet and the fluid outlet is reduced.

Abstract: A swage hermetic sealing of a MEMS or microdevice or nanodevice package using high force. A cutting and flowing edge 430 is formed on a package cover which is pressed into a mating , integral gasket 425 on a package base. A material extension of the package cover 450 is simultaneously folded under the package base to supply force maintenance for permanent hermaticity. The swage hermetic sealing of single or an array of covers to an extended wafer or substrate is accomplished by a cutting and flowing edge 560. Permanent force maintenance is achieved through a re-entrant cavity 565 and annular ring 535 on the wafer or substrate.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A package for semiconductor light emitting element is described. The package includes a first metal substrate having a cup shaped recess portion, an insulating member having a first cup shaped opening, provided on the first metal substrate, and a second metal substrate having a second cup shaped opening, provided on the insulating member with being electrically insulated from the first metal substrate, having a cavity in the inner surface.

Abstract: A microelectronic assembly is provided, comprising at least a first microelectronic die carrying a microelectronic circuit, at least a first periphery seal attached to an edge of a surface of the microelectronic die, at least a first solder thermal interface material attached to a central region of the surface of the microelectronic die, the solder thermal interface material having a higher thermal conductivity than the periphery seal, and a thermally conductive member attached to the periphery seal and the solder thermal interface material on a side thereof opposing the microelectronic die.