With Specified Means (e.g., Lip) To Seal Base To Cap Patents (Class 257/710)
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Patent number: 8829668Abstract: There is provided an electronic device in which the deterioration of the device is prevented and an aperture ratio is improved without using a black mask and without increasing the number of masks. In the electronic device, a first electrode (113) is disposed on another layer different from the layer on which a gate wiring (145) is disposed as a gate electrode, and a semiconductor layer of a pixel switching TFT is superimposed on the gate wiring (145) so as to be shielded from a light. Thus, the deterioration of the TFT is suppressed, and a high aperture ratio is realized.Type: GrantFiled: September 12, 2011Date of Patent: September 9, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Kazutaka Inukai
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Patent number: 8829667Abstract: An electronic apparatus includes a main board, a semiconductor package, an upper conductive EMI shield member, and a lower conductive EMI shield member. The main board includes a first ground pad. The semiconductor package is spaced apart from and electrically connected to the main board. The upper conductive EMI shield member covers a top surface and a sidewall of the semiconductor package. The lower conductive EMI shield member surrounds a space between the main board and the semiconductor package, and is electrically connected to the upper conductive EMI shield member and the first ground pad.Type: GrantFiled: August 16, 2013Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Woo Park, Wang-Ju Lee, In-Sang Song
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Patent number: 8816485Abstract: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.Type: GrantFiled: January 18, 2012Date of Patent: August 26, 2014Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Chris Apanius, Robert A. Shick, Hendra Ng, Andrew Bell, Wei Zhang, Phil Neal
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Patent number: 8816493Abstract: A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 ?/?.Type: GrantFiled: June 19, 2013Date of Patent: August 26, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoichi Nogami, Yoshitsugu Yamamoto, Akira Inoue, Yoshinori Yokoyama, Jun Fujita, Kazuyo Endo, Shinnosuke Soda, Kazuyasu Nishikawa
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Patent number: 8796697Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.Type: GrantFiled: March 14, 2013Date of Patent: August 5, 2014Assignee: Mitsubishi Electric CorporationInventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
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Patent number: 8786107Abstract: A semiconductor module includes a semiconductor having a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on an opposite surface of the semiconductor substrate. A first conductive member is in contact with the first electrode. A second conductive member is in contact with the second electrode. A third conductive member is in contact with the second conductive member and extends along the first conductive member. An insulating member provides insulation between the first conductive member and the third conductive member. The third conductive member is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. The semiconductor device is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member.Type: GrantFiled: September 13, 2012Date of Patent: July 22, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventor: Norimune Orimoto
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Patent number: 8765530Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: July 1, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8754519Abstract: According to one embodiment, a package for housing semiconductor element includes: a base plate including a top surface and a recessed portion formed as a downwardly-recessed portion of the top surface; a peripheral wall provided on the top surface of the base plate; a lid provided on an upper side of the peripheral wall and forming a semiconductor element housing space in cooperation with the base plate and the peripheral wall; and a feed-through terminal including a bottom end and fixed to the recessed portion so that the bottom end is located at a lower position than the top surface of the base plate except the recessed portion.Type: GrantFiled: December 27, 2010Date of Patent: June 17, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Tsuyoshi Hasegawa
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Patent number: 8742569Abstract: In some examples, a semiconductor package can be configured to electrically couple to a printed circuit board. The semiconductor package can include: (a) a lid having one or more first electrically conductive leads; (b) a base coupled to the lid and having one or more second electrically conductive leads electrically coupled to the one or more first electrically conductive leads; (c) one or more first semiconductor devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads; and (d) one or more first micro-electrical-mechanical system devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads. At least one of the lid or the base can have at least one port hole. The one or more first electrically conductive leads can be configured to couple to the printed circuit board. Other embodiments are disclosed.Type: GrantFiled: April 30, 2010Date of Patent: June 3, 2014Assignee: Ubotic Intellectual Property Co. Ltd.Inventors: Chi Kwong Lo, Lik Hang Wan, Ming Wa Tam
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Patent number: 8729695Abstract: In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.Type: GrantFiled: September 25, 2009Date of Patent: May 20, 2014Assignees: Agency for Science, Technology and Research, Seiko Instruments, Inc.Inventors: Chirayarikathu Veedu Sankarapillai Premachandran, Rakesh Kumar, Nagarajan Ranganathan, Won Kyoung Choi, Ebin Liao, Yasuyuki Mitsuoka, Hiroshi Takahashi, Ryuta Mitsusue
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Patent number: 8704361Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.Type: GrantFiled: January 31, 2012Date of Patent: April 22, 2014Assignee: Asahi Glass Company, LimitedInventor: Hiroki Takahashi
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Patent number: 8704360Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: December 31, 2012Date of Patent: April 22, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8697490Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.Type: GrantFiled: July 1, 2011Date of Patent: April 15, 2014Assignee: STATS ChipPAC, Ltd.Inventor: Rajendra D. Pendse
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Patent number: 8698287Abstract: A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member.Type: GrantFiled: June 9, 2010Date of Patent: April 15, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Shin Soyano
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Patent number: 8674498Abstract: An MEMS package is proposed, wherein a chip having MEMS structures on its top side is connected to a rigid covering plate and a frame structure, which comprises a polymer, to form a sandwich structure in such a way that a closed cavity which receives the MEMS structures is formed. Solderable or bondable electrical contact are arranged on the rear side of the chip or on the outer side of the covering plate which faces away from the chip, and are electrically conductively connected to at least one connection pad by means of an electrical connection structure.Type: GrantFiled: December 4, 2008Date of Patent: March 18, 2014Assignee: Epcos AGInventors: Gregor Feiertag, Hans Krüger, Alexander Schmajew
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Patent number: 8652883Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: February 18, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8633064Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's sprinted circuit board.Type: GrantFiled: March 15, 2013Date of Patent: January 21, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8629005Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: January 14, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8629552Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: December 31, 2012Date of Patent: January 14, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Methods of manufacture of bottom port multi-part surface mount silicon condenser microphone packages
Patent number: 8623710Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: January 7, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini -
Patent number: 8624386Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: December 31, 2012Date of Patent: January 7, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8624387Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: December 31, 2012Date of Patent: January 7, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8623709Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: January 7, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8624384Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: November 2, 2012Date of Patent: January 7, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8624385Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: December 31, 2012Date of Patent: January 7, 2014Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8617934Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.Type: GrantFiled: March 15, 2013Date of Patent: December 31, 2013Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 8598701Abstract: A semiconductor device has high reliability which suppresses a temperature rise of a set housing within an allowable range, and avoids an effect on a wiring on a package substrate due to thermal expansion of a heat dissipating member. The semiconductor device includes a semiconductor element, a package substrate, and a heat dissipating member. A first main surface of the semiconductor element faces an element-mounting surface of the package substrate and is connected to the package substrate. A main surface part of the heat dissipating member contacts a second main surface which is a back surface of first main surface of semiconductor element. A bonding part around a periphery of the main surface part is bonded to a bonding area of the element-mounting surface of the package substrate. A wiring on the package substrate is arranged at a portion other than the element-mounting surface, in a region of the bonding area.Type: GrantFiled: March 15, 2012Date of Patent: December 3, 2013Assignee: Panasonic CorporationInventors: Keisuke Sato, Kouji Takemura
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Patent number: 8592959Abstract: A semiconductor device includes a semiconductor element, a wiring board including a conductor portion formed on a first surface thereof on which the semiconductor element is mounted, the conductor portion being electrically connected to the semiconductor element, and a concave cap provided to seal the first surface of the wiring board, the concave cap being mounted through an adhesive on the first surface of the wiring board In the semiconductor device, a sidewall portion of the concave cap includes an inside surface facing toward the conductor portion of the wiring board, an outside surface positioned on an opposite side to the inside surface, and a bottom surface adhered onto the first surface of the wiring board. The sidewall portion of the concave cap is provided so that a thickness thereof becomes thinner at a portion extending from the outside surface to the bottom surface.Type: GrantFiled: November 24, 2010Date of Patent: November 26, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Tomoharu Fujii
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Patent number: 8581239Abstract: A semiconductor structure comprises a carrier, a plurality of under bump metallurgy layers, a plurality of copper containing bumps and an organic barrier layer, wherein the carrier comprises a protective layer and a plurality of conductive pads, mentioned protective layer comprises a plurality of openings, the conductive pads exposed by the openings, mentioned under bump metallurgy layers being formed on the conductive pads, mentioned copper containing bumps being formed on the under bump metallurgy layers, each of the copper containing bumps comprises a top surface and a ring surface in connection with the top surface, mentioned organic barrier layer having a first coverage portion, and mentioned first coverage portion covers the top surface and the ring surface of each of the copper containing bumps.Type: GrantFiled: January 19, 2012Date of Patent: November 12, 2013Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Shu-Chen Lin, Yung-Wei Hsieh, Jun-Yu Yeh
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Patent number: 8575748Abstract: A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.Type: GrantFiled: December 13, 2011Date of Patent: November 5, 2013Assignee: Sandia CorporationInventor: Anthony J. Farino
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Patent number: 8564123Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.Type: GrantFiled: January 21, 2011Date of Patent: October 22, 2013Inventors: Ching-Yu Ni, Chang-Sheng Hsu
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Patent number: 8558371Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.Type: GrantFiled: January 21, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: JiSun Hong, Taeje Cho, Un-Byoung Kang, Hyuekjae Lee, Youngbok Kim, Hyung-sun Jang
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Patent number: 8546936Abstract: A substrate surface of a semiconductor package, comprising: a plurality of product forming areas to provide mounting spaces of semiconductor chips. The substrate surface also comprises a plurality of staggered offset mesh block areas surrounding the plurality of product forming areas. The plurality of staggered offset mesh block areas minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.Type: GrantFiled: June 18, 2010Date of Patent: October 1, 2013Assignee: Spansion LLCInventors: Pakhorudin Hussin, Murugasan Manikam Achari, Tee-Eu Jin, Kwet Nam Wong
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Patent number: 8541891Abstract: A semiconductor device having a first rectangular chip on which wires, electrode pads and chip mounting area are provided, a first dame formed on the first rectangular chip around the electrode pads and the chip mounting area so as to cover the wires and an under fill formed by filling liquid resin between a second rectangular chip mounted on the chip mounting area in a flip-chip manner and the first rectangular chip.Type: GrantFiled: March 11, 2008Date of Patent: September 24, 2013Assignee: Lapis Semiconductor Co., Ltd.Inventor: Yoshihiro Saeki
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Patent number: 8502372Abstract: An electronic device includes first and second electronic device dice. The first electronic device die is embedded within a resin layer. A dielectric layer is located over the device die and the resin layer. First interconnects within the dielectric layer connect a first subset of electrical contacts on the first electronic device to corresponding terminals at a surface of the dielectric that are located over the first electronic device. Second interconnects within the dielectric layer connect a second subset of electrical contacts on the first electronic device to corresponding bump pads at a surface of the dielectric that are located over the resin layer.Type: GrantFiled: August 25, 2011Date of Patent: August 6, 2013Assignee: LSI CorporationInventor: John Osenbach
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Patent number: 8481859Abstract: Some embodiments teach a method of preparing a flexible substrate assembly. The method can include: (a) providing a carrier substrate; (b) providing a cross-linking adhesive; (c) providing a plastic substrate; and (d) coupling the carrier substrate to the plastic substrate using the cross-linking adhesive. Other embodiments are disclosed in this application.Type: GrantFiled: May 27, 2011Date of Patent: July 9, 2013Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on behalf of Arizona State UniversityInventors: Jesmin Haq, Scott Ageno, Douglas E. Loy, Shawn O'Rourke, Robert Naujokaitis
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Patent number: 8476755Abstract: A high frequency ceramic package includes: a first conductive pattern placed on the top surface of a ceramic RF substrate; a second conductive pattern placed on the bottom surface of the ceramic RF substrate; a through hole for passing through the top surface and bottom surface of the ceramic RF substrate; a through hole metal layer which is filled up in the through hole and which connects the first conductive pattern and the second conductive pattern; a ceramic seal ring placed on the ceramic RF substrate; an insulating adhesive bond placed on the ceramic seal ring; and a ceramic cap placed on the insulating adhesive bond, wherein the second conductive pattern is used as an external terminal, and between the ceramic cap and the top surfaces of the ceramic seal ring is sealed with the insulating adhesive bond and it is simple for structure and excellent in high frequency characteristics.Type: GrantFiled: April 2, 2009Date of Patent: July 2, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Tomohiro Senju
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Patent number: 8471382Abstract: A package includes: a metal wall disposed on a conductive base plate; a through-hole disposed in input/output portions of the metal wall; a lower layer feed through disposed on the conductive base plate; a wiring pattern disposed on the lower layer feed through; an upper layer feed through disposed on a part of the lower layer feed through and a part of the wiring pattern; and a terminal disposed on the wiring pattern, wherein a width of a part of the lower layer feed through and a width of the upper layer feed through are wider than a width of the through-hole, the lower layer feed through is adhered to a side surface of the metal wall, the upper layer feed through is adhered to the side surface of metal wall, and an air layer is formed between the wiring pattern and an internal wall of the through-hole.Type: GrantFiled: March 12, 2012Date of Patent: June 25, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Kazutaka Takagi
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Patent number: 8446004Abstract: A light emitting die package and a method of manufacturing the die package are disclosed. The die package includes a leadframe, at least one light emitting device (LED), a molded body, and a lens. The leadframe includes a plurality of leads and has a top side and a bottom side. A portion of the leadframe defines a mounting pad. The LED device is mounted on the mounting pad. The molded body is integrated with portions of the leadframe and defines an opening on the top side of the leadframe, the opening surrounding the mounting pad. The molded body further includes latches on the bottom side of the leadframe. The lens is coupled to the molded body. A composite lens is used as both reflector and imaging tool to collect and direct light emitted by LED(s) for desired spectral and luminous performance.Type: GrantFiled: June 26, 2008Date of Patent: May 21, 2013Assignee: Cree, Inc.Inventors: Ban P. Loh, Gerald H. Negley
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Patent number: 8421219Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.Type: GrantFiled: June 28, 2011Date of Patent: April 16, 2013Assignee: Fujitsu LimitedInventors: Tsuyoshi So, Hideo Kubo, Seiji Ueno, Osamu Igawa
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Patent number: 8421838Abstract: An optical device including an optical element; a package member in which the optical element is held on a bottom surface of the package member in an area surrounded by walls; and a plate member that seals the area surrounded by the walls and the bottom surface in an airtight manner, the plate member being translucent and joined to the package member with a resin material. The walls have a structure including steps, the plate member is joined onto one of the steps of the walls, and at least a part of the walls facing side surfaces of the plate member includes a positioning part for positioning the plate member and a retaining part for retaining the resin material, in a direction perpendicular to the bottom surface.Type: GrantFiled: November 11, 2010Date of Patent: April 16, 2013Assignee: Ricoh Company, Ltd.Inventors: Takayuki Yamaguchi, Satoru Sugawara, Kazuhiko Adachi, Masaki Hiroi
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Patent number: 8384212Abstract: To provide a semiconductor equipment having high heat-transfer effect and breakdown voltage, and a method of manufacturing the same. The semiconductor equipment includes: a sealed container; a stem connected to the sealed container via a stem peripheral portion; and a semiconductor chip mounted on a top surface of the stem, inside the sealed container. The semiconductor chip is electrically connected to a lead provided to the stem, the stem peripheral portion, which is of a material that is different from the material of stem and the same as the material of the sealed container, is bonded along a periphery of the stem, and the sealed container is filled with a working fluid including at least one of ethanol, a perfluorocarbon, and a fluoroether.Type: GrantFiled: June 30, 2011Date of Patent: February 26, 2013Assignee: Panasonic CorporationInventors: Nobuyuki Otsuka, Manabu Yanagihara, Shuichi Nagai, Daisuke Ueda
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Patent number: 8351222Abstract: A package enclosing at least one microelectronic element (60) such as a sensor die and having electrically conductive connection pads (31) for electric connection of the package to another device is manufactured by providing a sacrificial carrier; applying an electrically conductive pattern (30) to one side of the carrier; bending the carrier in order to create a shape of the carrier in which the carrier has an elevated portion and recessed portions; forming a body member (45) on the carrier at the side where the electrically conductive pattern (30) is present; removing the sacrificial carrier; and placing a microelectronic element (60) in a recess (47) which has been created in the body member (45) at the position where the elevated portion of the carrier has been, and connecting the microelectronic element (60) to the electrically conductive pattern (30). Furthermore, a hole (41) is arranged in the package for providing access to a sensitive surface of the microelectronic element (60).Type: GrantFiled: August 2, 2011Date of Patent: January 8, 2013Assignee: Koninklijke Philips Electronics N.V.Inventors: Johannes Wilhelmus Weekamp, Antonius Constan Johanna Cornelis Van Den Ackerveken, Will J. H. Ansems
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Patent number: 8338851Abstract: A multi-layer LED array engine is provided. The multi-layer LED array engine includes a base plate frame, a molded platform, two lead frames, a lighting element, a dome, a protection layer, and a phosphorous layer. The molded platform is disposed on and secured to the base plate frame. The two lead frames are combined with two lead frame grooves of the base plate frame. The lighting element is disposed on a lighting area of the base plate frame. The protection layer is provided on the lighting element, and the phosphorous layer is provided on the protection layer. The dome is secured to the molded platform for covering the molded platform and the lighting element.Type: GrantFiled: March 17, 2010Date of Patent: December 25, 2012Assignee: Gem Weltronics TWN CorporationInventors: Jon-Fwu Hwu, Yung-Fu Wu
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Patent number: 8314486Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed.Type: GrantFiled: February 23, 2010Date of Patent: November 20, 2012Assignee: STATS ChipPAC Ltd.Inventors: HeeJo Chi, NamJu Cho, HyungSang Park
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Patent number: 8309388Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.Type: GrantFiled: December 17, 2008Date of Patent: November 13, 2012Assignee: Texas Instruments IncorporatedInventors: Kurt P. Wachtler, Wei-Yan Shih, Gregory E. Howard
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Patent number: 8304845Abstract: An integrated component having a substrate, the substrate having a cavity which surrounds a mechanical structure. The cavity is filled by a fluid of a specific composition under a specific pressure, and the mechanical properties of the mechanical structure are influenced by the fluid.Type: GrantFiled: November 24, 2006Date of Patent: November 6, 2012Assignee: Robert Bosch GmbHInventors: Udo Bischof, Holger Hoefer, Volker Schmitz, Axel Grosse, Lutz Mueller, Ralf Hausner
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Patent number: 8268670Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.Type: GrantFiled: September 22, 2011Date of Patent: September 18, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
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Patent number: 8264059Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.Type: GrantFiled: February 2, 2011Date of Patent: September 11, 2012Assignee: STATS ChipPAC, Ltd.Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
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Patent number: 8247900Abstract: A flip chip semiconductor package is provided. In one embodiment, the flip chip semiconductor package comprises a first substrate having a first surface and a second surface opposite the first surface, a semiconductor chip mounted on the first surface of the first substrate by solder bumps, a thermally-conductive stiffener mounted above the first surface of the first substrate and around the chip to define a cavity region therebetween, one or more molding compound material disposed in the cavity region, and a second substrate mounted to the second surface of the first substrate by solder balls.Type: GrantFiled: December 29, 2009Date of Patent: August 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Tsorng-Dih Yuan