Abstract: The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.

Abstract: A semiconductor device packaging structure is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Abstract: A package for use in encapsulating an electronic device is disclosed. The package includes a dielectric frame having first and second sides with a pair of apertures extending through the dielectric frame. These apertures are separated by a raised shelf span extending inwardly from an internal perimeter of the dielectric frame. The raised shelf span defines a first thickness of the dielectric frame and a raised sidewall extending outwardly from the second side along an external perimeter of said dielectric frame defines a second thickness of said frame, with the second thickness being greater than the first thickness. Also provided is a metallic component having a flange and a pedestal that extends perpendicularly from the flange. The flange is bonded to the first side of the dielectric frame and extends across one of the pair of apertures with the pedestal extending into that aperture. A gap between the pedestal and the dielectric frame having a width of at least 0.015 inch.

Abstract: A microstructured component with microsensors or other active microcomponent is provided. The microstructured component includes a substrate and at least one housing arranged on the substrate with one or more active microstructures situated on it.

Abstract: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: An immersion cooling apparatus includes a multi-terminal thermally conductive module that supports and encloses a power semiconductor device and a housing defining a flow-through chamber in which the thermally conductive module is mounted and through which liquid coolant is circulated. The thermally conductive module has first and second oppositely disposed connector headers housing terminal pins or blades electrically coupled to the semiconductor device, and the connector headers protrude through openings in oppositely disposed sidewalls of the housing so that the portion of the thermally conductive module between the connector headers is suspended in the chamber and immersed in the circulating coolant. The thermally conductive module is sealed against the housing sidewalls around the openings, and one of the sidewalls is removable to facilitate installation of the thermally conductive module in the housing or its subsequent removal.

Abstract: A semiconductor device includes a semiconductor element mounted on a substrate; at least one electronic part arranged around the semiconductor element; and a heat radiation member bonded to a backside of the semiconductor element by a bonding material. The heat radiation member has an isolation part extending between an outer circumference of the semiconductor element and the electronic part.

Abstract: A package for use in encapsulating an electronic device is disclosed. In some embodiments, the package includes the following: a dielectric frame having first and second sides, an aperture, a raised shelf portion defined along an internal perimeter of the dielectric frame and extending outwardly from the second side, the raised shelf portion defining a first thickness of the dielectric frame, and a raised sidewall extending outwardly from the second side along an external perimeter of the dielectric frame, the raised sidewall defining a second thickness of the frame, the second thickness being greater than the first thickness; a metallic component bonded to the dielectric frame and extending across the aperture; and a seam weldable, low-profile metallic seal ring bonded to the raised sidewall of the dielectric frame.

Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.

Abstract: A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die.

Abstract: A semiconductor assembly includes a substrate with at least a CMOS region and a seal ring region and an optional micro electro mechanical system (MEMS) region, a shallow trench isolation disposed in the CMOS region of the substrate, an optional micro electro mechanical system device disposed in the micro electro mechanical system region, a plurality of recesses disposed in the seal ring region of the substrate, a first metal-oxide semiconductor disposed in the CMOS region, a dielectric layer disposed on the substrate and on the recesses, and a seal ring disposed in the seal ring region and embedded in the dielectric layer to cover and fill up the recesses, wherein the seal ring region surrounds at least the CMOS region and the optional MEMS region.

Abstract: One embodiment of a microelectronic component system includes a base adapted for supporting a microelectronic component, a membrane sealed to the base, and a glass lid built-up on the membrane and hermetically sealing the membrane.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.

Abstract: A semiconductor device has a substrate. A die is attached to a first surface of the substrate. A heat sink is provided having an approximately planer member and support members extending from the planer member. The support members are attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die. An encapsulant is provided for encapsulating the device, wherein an exterior surface of the planer member is exposed. A non-tapered opening is formed in the planer member. The encapsulant is injected through the opening to encapsulate the cavity and the encapsulant will partially fill the non-tapered opening.

Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.

Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.

Abstract: An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads.

Abstract: An embodiment of the present invention provides a method of manufacturing hermetic packaging for devices on a substrate wafer, comprising forming a plurality of adhesive rings on a cap wafer or the substrate wafer, bonding the cap wafer to the substrate wafer with an adhesive layer, forming trenches in the cap wafer and the adhesive rings along outer rim of the adhesive rings, and covering sidewall of the trenches by at least one deposited film to provide a diffusion barrier to moisture or gas.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: A packaging structure for hermetically sealing a functional device by solder connection at a wafer level in which a first Si substrate having a concave portion metallized on its internal surface and a second Si substrate metallized at a position opposed to said concave portion are used, the metallization applied to the internal surface of the concave portion of the first Si substrate and the metallization applied to the second Si substrate at the position opposed to the concave portion are connected by molten solder to hermetically seal the functional device between the first Si substrate and the second Si substrate, whereby the wettability of the solder for the two Si substrates is improved, the bondability between the Si substrates is enhanced, and the yield at which the package is manufactured is improved.

Abstract: A low-temperature inorganic dielectric ALD film (e.g., Al2O3 and TiO2) is deposited on a packaged or unpackaged chip device so as to coat the device including any exposed electrical contacts. Such a low-temperature ALD film generally can be deposited without damaging the packaged chip device. The ALD film is typically deposited at a sufficient thickness to provide desired qualities (e.g., hermeticity for the entire packaged chip device, passivation for the electrical contacts, biocompatibility, etc.) but still allow for electrical connections to be made to the electrical contacts (e.g., by soldering or otherwise) directly through the ALD film without having to expose the electrical contacts.

Abstract: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.

Abstract: An LED package and a fabrication method thereof are provided. The LED package includes an upper metal plate having an LED-receiving hole therein; a lower metal plate disposed under the upper metal plate; and an insulator which the upper metal plate and the lower metal plate from each other. A portion of the lower metal plate is exposed via the LED-receiving hole and an LED is mounted on the exposed portion of the lower metal plate and is electrically connected to both of the upper and lower metal plates. A protective cover encloses and protects exposed surfaces of the upper and lower metal plates.

Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.

Abstract: The present invention is directed to low-cost, low-processing temperature, and simple reinforcement, repair, and corrosion protection for hermetically sealed modules and hermetic connectors. A thin layer of glass is applied over the module's seal or the connector' glass frit. The layer of glass comprises an alkali silicate glass. The layer of glass is produced from a material which is a low viscosity liquid at room temperature prior to curing and is cured at low temperatures (typically no more than about 160 degrees Celsius). Subsequent to curing, the layer of glass is intimately bonded to the seal, watertight, and is stable from about negative two-hundred forty-three degrees Celsius to at least about seven-hundred twenty-seven degrees Celsius. The glass layer provides corrosion protection, seals any existing leaks, and possesses good flexibility and adhesion. The resulting bond is hermetic with good aqueous durability and strength similar to that of monolithic structures.

Abstract: Embodiments of the present invention describe a bare die package and its methods of fabrication. The bare die package comprises a die electrically coupled to a package substrate, and a displacement constraint. In an embodiment of the present invention, the displacement constraint is a plurality of members fixedly attached onto the package substrate and surrounds the die. When the bare die package is secured between a socket and a heat sink, the plurality of members provide structural support to the package substrate and prevent excessive substrate warpage.

Abstract: A kind of microphone package structure includes at least of a substrate, a sound processing unit, an upper cap and other devices. There would be at least one trench set on the substrate, and a separation gap between the trench and the bonding pad of the substrate is maintained. After connective paste is smeared on the surface of the substrate, the trench would be assembled with other devices. This kind of package structure could prevent a short circuit being caused by the overflowing of the connective paste.

Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.

Abstract: A method of protecting a micro-mechanical sensor structure embedded in a micro-mechanical sensor chip, in which the micro-mechanical sensor structure is fabricated with a protective membrane, the micro-mechanical sensor chip is arranged so that a surface of the protective membrane faces toward a second chip, and the micro-mechanical sensor chip is secured to the second chip.

Abstract: A cap 25 having a piece of glass 26 formed at a laser irradiating position and covering a laser irradiating direction and an upper face of a package 24, is mounted onto the package 24 having lateral faces of a frame body 30 formed in three directions other than the laser irradiating direction, so as to reduce the distance between a semiconductor element 22 and the piece of glass 26 and to reduce a radius 32 of the piece of glass 26. The profile of the semiconductor device can be therefore lowered while maintaining the characteristics of a semiconductor laser. In addition, by mounting the semiconductor device, the profile of an optical pickup device can also be lowered.

Abstract: A method for forming a seal ring is disclosed. First, a substrate including a MEMS region, a logic region and a seal ring region is provided. Second, a trench is formed in the MEMS region and multiple recesses are formed in the seal ring region. An oxide fills the trench and the recesses. Later, a MOS is form in the logic region and a dielectric layer is formed on the substrate. Then, an etching procedure is carried out to partially remove the dielectric layer and simultaneously remove the oxide in the multiple recesses completely to form a seal ring space. Afterwards, a metal fills the seal ring space to from the seal ring.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: An integrated circuit (IC) device package is presented. A frame body has opposing first and second surfaces and a central opening that is open at the first and second surfaces. The second frame body surface is mounted to a first stiffener surface. An IC die is mounted to the first stiffener surface within the central opening through the frame body. A planar lid has opposing first and second surfaces. The second lid surface is coupled to the first frame body surface. A first substrate surface is coupled to a second stiffener surface. An array of electrically conductive terminals is coupled to a second substrate surface. The stiffener, frame body, and lid form an enclosure structure substantially enclosing the IC die. The die enclosure spreads heat from the IC die, and shields EMI emanating from and radiating toward the IC die. At least one tab protrudes from the second surface of the frame body. At least one receptacle formed in the first surface of the stiffener corresponding to the at least one tab.

Abstract: A semiconductor package has a substrate having a first heat transfer path for transferring heat from an optical functional element to a back surface of the substrate, a first heat dissipation unit dissipating the transferred heat therefrom, a second heat transfer path for transferring heat generated in an internal cavity and heat from a window lid itself to a back surface and/or a side surface of the substrate, a second heat dissipation unit dissipating the transferred heat therefrom. The heat transfer paths extend through the substrate and have thermal vias.

Abstract: A method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package is disclosed. In one embodiment, a method includes forming a dam structure on an outer area of a substrate surface of a semiconductor package and blocking a flow of a mold material from a mold cavity of the semiconductor package to the outer area of the substrate surface using the dam structure. In another embodiment, a substrate surface of a semiconductor package includes product forming areas to provide mounting spaces of semiconductor chips and staggered offset mesh block areas surrounding the product forming areas to act as dam structures to minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.

Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.

Abstract: One embodiment of an electronic component packaging system includes a base adapted for supporting an electronic component, a lid sealed to the base, the lid including a fillport, and the fillport hermetically sealed by light irradiation.

Abstract: An electronic module includes a printed circuit board with a heat producing electrical component assembled in an insulating housing. The component is adjacent a thermally conducting heat sink with a thermally conductive material disposed therebetween. Integral with the heat sink is a thermally conductive runner, partially encased in the housing wall, connecting the heat sink to a thermally conductive port. The port is coupled to a base structure when the housing is attached to the base, forming a heat conduction path from the component to the base. This conductive path may also provide an electrical ground path from the printed circuit board to the base.

Abstract: A method of packaging a semiconductor component with a printed wiring board is disclosed. The method includes determining a first distance, applying a thin film onto a surface of the semiconductor component such that the thin film is spaced apart from a support of the semiconductor, applying a solder pad onto the printed wiring board, placing the semiconductor component with the thin film onto the printed wiring board, and positioning the thin film adjacent the solder pad.

Abstract: A contact device for use with a power semiconductor component in a power semiconductor module or a disc-type thyristor, the module or thyristor having a molded body with a first recess disposed above the component. The contact device makes electrical contact with the auxiliary connection of the component, and is disposed within a second recess in the module or thyristor. The contact device includes a spring having a pin-like extension at a first end thereof that faces the component and a metal molded body that is arranged at the opposite end thereof and has a first connecting device formed as a flat section of the metal molded body. The flat section is arranged generally parallel to the component, and has a second connecting device for connection to a connecting cable. The connecting device may also have a multipart insulating housing for holding the contact spring and the metal molded body.

Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.

Abstract: A MEMS package and methods for its embodiment are described. The MEMS package has at least one MEMS device mounted on a flexible and foldable substrate. A metal cap structure surrounds the at least one MEMS device wherein an edge surface of the metal cap structure is attached to the flexible substrate and wherein a portion of the flexible substrate is folded under itself thereby forming the MEMS package. A meshed metal environmental hole underlying the at least one MEMS device provides enhanced EMI immunity.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: A first container member (9, 109, 212) mounting an electronic device (71, 171, 261) thereon and a second container member (2, 102, 202) are bonded with an adhesive (3, 103) or a metal layer (103, 251). Thus an inner space (90, 190, 211) is formed and the electronic device can be closed in the inner space at a low temperature. In the case the adhesive is used, an exposed surface of the adhesive is coated with a metal film (4) to improve the closeness of the inner space. Further, an electronic device (261, 272) may be mounted on the second container member so as to increase the electronic device arrangement density in a packaged electronic device.

Abstract: A dynamic quantity sensor includes a sensor chip having a movable portion at one surface side thereof and a silicon layer at another surface side thereof. The movable portion is displaced under application of a dynamic quantity. The silicon layer is separated from the movable portion through an insulator. The dynamic quantity sensor also includes a circuit chip for transmitting/receiving electrical signals to/from the sensor chip. The circuit chip is disposed to confront the one surface of the sensor chip through a gap portion and cover the movable portion. The sensor chip and the circuit chip are bonded to each other around the gap portion so that a bonding portion is formed to substantially surround the gap portion and thereby seal the gap portion.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.