Isolation Of Cooling Means (e.g., Heat Sink) By An Electrically Insulating Element (e.g., Spacer) Patents (Class 257/717)
  • Patent number: 10400988
    Abstract: A light emitting module may include a board, at least one light source unit provided on the board, an optical member provided on the at least one light source unit, and a reflection unit provided between the board and the optical member in an inclined state beside at least one light source unit. The reflection unit may be provided closer to the optical member than to the board and may include a pattern having lower reflectance than other constructions of the light emitting module.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: September 3, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Lee Im Kang
  • Patent number: 10269592
    Abstract: Matching of coefficient of thermal expansion for heat spreaders and carrier die can facilitate optoelectronic die alignment. In one example, an apparatus comprises a carrier die comprising a first coefficient of thermal expansion, two or more optoelectronic die disposed on the carrier die, and a spreader. The spreader can comprise a second material coefficient of thermal expansion matched to the first coefficient of thermal expansion. Additionally, a thermal interface material is disposed between the spreader and the one or more optoelectronic die.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fuad Elias Doany, Mark Schultz
  • Patent number: 10256298
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a semiconductor layer formed on the substrate. The semiconductor structure includes an isolation structure through the semiconductor layer, and the isolation structure has an opening with a first width, and the isolation structure has a vacuum gap. The semiconductor structure also includes a contact plug structure through the semiconductor layer, and the contact plug structure has an opening with a second width, and the second width is greater than the first width.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: April 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Chun-Ting Yang, Ho-Chien Chen
  • Patent number: 10229870
    Abstract: An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein the second thickness is larger than the first thickness.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: March 12, 2019
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 10050010
    Abstract: A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Campbell, Sarah K. Czaplewski, Elin Labreck, Jennifer I. Porto
  • Patent number: 10032726
    Abstract: Methods for an embedded vibration management system are disclosed and may include fabricating a semiconductor package that supports vibration management by forming an array of vibration absorbing structures, placing the array proximate to a leadframe comprising two-legged supported leads, placing a semiconductor device above the leadframe, and encapsulating the semiconductor device and the leadframe. Each vibration absorbing structure may comprise a mass element formed on a material with lower density than that of the mass element. The array may be placed on a top, a bottom, or both surfaces of the leadframe. Sections of the array may be placed symmetrically with respect to the semiconductor device. The vibration absorbing structures may be cubic in shape and may be enclosed in an encapsulating material. The two-legged supported leads may be formed by bending metal strips with holes. The vibration absorbing structures may be exposed to the exterior of the semiconductor package.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: July 24, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Bora Baloglu, Adrian Arcedera, Marc Alan Mangrum, Russell Shumway
  • Patent number: 10018429
    Abstract: An apparatus body heat dissipation device includes an apparatus case, at least one plate body and at least one drive member. The apparatus case has at least one first opening and at least one second opening and a receiving space. The plate body is disposed in the receiving space. The drive member serves to drive the plate body to move within the receiving space to produce an air convection effect between the interior of the apparatus case and the ambient surrounding air of the apparatus case so that the air convection in the limited space of the apparatus body can be effectively enhanced to greatly enhance the heat dissipation efficiency.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: July 10, 2018
    Assignee: Asia Vital Components Co., Ltd.
    Inventor: Ching-Hang Shen
  • Patent number: 10002822
    Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 19, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: MuSeob Shin, Won-young Kim, Sanghyun Park, Jinchan Ahn
  • Patent number: 9884204
    Abstract: A device that reduces subcutaneous adipose tissue using a matrix of LEDs to heat and destroy fat cells. The surface facing the patient's skin may be a plate of thermally conductive material such as copper or aluminum, with apertures for the LEDs. Fat reduction may be optimized using infrared LEDs with peak spectral power in the range of 920 nm to 950 nm. The device may include multiple light emitting sections connected with flexible couplings so that the device can conform to curved body shapes; treatment surfaces of individual sections may also be curved. Sections may include cooling mechanisms to cool both the LEDs and the plate facing the patient's skin, such as thermoelectric cooling elements and air or water circulation. A user interface may provide monitoring and control of treatment parameters. The device may incorporate ultraviolet LEDs to facilitate removal of an adhesive attaching the device to the patient.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 6, 2018
    Inventors: Casper Dolleris, Jan K. Enemaerke, Edward Victor Ross
  • Patent number: 9882346
    Abstract: The invention describes carrier structure (100, 200) for assembling a semiconductor lighting module, comprising at least two sub carriers (110, 210) and an alignment structure (120, 130, 230, 232) mechanically coupling the sub carriers (110, 210). The alignment structure (120, 130, 230, 232) is adapted such that the mechanical coupling to at least a part of the sub carriers (110, 210) disappears during thermal mating the carrier structure (100, 200) on a carrier (110, 250). The alignment structure (120, 130, 230, 232) is further adapted to compensate a coefficient of thermal expansion of a material of the carrier (110, 250) being higher than a coefficient of thermal expansion of a material of the carrier structure (100, 200). The invention further describes a semiconductor chip comprising such a carrier structure (100, 200) and a semiconductor lighting module comprising the carrier structure (100, 200) or the semiconductor chip.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 30, 2018
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Stephan Gronenborn, Gero Heusler, Ralf Gordon Conrads, Holger Moench
  • Patent number: 9877381
    Abstract: A composite electronic composite includes a plurality of multilayer ceramic capacitors each including a ceramic body in which dielectric layer and internal electrodes are alternately disposed and first and second external electrodes disposed on a lower surface of the ceramic body, a tantalum capacitor including a body part including a sintered tantalum powder material and a tantalum wire of which a portion is embedded in the body part and disposed on the plurality of multilayer ceramic capacitors, and a molding portion enclosing the tantalum capacitor and the plurality of multilayer ceramic capacitors.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Soo Hwan Son
  • Patent number: 9768149
    Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Jaspreet S. Gandhi, James M. Derderian
  • Patent number: 9667165
    Abstract: A power conversion apparatus includes a semiconductor module that includes a main body containing at least one semiconductor element, power terminals projecting from the main body to be connected to a high-voltage DC power supply and high-voltage signal terminals projecting from the main body, and is configured to convert a DC power supplied from the high-voltage DC power supply to an AC power by switching operation of the semiconductor element. The power conversion apparatus further includes a low-voltage component connected to a low-voltage DC power supply and a control circuit board on which a control circuit for controlling the switching operation of the semiconductor element is formed. The control circuit board is connected with low-voltage signal terminals extending from the low-voltage component and the high-voltage signal terminals. The low-voltage and high-voltage signal terminals are solder-connected to the control circuit board.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: May 30, 2017
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Inamura, Hideaki Tachibana
  • Patent number: 9656868
    Abstract: Provided is a boron-nitride powder that is suitable for use in a resin composition for transmitting heat from a heat-producing electronic component such as a power device to a heat-dissipating member. The boron-nitride powder reduces thermal-conductivity anisotropy and thermal contact resistance, resulting in high thermal conductivity, and contains boron-nitride particles each consisting of hexagonal boron-nitride primary particles joined together. The boron-nitride powder, which is an aggregate of said boron-nitride particles, exhibits a mean sphericity of at least 0.70, a mean particle diameter of 20-100 ?m, a porosity of 50-80%, a mean pore diameter of 0.10-2.0 ?m, a maximum pore diameter of at most 10 ?m, and a calcium content of 500-5,000 ppm. Under X-ray powder diffraction, the graphitization index of the boron-nitride powder is preferably between 1.6 and 4.0, inclusive, and the peak intensity ratio (I(002)/I(100)) between the (002) plane and the (100) plane is preferably at most 9.0.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: May 23, 2017
    Assignee: DENKA COMPANY LIMITED
    Inventors: Taiki Nishi, Koki Ikarashi, Toshikatsu Mitsunaga
  • Patent number: 9646915
    Abstract: In a laminating direction of first to fifth ceramic sheets, a first slit and a second slit are positioned closer to a first mounting section and a second mounting section than a first communication hole, a second communication hole, a third communication hole and a fourth communication hole. Moreover, an overlapping section where each first slit and the first communication hole overlap, and an overlapping section where each second slit and the third communication hole overlap, are positioned in the vicinity of an area where the first mounting section and the second mounting section are disposed when viewed from the laminating direction of the first to fifth ceramic sheets.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 9, 2017
    Assignee: Kyocera Corporation
    Inventors: Yoshitaka Iwata, Shogo Mori, Daizo Kamiyama, Kenji Tsubokawa, Shinichi Soga, Hideo Tanimoto
  • Patent number: 9608184
    Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: March 28, 2017
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Naoyuki Urasaki, Kanako Yuasa
  • Patent number: 9545020
    Abstract: A control unit is stored in an airtight housing constituted by a base, an annular peripheral wall member, a cover, and first and second interior packings, second wiring conductors connected to input/output equipment and first wiring conductors connected to a host controller through a control signal connector are brought into press-contact with input/output control terminals of the control unit by first and second pressing elastic mats, the relative positions of associated components are regulated by positioning pins passing through from the cover to the base, and the cover is opened by loosening blockade screws without causing an assembly dimension error or sliding wear of conductive contact portions due to thermal deformation, whereby the control unit is detached.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: January 10, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shozo Kanzaki, Fumiaki Arimai, Hiroyoshi Nishizaki, Masato Nakanishi
  • Patent number: 9516752
    Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Patricia A Brusso, Mitul B Modi, Carolyn R. McCormick, Ruben Cadena, Sankara J Subramanian, Edward L. Martin
  • Patent number: 9508651
    Abstract: A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: November 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Patent number: 9497876
    Abstract: Fastening systems for power modules including molded body (2) with flat surface (2a) bearing on supporting structure, and a plurality of protruding contact pins (3). A pressing element (5) presses a power module (1) on a side opposite the supporting structure. A connecting element (11) fastens the pressing element (5) on the supporting structure and imparts a force pressing towards the supporting structure. Sections (9, 10) formed on the pressing element (5) have outer edge regions (10) acting elastically on edge regions of the power module (1) in the fastened position. These edge regions are loaded with a pressing force towards the supporting structure. Such power modules (1) are useable with such fastening systems, as are the pressing elements (5).
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: November 15, 2016
    Assignee: BRUSA Elektronik AG
    Inventors: Martin Berkmann, Katja Stengert
  • Patent number: 9407251
    Abstract: A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: August 2, 2016
    Assignee: Cree Fayetteville, Inc.
    Inventors: Brandon Passmore, Zach Cole, Bret Whitaker, Adam Barkley, Ty McNutt, Alexander Lostetter
  • Patent number: 9374885
    Abstract: A ceramic elements module including ceramic elements that have a plurality of lower inserting grooves; an electronic component that is mounted on a lower surface of the ceramic elements; and a heat sink that is coupled with a lower part of the ceramic elements mounted with the electronic component and has a first penetrating hole corresponding to the lower inserting groove and a second penetrating hole into which the electronic component is inserted.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: June 21, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Gyu Man Hwang, Dae Hyeong Lee
  • Patent number: 9371449
    Abstract: The invention relates to boron nitride agglomerates, comprising hexagonal boron nitride primary particles, wherein the hexagonal boron nitride primary particles are connected to one another by means of an inorganic binding phase comprising at least one nitride and/or oxynitride. The invention also relates to a method for producing such boron nitride agglomerates, wherein boron nitride starting powder in the form of boron nitride primary particles is mixed with binding-phase raw materials, processed into granules or molded bodies and these are then subjected to a temperature treatment at a temperature of at least 1000° C. in a nitriding atmosphere, and the obtained granules or molded bodies are comminuted and/or fractionated if necessary. The boron nitride agglomerates according to the invention are suitable as a filler for polymers to be used for producing polymer-boron nitride composite materials.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: June 21, 2016
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Martin Engler, Krishna B. Uibel
  • Patent number: 9355968
    Abstract: A surface mount semiconductor package, semiconductor device, and method for fabrication of the surface mount semiconductor package and electrical device are described that include a leadframe assembly, an integrated circuit device disposed on the leadframe assembly, a silicon shield disposed on the integrated circuit device, where the silicon shield is configured to mitigate packaging stress to the integrated circuit device, and a molding layer that encapsulates the integrated circuit device, the silicon shield, and at least a portion of the leadframe assembly.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 31, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ming Cheng, Ken Wang, Tian Tian, Mohammad Ayyash, Tuyen Pham, Brian Rush
  • Patent number: 9287233
    Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho, Yu-Chih Liu, Chun-Cheng Lin, Shih-Yen Lin
  • Patent number: 9287202
    Abstract: A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30). The lead terminals (21) are made of copper or a copper alloy. The die pad (10) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals (21).
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 15, 2016
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Motoharu Haga, Shoji Yasunaga
  • Patent number: 9257365
    Abstract: Cooling assemblies and power electronics modules having multiple-level porosity structures with both a micro- and macro-level porosity are disclosed. In one embodiment, a cooling assembly includes a jet impingement assembly including a fluid inlet channel fluidly coupled an array of orifices provided in a jet plate, and a heat transfer substrate having a surface. The heat transfer substrate is spaced apart from the jet plate. A first array of metal fibers is bonded to the surface of the heat transfer substrate in a first direction, and a second array of metal fibers is bonded to the first array of metal fibers in a second direction. Each metal fiber of the first array of metal fibers and the second array of metal fibers includes a plurality of metal particles defining a micro-porosity. The first array of metal fibers and the second array of metal fibers define a macro-porosity.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: February 9, 2016
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: Shailesh N. Joshi
  • Patent number: 9226400
    Abstract: In a method for manufacturing a multilayer ceramic electronic device, a multilayer ceramic element assembly including laminated unsintered ceramic base material layers, a first conductor pattern, a seat portion disposed in a surface of the multilayer ceramic element assembly and arranged to mount a surface mount electronic device thereon, a second conductor pattern connected to the surface mount electronic device, and a resin introduction portion located outside a vertically projected region of the surface mount electronic device and arranged to introduce a resin to the seat portion is prepared. The multilayer ceramic element assembly is fired and the surface mount electronic device is mounted on the seat portion of the fired multilayer ceramic element assembly with the second conductor pattern therebetween. The resin is filled from the resin introduction portion into the seat portion and between the seat portion and the surface mount electronic device and is cured.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 29, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masato Nomiya, Norio Sakai, Mitsuyoshi Nishide
  • Patent number: 9219020
    Abstract: A cavity is formed in a working surface of a substrate in which a semiconductor element is formed. A glass piece formed from a glass material is bonded to the substrate, and the cavity is filled with the glass material. For example, a pre-patterned glass piece is used which includes a protrusion fitting into the cavity. Cavities with widths of more than 10 micrometers are filled fast and reliably. The cavities may have inclined sidewalls.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski, Gerhard Schmidt
  • Patent number: 9184104
    Abstract: A semiconductor device has a semiconductor die disposed over the substrate. A conductive via is formed partially through the substrate. An encapsulant is deposited over the semiconductor die and substrate. An insulating layer is formed over the semiconductor die and encapsulant. The insulating layer includes an organic or inorganic insulating material. An adhesive layer is deposited over the insulating layer. The adhesive layer contacts only the insulating layer. A carrier is bonded to the adhesive layer. The insulating layer provides a single CTE across the entire bonding interface between the adhesive layer and semiconductor die and encapsulant. The constant CTE of the insulating layer reduces stress across the bonding interface. A portion of the substrate is removed by backgrinding to expose the conductive via. An insulating layer is formed over the substrate around the conductive via. An interconnect structure is formed over the conductive via.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: November 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Lai Yee Chia, Duk Ju Na
  • Patent number: 9101077
    Abstract: An electronic component package includes a support and heat conductor. The heat conductor has a protuberance and the support has a socket arranged to be able to receive the protuberance so that the movement of heat conductor relative to the support during the assembly process is reduced.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 4, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Jean-Michel Riviere, Karine Saxod
  • Patent number: 9097088
    Abstract: Subterranean devices are provided that are configured or designed for high temperature downhole use. The downhole devices comprise an electronic device configured or designed for downhole use in the well and a heat dissipation system. The heat dissipation may include one or more active coolers and a micro-particulate radiation improving coating applied to the active cooler.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: August 4, 2015
    Assignee: Schlumberger Technology Corporation
    Inventors: Jiro Takeda, Lahcen Garando, Jose Gregorio Labanda
  • Patent number: 9054074
    Abstract: A series of hierarchical channels are formed in a first member surface of a first member using a continuous-feed manufacturing process. The channels are configured to control particle stacking. The first member is pressed to a second member with a layer of particle-filled viscous material between the first member surface and a second member surface of the second member. An inventive assembly includes mating surfaces with at least one surface formed with a series of parallel hierarchical channels configured to control stacking of the particles during pressing together of the surfaces. The surface is substantially free of any other hierarchical channels formed thereon.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Ryan J. Linderman, Erich M. Ruetsche
  • Patent number: 9041192
    Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 26, 2015
    Assignee: Broadcom Corporation
    Inventors: Seyed Mahdi Saeidi, Sam Ziqun Zhao
  • Patent number: 9033515
    Abstract: A heat dissipation device of a light engine for a projector has a housing, a fan module, a light engine and a heat sink. The light engine is positioned in the housing and connected to the heat sink. The heat sink is positioned out of the housing. The housing has a fan-enclosed flow channel attached on an outer surface of the housing. The fan module is guided by the fan-enclosed flow channel to the heat sink to enhance heat dissipation efficiency of the light engine for the projector.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 19, 2015
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ming-Chih Sun, Kai Huang
  • Patent number: 9030005
    Abstract: In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yasutaka Sugimoto, Takahiro Takada
  • Patent number: 9018861
    Abstract: A field emission device is configured as a heat engine. Different embodiments of the heat engine may have different configurations that may include a cathode, gate, suppressor, and anode arranged in different ways according to a particular embodiment. Different embodiments of the heat engine may also incorporate different materials in and/or proximate to the cathode, gate, suppressor, and anode.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: April 28, 2015
    Inventors: Roderick A. Hyde, Jordin T. Kare, Nathan P. Myhrvold, Tony S. Pan, Lowell L. Wood, Jr.
  • Patent number: 9018744
    Abstract: A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Khalil Hosseini
  • Patent number: 9013040
    Abstract: A memory device with die stacking is provided. A plurality of substrates layers are stacked together into a stack. Each substrate layer may include a substrate having a plurality of cavities to receive integrated circuit components within the thickness of the substrate. A plurality of conductive spheres are arranged between at least two adjacent substrate layers and are electrically coupled to the integrated circuit components in at least one of the two adjacent substrates. The two adjacent substrate layers of the stack include: (a) a first substrate having a first plurality of cavities to receive integrated circuit components, and (b) a second substrate having a second plurality of cavities to receive integrated circuit components, wherein the first plurality of cavities is offset from a second plurality of cavities.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Sanmina Corporation
    Inventor: Jon Schmidt
  • Patent number: 9006889
    Abstract: Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 14, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventor: Jaydutt J. Joshi
  • Patent number: 9001512
    Abstract: A heat spreader for a resistive element is provided, the heat spreader having a body portion that is arranged over a top surface of the resistive element and electrically insulated from the resistive element. The heat spreader also includes one or more leg portion that extends from the body portion and are associated with the heat sink in a thermally conductive relationship.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 7, 2015
    Assignee: Vishay Dale Electronics, Inc.
    Inventors: Clark L. Smith, Todd L. Wyatt, Thomas L. Veik
  • Patent number: 9000582
    Abstract: A power semiconductor module includes: a circuit body having a power semiconductor element and a conductor member connected to the power semiconductor element; a case in which the circuit body is housed; and a connecting member which connects the circuit body and the case. The case includes: a first heat dissipating member and a second heat dissipating member which are disposed in opposed relation to each other while interposing the circuit body in between; a side wall which joins the first heat dissipating member and the second heat dissipating member; and an intermediate member which is formed on the periphery of the first heat dissipating member and connected to the side wall, the intermediate member including a curvature that is projected toward a housing space of the case.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinji Hiramitsu, Atsushi Koshizaka, Masato Higuma, Hiroshi Tokuda, Keiji Kawahara
  • Patent number: 8995129
    Abstract: A back metal layer (16, 31) has a plurality of stress relaxation spaces (17). Each stress relaxation space (17) is formed to open at least at one of the front surface and the back surface of the back metal layer (16, 31). A region in the back metal layer (16, 31) that is directly below a semiconductor device (12) is defined as a directly-below region (A1), and a region outside the directly-below region (A1) that corresponds to and has the same dimensions as the directly-below region (A1) is defined as a comparison region (A21). The volume of the stress relaxation spaces (17) in the range of the directly-below region (A1) is less than the volume of the stress relaxation spaces (17) formed in the range of the comparison region (A21).
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 31, 2015
    Assignees: Kabushiki Kaisha Toyota Jidoshokki, Showa Denko K. K.
    Inventors: Yoshitaka Iwata, Shogo Mori, Tomoya Hirano, Kazuhiko Minami
  • Patent number: 8994168
    Abstract: A semiconductor package includes a wiring board; a semiconductor chip mounted on the wiring board; and a radiation plate mounted on the semiconductor chip, including an insulating member including a resin that is the same as a resin included in the wiring board, as a main constituent, a first metal foil formed on a first surface of the insulating member, a second metal foil formed on a second surface of the insulating member, the second surface being an opposite to the first surface, the radiation plate being provided with a through hole that penetrates the first metal foil, the insulating member and the second metal foil, and a metal layer formed to cover the inner surface of the through hole to thermally connect the first metal foil and the second metal foil by penetrating the insulating member in a thickness direction.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yukio Sato
  • Patent number: 8987895
    Abstract: A clad material 1A for insulating substrates is provided with a Ni layer 4 made of Ni or a Ni alloy, a Ti layer 6 made of Ti or a Ti alloy and arranged on one side of the Ni layer, and a first Al layer 7 made of Al or an Al alloy and arranged on one side of the Ti layer 6 that is opposite to a side of the Ti layer 6 on which the Ni layer 4 is arranged. The Ni layer 4 and the Ti layer 6 are joined by clad rolling. A Ni—Ti series superelastic alloy layer 5 formed by alloying at least Ni of constituent elements of the Ni layer 4 and at least Ti of constituent elements of the Ti layer 6 is interposed between the Ni layer 4 and the Ti layer 6. The Ti layer 6 and the first Al layer 7 are joined by clad rolling in an adjoining manner.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: March 24, 2015
    Assignee: Showa Denko K.K.
    Inventors: Atsushi Otaki, Shigeru Oyama
  • Patent number: 8981555
    Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has a package substrate, an integrated circuit die attached to the package substrate, and a package level heat dissipation device, such as an integrated heat spreader, attached to the package substrate encapsulating the integrated circuit die. The package level heat dissipation device has a top side with a ridge formed on top of a perimeter of the top side, and a bottom side that couples to the integrated circuit die.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventor: Ted Lee
  • Patent number: 8975743
    Abstract: In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: March 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tetsuo Kanamori, Yukihiro Yagi, Yasutaka Sugimoto, Takahiro Takada
  • Patent number: 8952525
    Abstract: A semiconductor module includes a case including a receiving space that is formed by a frame portion and a pair of wall portions disposed to face each other with the frame portion therebetween. The wall portion includes a heat-dissipation portions and a support wall that supports the heat-dissipation portions at the frame portion, and the wall portion includes a heat-dissipation portion and a support wall that supports the heat-dissipation portion at the frame portion. The heat-dissipation portions provided at the wall portion are separately provided by being disposed to face a plurality of semiconductor device blocks respectively. A plurality of separate heat-dissipation portions is surrounded by the support wall, the support wall is deformed to recessed from the frame portion through the separate heat-dissipation portions inside the case such that a plurality of insulating sheets is closely joined to a plurality of lead frames and the plurality of heat-dissipation portions.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 10, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Eiichi Ide, Takeshi Tokuyama, Nobutake Tsuyuno, Kinya Nakatsu, Tokihito Suwa, Yuujiro Kaneko
  • Patent number: 8941234
    Abstract: A method includes preparing a bonding surface of a heat dissipating member, applying flux to the bonding surface of the heat dissipating member, and removing excess flux from the bonding surface so that minimal flux is provided. The method also includes preparing a die surface of an electronic device package, applying flux to the die surface, and removing excess flux from the die surface so that minimal flux is provided. The method further includes positioning a preform solder component on the die surface, positioning the heat dissipating member over the die surface and the preform solder component such that the flux layer of the bonding surface is in contact with the preform solder component, and reflowing the solder component using a reflow oven. A heat spreader is also described for use in the process.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: January 27, 2015
    Assignee: DY 4 Systems, Inc.
    Inventors: Ivan Straznicky, Peter Robert Lawrence Kaiser, Steven Drennan, Marc-Jason Renaud, Georges Francis Marquis
  • Patent number: RE46448
    Abstract: A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Brent A. Anderson, Edward J. Nowak