Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

Abstract: A thermal interface for discrete semiconductor devices (such as IGBT's) having a thermally conductive structure, a PCB populated with discrete electronic components, and each of the discrete semiconductor devices having a housing extending beyond the edge of the PCB and in a direction substantially parallel to a plane of the PCB, and a clamp bar secured to the thermally conductive structure adapted to compressively secure each housing to the thermally conductive structure and adapted to maintain thermal contact between a surface of each housing and the surface of the thermally conductive structure. A thermally conductive and electrically insulative pad is positioned between the semiconductor device housing and the thermally conductive structure. A casing enclosing the interface and PCB includes the thermally conductive structure formed on a backwall of the casing.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip over the package substrate, and at least one integrated device integrated with the semiconductor chip. The integrated device is integrated directly beneath the semiconductor chip in order to facilitate signal transmission.

Abstract: The invention provides a semiconductor package, which may include a connection structure including one or more redistribution layers. A semiconductor chip is disposed on the connection structure and has an active surface on which a connection pad electrically connected to the redistribution layer is disposed and an inactive surface opposite to the active surface. An encapsulant is disposed on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant such that one exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is disposed on the encapsulant and covers the one exposed surface of the conductor pattern layer.

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

Abstract: A light emitting module includes a light emitting device, a heat dissipating plate, and a holder. The light emitting device has a light extraction window and a plurality of electrodes. The light emitting device is secured to the heat dissipating plate. The heat dissipating plate is secured to the holder. The holder includes a plurality of terminals respectively connected to the electrodes of the light emitting device. The heat dissipating plate includes an exposed portion exposed from the holder when viewed from a side of the light emitting module on which the light extraction window of the light emitting device is provided.

Abstract: A method produces an optoelectronic lighting device. The device efficiently increases a decoupling of electromagnetic radiation from a volume emitter LED chip. This is achieved in that, a frame made of an optical material is provided on side surfaces of the volume emitter LED chip, wherein the frame has a curved section. Light decoupled via the side surfaces of the volume emitter LED chip is thereby coupled into the frame, and can be decoupled again via same or reflected, for example, on a reflective material applied to the frame.

Abstract: A motor component for a linear motor, in particular a primary part and/or stator, which comprises a laminated core and a cooling body, wherein at least two grooves are arranged in the laminated core in order for at least two windings and/or at least two permanent magnets to be mounted in the grooves, wherein the grooves are arranged in parallel in one plane in the laminated core. In order to be able to produce good cooling and nevertheless provide a cost-effective motor component, the cooling body is connected to the laminated core and arranged parallel to the arrangement of the grooves, wherein the laminated core and the cooling body are adhesively bonded to one another.

Abstract: A thermal dissipation structure for integrated circuits includes a semiconductor substrate, a thermal dissipation trench, a metal seed layer and a metal layer. The semiconductor substrate has a first surface and a second surface which is opposite to the first surface. Integrated circuits are located on and thermally coupled with the first surface. The thermal dissipation trench is formed within the second surface. The metal seed layer seals the thermal dissipation trench to define a thermal dissipation channel. The thermal dissipation channel includes an inlet and an outlet. The metal layer is an electroplated layer formed from the metal seed layer.

Abstract: A clamp assembly is operable to engage at least three heat-generating electrical components arranged side-by-side and clamp the electrical components relative to a heat sink. The clamp assembly includes a clamp bar and a fastener to secure the clamp bar to the heat sink. The clamp bar includes at least three spaced apart projections configured to be located in engagement with the respective electrical components. The clamp bar presents a slot positioned between a spaced apart pair of the projections and defines respective clamp bar sections on opposite sides thereof. The slot permits the clamp bar sections to shift relative to one another and thereby facilitate clamping engagement of the projections with the electrical components.

Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

Abstract: A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

Abstract: An information handling system, including a substrate including a plurality of exposed electrical components on a top surface of the substrate; a bare die positioned on the top surface of the substrate; a gasket positioned on the top surface of the substrate, the gasket is non-electrically conductive; and an electrically conductive thermal interface material (TIM) positioned on a top surface of the bare die, wherein a top surface of the gasket and a top surface of the electrically conductive TIM are substantially flush, wherein the top surface of the electrically conductive TIM and the top surface of the gasket are opposite the top surface of the substrate, wherein the gasket inhibits contact between the electrically conductive TIM and the exposed electrical components.

Abstract: A layered composite configured to form an interface between a heat exchanger and an integrated circuit includes a first polymer layer, a second polymer layer, a liquid metal in direct contact with the first polymer layer, a solid solute in direct contact with the second polymer layer, and a barrier between the liquid metal and the solid solute. The liquid metal is liquid at normal temperature and pressure. The solid solute includes microparticles, nanoparticles, or both and is solid at normal temperature and pressure. The barrier prevents contact of the liquid metal and the solid solute at normal temperature and pressure, and is configured to rupture under compression of the layered composite, thereby allowing the liquid metal and the solid solute to form a mixture between the first polymer layer and the second polymer layer.

Abstract: A method for fabricating an electronic package includes providing a metal member including a supporting plate and a plurality of conductive pillars disposed on the supporting plate. A circuit structure is coupled to the conductive pillars. An electronic component is disposed on the metal member and electrically connected to the circuit structure. An encapsulant encapsulates the conductive pillars and the electronic component. Subsequently, the supporting plate is removed. Any mold can be used for fabricating the electronic package, no matter what the size of the electronic package is. Therefore, the fabricating cost of the electronic package is reduced.

Abstract: A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.

Abstract: A method of forming a semiconductor package includes dispensing an adhesive on a substrate that has an integrated circuit die attached thereon, placing a lid over the integrated circuit die such that a bottom surface of the lid caps at least a portion of the adhesive, and pressing the lid against the substrate such that a portion of the adhesive is squeezed from a space between the bottom surface of the lid and the substrate onto a sidewall of the lid.

Abstract: A carrier structure is provided. A spacer is formed in an insulation board body provided with a circuit layer, and is not electrically connected to the circuit layer. The spacer breaks the insulation board body, and a structural stress of the insulation board body will not be continuously concentrated on a hard material of the insulation board body, thereby preventing warpage from occurring to the insulation board body.

Abstract: Embodiments of the present invention relate to an heterogenous thermal interface material (TIM). The heterogenous TIM includes two or more different materials. One material has a low elastic modulus, also known as Young's modulus, and is utilized primarily to transfer heat from one component to another component. Another material has a higher elastic modulus and is primarily utilized to bond or connect the corners and/or edges of one component to the other component. The high elastic modulus material is generally located within the heterogenous TIM where TIM strain is or is expected to be high. For example, the high elastic modulus material may be located at the corner and/or edge regions of the heterogenous TIM.

Abstract: The disclosed component module includes a component comprising at least one electric contact to which at least one porous contact piece is connected; the component module further includes a cooling system for fluid-based cooling, said cooling system comprising one or more cooling ducts which are formed by pores of the porous contact piece. The disclosed power module comprises a component module of said type.

Abstract: An electronic package includes a metal member including a supporting plate and a plurality of conductive pillars disposed on the supporting plate. A circuit structure is coupled to the conductive pillars. An electronic component is disposed on the metal member and electrically connected to the circuit structure. An encapsulant encapsulates the conductive pillars and the electronic component. Any mold can be used for fabricating the electronic package, no matter what the size of the electronic package is. Therefore, the fabricating cost of the electronic package is reduced.

Abstract: An example method of attaching a printed circuit board (PCB) to a heat exchanger comprises: providing a heat exchanger comprising a base plate and two ridges attached to the base plate, wherein the ridges form a splayed channel; placing a printed circuit board (PCB) into the splayed channel; and squeezing the ridges of the splayed channel towards a longitudinal axis of the splayed channel.

Abstract: A light emitting module may include a board, at least one light source unit provided on the board, an optical member provided on the at least one light source unit, and a reflection unit provided between the board and the optical member in an inclined state beside at least one light source unit. The reflection unit may be provided closer to the optical member than to the board and may include a pattern having lower reflectance than other constructions of the light emitting module.

Abstract: Matching of coefficient of thermal expansion for heat spreaders and carrier die can facilitate optoelectronic die alignment. In one example, an apparatus comprises a carrier die comprising a first coefficient of thermal expansion, two or more optoelectronic die disposed on the carrier die, and a spreader. The spreader can comprise a second material coefficient of thermal expansion matched to the first coefficient of thermal expansion. Additionally, a thermal interface material is disposed between the spreader and the one or more optoelectronic die.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a semiconductor layer formed on the substrate. The semiconductor structure includes an isolation structure through the semiconductor layer, and the isolation structure has an opening with a first width, and the isolation structure has a vacuum gap. The semiconductor structure also includes a contact plug structure through the semiconductor layer, and the contact plug structure has an opening with a second width, and the second width is greater than the first width.

Abstract: An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein the second thickness is larger than the first thickness.

Abstract: A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.

Abstract: Methods for an embedded vibration management system are disclosed and may include fabricating a semiconductor package that supports vibration management by forming an array of vibration absorbing structures, placing the array proximate to a leadframe comprising two-legged supported leads, placing a semiconductor device above the leadframe, and encapsulating the semiconductor device and the leadframe. Each vibration absorbing structure may comprise a mass element formed on a material with lower density than that of the mass element. The array may be placed on a top, a bottom, or both surfaces of the leadframe. Sections of the array may be placed symmetrically with respect to the semiconductor device. The vibration absorbing structures may be cubic in shape and may be enclosed in an encapsulating material. The two-legged supported leads may be formed by bending metal strips with holes. The vibration absorbing structures may be exposed to the exterior of the semiconductor package.

Abstract: An apparatus body heat dissipation device includes an apparatus case, at least one plate body and at least one drive member. The apparatus case has at least one first opening and at least one second opening and a receiving space. The plate body is disposed in the receiving space. The drive member serves to drive the plate body to move within the receiving space to produce an air convection effect between the interior of the apparatus case and the ambient surrounding air of the apparatus case so that the air convection in the limited space of the apparatus body can be effectively enhanced to greatly enhance the heat dissipation efficiency.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: A device that reduces subcutaneous adipose tissue using a matrix of LEDs to heat and destroy fat cells. The surface facing the patient's skin may be a plate of thermally conductive material such as copper or aluminum, with apertures for the LEDs. Fat reduction may be optimized using infrared LEDs with peak spectral power in the range of 920 nm to 950 nm. The device may include multiple light emitting sections connected with flexible couplings so that the device can conform to curved body shapes; treatment surfaces of individual sections may also be curved. Sections may include cooling mechanisms to cool both the LEDs and the plate facing the patient's skin, such as thermoelectric cooling elements and air or water circulation. A user interface may provide monitoring and control of treatment parameters. The device may incorporate ultraviolet LEDs to facilitate removal of an adhesive attaching the device to the patient.

Abstract: The invention describes carrier structure (100, 200) for assembling a semiconductor lighting module, comprising at least two sub carriers (110, 210) and an alignment structure (120, 130, 230, 232) mechanically coupling the sub carriers (110, 210). The alignment structure (120, 130, 230, 232) is adapted such that the mechanical coupling to at least a part of the sub carriers (110, 210) disappears during thermal mating the carrier structure (100, 200) on a carrier (110, 250). The alignment structure (120, 130, 230, 232) is further adapted to compensate a coefficient of thermal expansion of a material of the carrier (110, 250) being higher than a coefficient of thermal expansion of a material of the carrier structure (100, 200). The invention further describes a semiconductor chip comprising such a carrier structure (100, 200) and a semiconductor lighting module comprising the carrier structure (100, 200) or the semiconductor chip.

Abstract: A composite electronic composite includes a plurality of multilayer ceramic capacitors each including a ceramic body in which dielectric layer and internal electrodes are alternately disposed and first and second external electrodes disposed on a lower surface of the ceramic body, a tantalum capacitor including a body part including a sintered tantalum powder material and a tantalum wire of which a portion is embedded in the body part and disposed on the plurality of multilayer ceramic capacitors, and a molding portion enclosing the tantalum capacitor and the plurality of multilayer ceramic capacitors.

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

Abstract: A power conversion apparatus includes a semiconductor module that includes a main body containing at least one semiconductor element, power terminals projecting from the main body to be connected to a high-voltage DC power supply and high-voltage signal terminals projecting from the main body, and is configured to convert a DC power supplied from the high-voltage DC power supply to an AC power by switching operation of the semiconductor element. The power conversion apparatus further includes a low-voltage component connected to a low-voltage DC power supply and a control circuit board on which a control circuit for controlling the switching operation of the semiconductor element is formed. The control circuit board is connected with low-voltage signal terminals extending from the low-voltage component and the high-voltage signal terminals. The low-voltage and high-voltage signal terminals are solder-connected to the control circuit board.

Abstract: Provided is a boron-nitride powder that is suitable for use in a resin composition for transmitting heat from a heat-producing electronic component such as a power device to a heat-dissipating member. The boron-nitride powder reduces thermal-conductivity anisotropy and thermal contact resistance, resulting in high thermal conductivity, and contains boron-nitride particles each consisting of hexagonal boron-nitride primary particles joined together. The boron-nitride powder, which is an aggregate of said boron-nitride particles, exhibits a mean sphericity of at least 0.70, a mean particle diameter of 20-100 ?m, a porosity of 50-80%, a mean pore diameter of 0.10-2.0 ?m, a maximum pore diameter of at most 10 ?m, and a calcium content of 500-5,000 ppm. Under X-ray powder diffraction, the graphitization index of the boron-nitride powder is preferably between 1.6 and 4.0, inclusive, and the peak intensity ratio (I(002)/I(100)) between the (002) plane and the (100) plane is preferably at most 9.0.

Abstract: In a laminating direction of first to fifth ceramic sheets, a first slit and a second slit are positioned closer to a first mounting section and a second mounting section than a first communication hole, a second communication hole, a third communication hole and a fourth communication hole. Moreover, an overlapping section where each first slit and the first communication hole overlap, and an overlapping section where each second slit and the third communication hole overlap, are positioned in the vicinity of an area where the first mounting section and the second mounting section are disposed when viewed from the laminating direction of the first to fifth ceramic sheets.

Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.

Abstract: A control unit is stored in an airtight housing constituted by a base, an annular peripheral wall member, a cover, and first and second interior packings, second wiring conductors connected to input/output equipment and first wiring conductors connected to a host controller through a control signal connector are brought into press-contact with input/output control terminals of the control unit by first and second pressing elastic mats, the relative positions of associated components are regulated by positioning pins passing through from the cover to the base, and the cover is opened by loosening blockade screws without causing an assembly dimension error or sliding wear of conductive contact portions due to thermal deformation, whereby the control unit is detached.

Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

Abstract: A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.

Abstract: Fastening systems for power modules including molded body (2) with flat surface (2a) bearing on supporting structure, and a plurality of protruding contact pins (3). A pressing element (5) presses a power module (1) on a side opposite the supporting structure. A connecting element (11) fastens the pressing element (5) on the supporting structure and imparts a force pressing towards the supporting structure. Sections (9, 10) formed on the pressing element (5) have outer edge regions (10) acting elastically on edge regions of the power module (1) in the fastened position. These edge regions are loaded with a pressing force towards the supporting structure. Such power modules (1) are useable with such fastening systems, as are the pressing elements (5).

Abstract: A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

Abstract: The invention relates to boron nitride agglomerates, comprising hexagonal boron nitride primary particles, wherein the hexagonal boron nitride primary particles are connected to one another by means of an inorganic binding phase comprising at least one nitride and/or oxynitride. The invention also relates to a method for producing such boron nitride agglomerates, wherein boron nitride starting powder in the form of boron nitride primary particles is mixed with binding-phase raw materials, processed into granules or molded bodies and these are then subjected to a temperature treatment at a temperature of at least 1000° C. in a nitriding atmosphere, and the obtained granules or molded bodies are comminuted and/or fractionated if necessary. The boron nitride agglomerates according to the invention are suitable as a filler for polymers to be used for producing polymer-boron nitride composite materials.

Abstract: A ceramic elements module including ceramic elements that have a plurality of lower inserting grooves; an electronic component that is mounted on a lower surface of the ceramic elements; and a heat sink that is coupled with a lower part of the ceramic elements mounted with the electronic component and has a first penetrating hole corresponding to the lower inserting groove and a second penetrating hole into which the electronic component is inserted.

Abstract: A surface mount semiconductor package, semiconductor device, and method for fabrication of the surface mount semiconductor package and electrical device are described that include a leadframe assembly, an integrated circuit device disposed on the leadframe assembly, a silicon shield disposed on the integrated circuit device, where the silicon shield is configured to mitigate packaging stress to the integrated circuit device, and a molding layer that encapsulates the integrated circuit device, the silicon shield, and at least a portion of the leadframe assembly.

Abstract: A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30). The lead terminals (21) are made of copper or a copper alloy. The die pad (10) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals (21).

Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.

Abstract: Cooling assemblies and power electronics modules having multiple-level porosity structures with both a micro- and macro-level porosity are disclosed. In one embodiment, a cooling assembly includes a jet impingement assembly including a fluid inlet channel fluidly coupled an array of orifices provided in a jet plate, and a heat transfer substrate having a surface. The heat transfer substrate is spaced apart from the jet plate. A first array of metal fibers is bonded to the surface of the heat transfer substrate in a first direction, and a second array of metal fibers is bonded to the first array of metal fibers in a second direction. Each metal fiber of the first array of metal fibers and the second array of metal fibers includes a plurality of metal particles defining a micro-porosity. The first array of metal fibers and the second array of metal fibers define a macro-porosity.

Abstract: A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.