Isolation Of Cooling Means (e.g., Heat Sink) By An Electrically Insulating Element (e.g., Spacer) Patents (Class 257/717)
  • Patent number: 8338852
    Abstract: A light emitting assembly (10) includes an aluminum heat sink (12) having a plurality of elongated slots (18) which space and define a plurality of sections (20). A pair of fins (30) extend from each section (20) along opposite sides of each elongated slot (18). A plurality of integral bridges (26) extend across the elongated slots (18). A screen (54) is disposed over each of the elongated slots (18). A light transmissive independent cover (44) is adhesively secured to each of the sections (20) around the light emitting diodes (28) so that one cover (44) independently covers the light emitting diodes (28) on each of the sections (20). The covers (44) are separated by the elongated slots (18). A housing (50) is spaced from the fins (30) and includes vents (52) whereby cooling air passes through the slots (18), over the fins (30), and out the vents (52).
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: December 25, 2012
    Assignee: Relume Technologies, Inc.
    Inventor: Peter A. Hochstein
  • Patent number: 8324653
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an insulative material. The heat spreader includes a base and a ceramic block. The conductive trace provides signal routing between a pad and a terminal. The insulative material extends between the base and the terminal. The ceramic block is embedded in the base. The semiconductor device overlaps the ceramic block, is electrically connected to the conductive trace and is thermally connected to the heat spreader.
    Type: Grant
    Filed: August 1, 2010
    Date of Patent: December 4, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 8324723
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump that includes first, second and third bent corners that shape a cavity. The conductive trace includes a pad and a terminal. The semiconductor device is located within the cavity, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends into an opening in the adhesive and provides a recessed die paddle and a reflector for the semiconductor device. The conductive trace provides signal routing between the pad and the terminal.
    Type: Grant
    Filed: November 20, 2010
    Date of Patent: December 4, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 8319335
    Abstract: The invention relates to a power semiconductor module including a power semiconductor chip arranged on a substrate and comprising a bottom side facing the substrate, a top side facing away from the substrate, and an electrical contact face arranged on the top side. A bond wire is bonded to the contact face. At least when the power semiconductor module is fastened to a heatsink, a contact pressure element creates a contact pressure force (F) acting on a sub-portion 36 of a bond wire portion configured between two adjacent bond sites. The contact pressure force (F) results in the power semiconductor chip and a substrate beneath being pressed against the heatsink.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Olaf Hohlfeld, Thilo Stolze
  • Patent number: 8304897
    Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Siva Prakash Gurrum, Paul J Hundt, Vikas Gupta
  • Patent number: 8305762
    Abstract: There is disclosed an apparatus of planar heat pipe for cooling, which may be embedded in a printed circuit board for cooling of heat-dissipating components. The apparatus includes two panels that are both metal clad on one side, at least one of the panels being grooved on its metal clad side, the panels being assembled by their metal clad sides to form a sealed cavity, the cavity being filled with a fluid, the fluid circulating by capillary action along the grooves towards zones exposed to heat where it vaporizes.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: November 6, 2012
    Assignee: Thales Nederland B.V.
    Inventors: Wessel Willems Wits, Jan Hendrik Mannak, Rob Legtenberg
  • Patent number: 8299608
    Abstract: A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, David R. Motschman, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jiantao Zheng
  • Patent number: 8299601
    Abstract: A power semiconductor module includes: a circuit board having a metal base plate, a high thermal conductive insulating layer, and a wiring pattern; power semiconductor elements electrically connected to the wiring pattern; tubular external terminal connection bodies provided to the wiring pattern for external terminals; and a transfer mold resin body encapsulated to expose through-holes in the metal base plate and used to fixedly attach cooling fins to the face of the metal base plate on the other side with attachment members, the face of the metal base plate on the other side, and top portions of the tubular external terminal connection bodies, to form insertion holes for the attachment members communicating with the through-holes and having a larger diameter than the through-holes, and to cover the one side and side faces of the metal base plate and the power semiconductor elements.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: October 30, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
  • Patent number: 8299606
    Abstract: A semiconductor device is provided that may include an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, and a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate. The heat sink may include a housing that is made of a metal sheet and radiating fins that are fixed in the housing and made of aluminum. The metal sheet may have a coefficient of thermal expansion between those of the insulating substrate and the radiating fin.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shogo Mori, Eiji Kono, Keiji Toh
  • Patent number: 8288845
    Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: October 16, 2012
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Howard Bartlow, William McCalpin, Michael Lincoln
  • Patent number: 8288792
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: October 16, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 8283776
    Abstract: An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 9, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: Arvind Chandrasekaran
  • Patent number: 8283773
    Abstract: A semiconductor device includes an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate and at least one anti-warping sheet disposed on at least one surface of the heat sink. The anti-warping sheet is made of a metal sheet having a coating layer and has coefficient of thermal expansion between those of the insulating substrate and the heat sink.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shogo Mori, Eiji Kono, Keiji Toh
  • Patent number: 8272230
    Abstract: A temperature control unit for an electronic component and a handler apparatus, which are excellent in responsibility during cooling and heating, is obtained. The temperature control unit for an electronic component includes a cooling cycle device having a refrigerant passage circulating through a compressor, a condenser, an expander, and an evaporator; a thermally conductive block having an outer surface capable of coming in contact with the electronic component that is an object to be temperature-controlled, where an inner surface corresponding to the outer surface is placed opposite to the outer surface so as to be brought in contact with or apart from the evaporator; at least one first heater for heating the thermally conductive block; and a compressed air feeding circuit for feeding compressed air between facing surfaces of the evaporator and the thermally conductive block to part them.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: September 25, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Nakamura
  • Patent number: 8269248
    Abstract: Apparatus may be provided including a high power light emitting diode (LED) unit, at least one printed circuit board, and an interfacing portion of a heat sink structure. The high power LED unit includes at least one LED die, at least one first lead and at least one second lead, and a heat sink interface. The at least one printed circuit board includes a conductive pattern configured to connect both the at least one first lead and the at least one second lead to a current source. The interfacing portion of the heat sink structure is that portion through which a majority of heat of the heat sink interface is transmitted. The interfacing portion is directly in touching contact with a majority of a heat transfer area of the heat sink interface.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: September 18, 2012
    Inventor: Joseph B. Thompson
  • Patent number: 8263852
    Abstract: A heat sink has a number of fixing frames. The fixing frames are soldered with of solar cell devices. And, the fixing frames are defined with insulating ink. Hence, the fixing frames can be used for insulating and locating the of a solar cell devices. Besides, with the insulating ink, solar cells of the solar cell devices are prevented from being contacted with the heat sink. As a result, a good electrical property is obtained on assembling and using the solar cell devices.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: September 11, 2012
    Assignee: Atomic Energy Council—Institute of Nuclear Energy Research
    Inventors: Zun-Hao Shih, Hwen-Fen Hong, Kuo-Hsin Lin
  • Patent number: 8254113
    Abstract: A circuit board assembly includes a motherboard defining a number of plug slots, and a fixing mechanism for securing a heat sink. The fixing mechanism is positioned between two adjacent plug slots, and includes a support member mounted on the motherboard, two fixing brackets mounted on opposite ends of the support member, two bars rotatably connected to the fixing brackets, and a connection member detachably connected to the support member by the bars. The opposite borders of the support member extend in the same direction substantially parallel to the plug slots, and the support member forms four connecting portions for securing the heat sink on opposite sides thereof, and the connecting portions are located between the opposite borders.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: August 28, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Tsung-Kuel Liao, Te-Chung Kuan, Chan-Kuei Hsu
  • Patent number: 8253237
    Abstract: A power semiconductor arrangement and method is disclosed. One embodiment provides a power semiconductor module. An insulator is arranged between the module and a cooling element, increasing clearances between the power semiconductor module and the cooling element.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: August 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Peter Kanschat, Thilo Stolze
  • Patent number: 8248786
    Abstract: A heat sink type module includes a mounting seat and a heat sink. The mounting seat includes a supporting plate, and two substantially parallel first side plates extending up from opposite first sides of the supporting plate. A latch protrudes from an inner surface of each first side plate. A heat sink includes a base plate and fins extending up from a top surface of the base plate. The base plate includes two substantially parallel first sides. The latches of the first side plates latch the first sides of the base plate to fix the heat sink.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: August 21, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Hao-Der Cheng
  • Patent number: 8247891
    Abstract: A chip package structure including a substrate, at least one chip, a plurality of leads, a heat dissipation device, a molding compound, and at least one insulating sheet is provided. The chip is disposed on the substrate. The leads are electrically connected to the substrate. The molding compound having a top surface encapsulates the chip, the substrate, and a portion of the leads. The heat dissipation device is disposed on the top surface of the molding compound. The insulating sheet disposed between the heat dissipation device and at least one of the leads has a bending line dividing the insulating sheet into a main body disposed on the molding compound and a bending portion extending from the main body.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: August 21, 2012
    Assignee: Cyntec Co., Ltd.
    Inventors: Chau-Chun Wen, Da-Jung Chen, Bau-Ru Lu, Chun-Hsien Lu
  • Patent number: 8232637
    Abstract: A power module includes one or more semiconductor power devices bonded to an insulated metal substrate (IMS). A plurality of cooling fluid channels is integrated into the IMS.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: July 31, 2012
    Assignee: General Electric Company
    Inventors: Richard Alfred Beaupre, Peter Almern Losee, Xiaochun Shen, John Stanley Glaser, Joseph Lucian Smolenski, Adam Gregory Pautsch
  • Patent number: 8232576
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base and a ceramic block. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post and the ceramic block is embedded in the post. The semiconductor device overlaps the ceramic block, is electrically connected to the conductive trace and is thermally connected to the ceramic block. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal.
    Type: Grant
    Filed: August 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang, Sangwhoo Lim
  • Patent number: 8212353
    Abstract: Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: July 3, 2012
    Assignee: Altera Corporation
    Inventors: Wen-chou Vincent Wang, Yuan Li, Bruce Euzent, Vadali Mahadev
  • Patent number: 8212346
    Abstract: A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: July 3, 2012
    Assignee: Global Foundries, Inc.
    Inventors: E. Todd Ryan, Holger Schuehrer, Seung-Hyun Rhee
  • Patent number: 8207553
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a base. A cavity extends through the adhesive into the base. The semiconductor device extends into the cavity, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The adhesive extends between the cavity and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 26, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang, Sangwhoo Lim
  • Patent number: 8193553
    Abstract: The invention provides a semiconductor high-power light-emitting module including a heat-dissipating member, a heat-conducting device, and a diode light-emitting device. The heat-dissipating member includes an isolator member coupled to a first side of the heat-dissipating member. The heat-dissipating member has a second side opposite to the first side. The isolator member has a third side opposite to the first side. The environment temperature at the third side is higher than that at the second side. The heat-conducting device has a flat end and a contact portion tightly mounted on the heat-dissipating member. The diode light-emitting device is disposed on the flat end of the heat-conducting device. The semiconductor light-emitting module of the invention, applied to a headlamp of an automobile, has properties of saving electricity and long life, and furthermore the capability of integrating the heat-dissipating member into a shell of the automobile is both artistic and practical.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 5, 2012
    Assignee: Neobulb Technologies, Inc.
    Inventor: Jen-Shyan Chen
  • Patent number: 8193634
    Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 5, 2012
    Inventors: Andre Wong, Sukbhir Bajwa
  • Patent number: 8193556
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The semiconductor device extends into a cavity in the post, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 5, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang, Sangwhoo Lim
  • Patent number: 8188593
    Abstract: The present invention relates to a silicon substrate having through vias and a package having the same. The silicon substrate includes a substrate body, a plurality of through vias and at least one heat dissipating area. The substrate body has a surface, and the material of the substrate body is silicon. The through vias penetrate the substrate body, and each of the through vias has a conductive material therein. The heat dissipating area is disposed on the surface of the substrate body and covers at least two through vias. The heat dissipating area is made of metal, and the through vias inside the heat dissipating area have same electrical potential. Thus, the heat in the through vias is transmitted to the heat dissipating area, and since the area of the heat dissipating area is large, the silicon substrate has good heat dissipation efficiency.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: May 29, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hua Chen, Kuo-Pin Yang
  • Patent number: 8183574
    Abstract: The present invention relates to an electronic device for providing improved heat transporting capability for protecting heat sensitive electronics and a method for producing the same. The present invention also relates to uses of the electronic device for various applications such as in LED lamps for signalizing, signage, automative and illumination applications or a display apparatus or any combinations thereof.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: May 22, 2012
    Assignee: NXP B.V.
    Inventor: Gilles Ferru
  • Patent number: 8179679
    Abstract: An electronic device includes a printed circuit board having a wall deposited directly on a board serving as a base for a printed circuit. As the board is constructed, the wall is deposited on the board for controlling airflow. The wall controls airflow across the board and around components mounted to the board. The wall may be utilized for controlling airflow in combination with a second printed circuit board positioned adjacent to the first printed circuit board. The wall may be utilized for controlling various types of airflow, including airflow from sources including fans and convection, and from geometries including horizontal and vertical mounting geometries. The silicon wall may be utilized for preventing heat airflow generated by heat radiated from one component from impinging upon another component.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: May 15, 2012
    Assignee: NetApp, Inc.
    Inventor: Richard A. Slagle
  • Patent number: 8178893
    Abstract: The invention provides a semiconductor element mounting substrate that, by virtue of an improvement in thermal conduction efficiency between the substrate and another member, can reliably prevent, for example, a light emitting element such as a semiconductor laser from causing a defective operation by heat generation of itself, by taking full advantage of high thermal conductivity of a diamond composite material.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: May 15, 2012
    Assignee: A. L. M. T. Corp.
    Inventors: Kouichi Takashima, Hideaki Morigami, Masashi Narita
  • Patent number: 8174116
    Abstract: Provided are a spacer capable of avoiding a poor connection due to the suction of solder when the clearance width between a soldered semiconductor device and a printed circuit board is made constant, and a manufacturing method for the spacer. The spacer includes an electrically insulating base member, and at least one solder guiding terminal. The base member has a bottom face, a top face and at least one side face, of which the bottom face and the top face are out of contact with each other whereas the side face contacts one or both the bottom face and the top face. The solder guiding terminal covers the bottom face partially, the top face partially, and the side face partially or wholly. A solder guiding face as the surface of a portion of the solder guiding terminal covering the side face is not normal to the bottom face.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: May 8, 2012
    Assignee: NEC Corporation
    Inventors: Koichiro Masuda, Tooru Mori
  • Publication number: 20120091573
    Abstract: Provided is a semiconductor device including a heat dissipating fin; an insulating sheet bonded to an upper surface of the heat dissipating fin, with a part of the upper surface being exposed; a heat spreader located on the insulating sheet; a power element located on the heat spreader; and a transfer molding resin located to cover a predetermined surface including the part of the upper surface of the heat dissipating fin, the insulating sheet, the heat spreader and the power element, wherein the upper surface of the heat dissipating fin has a protruding shape and/or recessed shape located so as to bind an edge of the insulating sheet.
    Type: Application
    Filed: May 20, 2011
    Publication date: April 19, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Taishi SASAKI, Tsuyoshi TAKAYAMA, Mikio ISHIHARA
  • Patent number: 8159000
    Abstract: Disclosed is a light emitting diode (LED) package having an array of light emitting cells coupled in series. The LED package comprises a package body and an LED chip mounted on the package body. The LED chip has an array of light emitting cells coupled in series. Since the LED chip having the array of light emitting cells coupled in series is mounted on the LED package, it can be driven directly using an AC power source.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 17, 2012
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Chung Hoon Lee, Keon Young Lee, Hong San Kim, Dae Won Kim, Hyuck Jung Choi
  • Patent number: 8159066
    Abstract: A semiconductor package having a heat dissipation member capable of efficiently conveying excess heat away from semiconductor chips is presented. The semiconductor package includes a semiconductor chip, through-electrodes, and a heat dissipation member. The semiconductor chip has a first surface, a second surface facing away from the first surface, and bonding pads which are disposed on the first surface. The through-electrodes are electrically connected with the bonding pads and passing through the first and second surfaces of the semiconductor chip, and protrude outward from the second surface. The heat dissipation member faces the second surface of the semiconductor chip and is coupled to the through-electrodes.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Taek Yang
  • Patent number: 8153886
    Abstract: An increased efficiency Concentrator Photovoltaic System having a plurality of solar cells laterally spaced from each other on a substrate panel. The solar cells are mounted on electrically conductive areas of an otherwise non-conductive top surface of the substrate with each cell isolated from another by a non-conductive area. The individual cells are connected using ribbons or wires, between the front contact of the solar cells to the conductive area of another cell to form a circuit connecting the cells in a desired configuration. A plurality of tubular enclosures for concentrating light on the solar cells are mounted directly above the solar cells.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: April 10, 2012
    Assignee: Amonix, Inc.
    Inventors: Vahan Garboushian, Alexander M. Slade
  • Patent number: 8149574
    Abstract: A cooling fan housing assembly for assembling to a heat sink includes a boosting portion and a connecting portion extended from the boosting portion. The connecting portion includes a first part and a second part for covering on and fixing to the heat sink. The second part of the connecting portion is provided with at least one hooking section for firmly hooking to the heat sink, so that a cooling fan supported on the cooling fan housing assembly can be quickly assembled to the heat sink without the risk of producing vibration during the operation of the cooling fan. Therefore, the cooling fan housing assembly not only reduces assembling labor and time and manufacturing cost, but also enables stable operation of the cooling fan.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: April 3, 2012
    Assignee: Asia Vital Components Co., Ltd.
    Inventor: Sheng-Huang Lin
  • Patent number: 8138597
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: March 20, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8134232
    Abstract: A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically conductive, with a port disposed in the passivation layer. The port extends completely through the passivation layer to expose an underlying layer. A thermal pathway is disposed at least partially within the port, and makes thermal contact to both the underlying layer and the heat sink. The thermal transfer rate of the thermal pathway is greater than the thermal transfer rate either the passivation layer or the encapsulant.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: March 13, 2012
    Assignee: LSI Corporation
    Inventors: Mitchel E. Lohr, Qwai H. Low
  • Patent number: 8129742
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The conductive trace includes a pad, a terminal and a plated through-hole. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The conductive trace provides signal routing between the pad and the terminal using the plated through-hole.
    Type: Grant
    Filed: April 2, 2011
    Date of Patent: March 6, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 8125078
    Abstract: A semiconductor element cooling structure includes first and second semiconductor elements; a heat sink having a mounting surface on which the semiconductor elements are mounted and a cooling medium channel formed inside, through which a cooling medium for cooling the semiconductor elements flows; and a protruded portion provided at a position opposite to the mounting surface of the heat sink, extending in a direction intersecting flow direction of the cooling medium (direction of arrow DR1) and protruding from a bottom surface of the cooling medium channel to the inside of cooling medium channel. The semiconductor elements are arranged side by side in the direction of arrow DR1, such that the first semiconductor element is positioned upstream side than the second semiconductor element.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: February 28, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tadafumi Yoshida, Hiroshi Osada, Yutaka Yokoi
  • Publication number: 20120043652
    Abstract: A semiconductor power module includes an active element and a passive element serving as semiconductor elements each having a first electrode on a front surface and a second electrode on a back surface thereof, a heat pipe having a first region defined as arrangement parts of the active element and the passive element on its one end side and electrically connected to one of the first and second electrodes of the active element and the passive element arranged in the first region, a cooling fin arranged in a second region defined on the other end side of the heat pipe, and a heat pipe provided to sandwich the active element, the passive element, and the cooling fin arranged on the heat pipe along with the heat pipe and electrically connected to the other of the first and second electrodes of the active element and passive element.
    Type: Application
    Filed: May 24, 2011
    Publication date: February 23, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Koichi USHIJIMA
  • Patent number: 8120170
    Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: February 21, 2012
    Assignee: ATI Technologies ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
  • Patent number: 8115369
    Abstract: Disclosed is a lighting device. The lighting device includes: a substrate; a light emitting device disposed on the substrate; a heat radiating body radiating heat from the light emitting device; and a pad being interposed between the substrate and the heat radiating body and transferring heat generated from the light emitting device to the heat radiating body and comprising silicon of 10 to 30 wt %, a filler of 70 to 90 wt %, glass fiber of 2 to 7 wt % in terms of weight percent (wt %).
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: February 14, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Seok Jin Kang, Tae Young Choi, Sungho Hong, Dong Soo Kim
  • Patent number: 8094454
    Abstract: An immersion cooling apparatus includes a multi-terminal thermally conductive module that supports and encloses a power semiconductor device and a housing defining a flow-through chamber in which the thermally conductive module is mounted and through which liquid coolant is circulated. The thermally conductive module has first and second oppositely disposed connector headers housing terminal pins or blades electrically coupled to the semiconductor device, and the connector headers protrude through openings in oppositely disposed sidewalls of the housing so that the portion of the thermally conductive module between the connector headers is suspended in the chamber and immersed in the circulating coolant. The thermally conductive module is sealed against the housing sidewalls around the openings, and one of the sidewalls is removable to facilitate installation of the thermally conductive module in the housing or its subsequent removal.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: January 10, 2012
    Assignee: Delphi Technologies, Inc.
    Inventor: Michael J. Lowry
  • Patent number: 8093713
    Abstract: The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: January 10, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Xaver Schloegel, Christof Matthias Schilz
  • Patent number: 8081472
    Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: December 20, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Tokuyama, Kinya Nakatsu, Atushi Kawabata
  • Publication number: 20110304037
    Abstract: A semiconductor device includes an enclosure of insulating material having an introduction portion and a discharge portion for an insulating refrigerant and also having an opening, filters mounted on the introduction portion and the discharge portion, respectively, so as to prevent conductive foreign matter from entering the enclosure, a power semiconductor element provided on the outside of the enclosure, a heat sink bonded to the power semiconductor element and extending through the opening and within the enclosure, and an insulator covering the portions of the power semiconductor element and the heat sink lying outside of the enclosure.
    Type: Application
    Filed: February 15, 2011
    Publication date: December 15, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noboru Miyamoto, Shouji Saito
  • Patent number: 8072053
    Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 6, 2011
    Assignee: Kaixin Inc.
    Inventor: Tung Lok Li