Isolation Of Cooling Means (e.g., Heat Sink) By An Electrically Insulating Element (e.g., Spacer) Patents (Class 257/717)
  • Patent number: 8064203
    Abstract: A free standing film includes: i. a matrix layer having opposing surfaces, and ii. an array of nanorods, where the nanorods are oriented to pass through the matrix layer and protrude an average distance of at least 1 micrometer through one or both surfaces of the matrix layer. A method for preparing the free standing film includes (a) providing an array of nanorods on a substrate, optionally (b) infiltrating the array with a sacrificial layer, (c) infiltrating the array with a matrix layer, thereby producing an infiltrated array, optionally (d) removing the sacrificial layer without removing the matrix layer, when step (b) is present, and (e) removing the infiltrated array from the substrate to form the free standing film. The free standing film is useful as an optical filter, ACF, or TIM, depending on the type and density of nanorods selected.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: November 22, 2011
    Assignee: Dow Corning Corporation
    Inventors: Carl Fairbank, Mark Fisher
  • Patent number: 8058736
    Abstract: The present invention provides a semiconductor device including: a semiconductor chip mounted on a substrate; a heat spreader provided above the semiconductor chip; and a sealing resin interposed between the semiconductor chip and the heat spreader and covering the semiconductor chip. The heat spreader is not in contact with any of the substrate and the semiconductor chip, and has an opening.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: November 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Koike, Kenichi Kurihara
  • Patent number: 8039316
    Abstract: A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a first integrated circuit to the substrate by interconnects only along opposite sides of the first integrated circuit; and attaching a heat spreader to the substrate, the heat spreader extending over the first integrated circuit and between the opposite sides of the first integrated circuit.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: HeeJo Chi, Soo Jung Park, HanGil Shin
  • Patent number: 8035237
    Abstract: An integrated circuit package system is provided including providing a substrate having a die attached and electrically bonded thereto. The system includes forming heat slug pillars on the substrate, positioning a heat slug on the heat slug pillars, and encapsulating the substrate, the die, the heat slug pillars, and the heat slug in a mold compound. The system includes singulating the substrate, the die, the heat slug, and the mold compound.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: SeongMin Lee, Tae Keun Lee
  • Patent number: 8030762
    Abstract: An LED package having an anodized insulation layer which increases heat radiation effect to prolong the lifetime LEDs and maintains high luminance and high output, and a method therefor. The LED package includes an Al substrate having a reflecting region and a light source mounted on the substrate and connected to patterned electrodes. The package also includes an anodized insulation layer formed between the patterned electrodes and the substrate and a lens covering over the light source of the substrate. The Al substrate provides superior heat radiation effect of the LED, thereby significantly increasing the lifetime and light emission efficiency of the LED.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: October 4, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Young Ki Lee, Seog Moon Choi, Sang Hyun Shin
  • Patent number: 8030113
    Abstract: The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Ping-Chuan Wang, Xiaojin Wei, Huilong Zhu
  • Patent number: 8030758
    Abstract: A semiconductor module (10) includes a heat sink (1), an electronic component (2), a semiconductor device (3), and a thermally-conductive sheet member (4). The thermally-conductive sheet member (4) covers a part of the semiconductor device (3) and has a lower part (4b) and a side part (4c). The lower part (4b) is in contact with a mounting face (11a) of the heat sink (1). The side part (4c) extends from the lower part (4b) and covers a first side surface (3c) of the semiconductor device (3). The electronic component (2) is disposed across the side part (4c) of the thermally-conductive sheet member (4) from the semiconductor device (3).
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventor: Makoto Kitabatake
  • Patent number: 8030754
    Abstract: One embodiment in accordance with the invention is a system that can include a first wafer and a second wafer. The first wafer and the second wafer can be bonded together by a wafer bonding process that forms a gap between the first wafer and the second wafer. The gap can be configured for receiving a heat extracting material.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: October 4, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter G. Hartwell, Duncan Stewart
  • Publication number: 20110233758
    Abstract: A semiconductor devices includes a first die pad having the conductivity connected to one end of a DC power source, a second die pad having the conductivity connected to the other end of the DC power source, a first switching element provided on the first die pad, receiving DC power from the DC power source via the first die pad, and having a terminal opposite to the first die pad connected to a first output terminal, and a second switching element provided on the second die pad, receiving the DC power from the DC power source via the second die pad, and connected to the first output terminal, and having a terminal opposite to the second die pad.
    Type: Application
    Filed: February 23, 2011
    Publication date: September 29, 2011
    Applicant: Sanken Electric Co., Ltd.
    Inventors: Osamu MACHIDA, Michiyoshi Izawa
  • Patent number: 8022532
    Abstract: An interposer and a semiconductor device including the interposer, which can prevent thermal warpage of an insulative substrate. The interposer is provided with a semiconductor chip in a semiconductor device and may be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: September 20, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Sadamasa Fujii, Motoharu Haga
  • Patent number: 8022534
    Abstract: A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on the chip and located in the through opening.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 20, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tong Hong Wang, Chang Chi Lee
  • Patent number: 8018053
    Abstract: One example discloses a heat transfer device that can comprise a semiconductor material having a first region and a second region. The first region and the second region are doped to propel a charged carrier from the first region to the second region. The heat transfer device can also comprise an array of pointed tips thermoelectrically communicating with the second region. A heat sink faces the array, and a vacuum tunneling region is formed between the pointed tips and the heat sink. The heat transfer device further can further comprise a power source for biasing the heat sink with respect to the first region. The first region defines an N-type semiconductor material and the second region defines a P-type semiconductor material.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: September 13, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Harvey C. Nathanson, Robert M. Young, Joseph T. Smith, Robert S. Howell, Archer S. Mitchell
  • Patent number: 8008768
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a casing, a board and a semiconductor chip. The chip includes: an element part; a heat sink bonded to the element part; an insulting layer located on the heat sink so that the heat sink is located between the element part and the insulating layer; and a side wall insulating layer covering all of end faces of the heat sink. The semiconductor chip is located between the casing and the board, so that the insulating layer is directed to the casing to enable heat radiation from the heat sink toward the casing via the insulating layer.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: August 30, 2011
    Assignee: DENSO CORPORATION
    Inventor: Takeshi Miyajima
  • Patent number: 7999374
    Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi So, Hideo Kubo, Seiji Ueno, Osamu Igawa
  • Patent number: 7999375
    Abstract: An electronic device can comprise a semiconductor die on which can be formed a micromechanical system. The micromechanical system can comprise a plurality of electrically conductive elongate, contact structures, which can be disposed on input and/or output terminals of the semiconductor die. The micromechanical system can also comprise a cooling structure disposed on the semiconductor die.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: August 16, 2011
    Assignee: FormFactor, Inc.
    Inventors: Eric D. Hobbs, Gaetan L. Mathieu
  • Patent number: 7993978
    Abstract: A method of manufacturing a semiconductor device capable of obtaining high joining force between a heat spreader and resin is provided. The method of manufacturing a semiconductor device according to the present invention includes: setting a heat spreader 60 on a face formed a plurality of apertures 22 in a cavity 21 of a first molding die 14; filling resin 20 into the cavity; setting a substrate 54 mounted with a semiconductor chip 50 a second molding die 12; and pressure-welding the first molding die 14 and the second molding die 12 so that the semiconductor chip is embedded in the resin 20, wherein a plurality of concave portion is formed on one face of the heat spreader 60, a plurality of convex portions is formed on the other face of the heat spreader 60, and the plurality of concave portions and the plurality of convex portions are overlapped in plan view.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuko Sato
  • Patent number: 7989839
    Abstract: The present invention provides a method and apparatus for using light emitting diodes for curing and various solid state lighting applications. The method includes a novel method for cooling the light emitting diodes and mounting the same on heat pipe in a manner which delivers ultra high power in UV, visible and IR regions. Furthermore, the unique LED packaging technology of the present invention utilizes heat pipes that perform very efficiently in very compact space. Much more closely spaced LEDs operating at higher power levels and brightness are possible because the thermal energy is transported in an axial direction down the heat pipe and away from the light-emitting direction rather than a radial direction in nearly the same plane as the “p-n” junction.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: August 2, 2011
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventor: Jonathan S. Dahm
  • Patent number: 7982299
    Abstract: Included are a semiconductor package, a first bus bar, a second bus bar and a soldering control unit. The semiconductor package includes a power semiconductor element, a first electrode plate and a second electrode plate. The first bus bar is a conductive member which is soldered onto the main surface of the first electrode plate through a first solder member. The second bus bar is a conductive member which is soldered onto the main surface of the second electrode plate through a second solder member. The soldering control unit is provided on each of the main surface of the first bus bar to which the first electrode plate is soldered and the main surface of the second bus bar to which the second electrode plate is soldered, and controls the solder joint thickness.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: July 19, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naotake Watanabe
  • Patent number: 7982307
    Abstract: An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: July 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Ahmed Amin, David L. Crouthamel, John W. Osenbach, Thomas H. Shilling, Brian T. Vaccaro
  • Patent number: 7982293
    Abstract: A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing area.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: July 19, 2011
    Assignee: Infineon Technologies AG
    Inventors: Wei Kee Chan, Weng Shyan Aik
  • Patent number: 7973400
    Abstract: A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Jin Paek, Woo-Seop Kim, Ki-Sung Kim
  • Patent number: 7968925
    Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: June 28, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito
  • Patent number: 7965506
    Abstract: A heat sink apparatus and method are provided for allowing air to flow directly to an integrated circuit package thereunder. In use, a heat sink is provided including an upper portion with a plurality of fins, and a lower portion configured for allowing air to flow directly to an integrated circuit package thereunder.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: June 21, 2011
    Assignee: NVIDIA Corporation
    Inventors: Zhihai Zack Yu, Don Le
  • Patent number: 7960827
    Abstract: A thermal via heat spreader package includes an electronic component having an active surface including a nonfunctional region. A package body encloses the electronic component, the package body comprising a principal surface. Thermal vias extend from the principal surface through at least a portion of the package body and towards the nonfunctional region. A heat spreader is thermally connected to the thermal vias. Heat generated by the electronic component is dissipated to the thermal vias and to the heat spreader. The density of the thermal vias is increased in a hotspot of the electronic component thus maximizing heat transfer from the hotspot. In this manner, optimal heat transfer from the electronic component is achieved.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: June 14, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: August J. Miller, Jr., Jeffrey A. Miks, Christopher M. Scanlan, Mahmoud Dreiza
  • Patent number: 7957146
    Abstract: The invention relates to an illumination device (1) comprising at least one preferably ceramic substrate plate (2), at least one luminous element (3) arranged on a front side (A) of the substrate plate (2) in particular at least one light emitting diode (LED) (3), and at least one preferably metallic heat sink (4) connected, in particular adhesively bonded and/or soldered, to a rear side (B) of the substrate plate (2) over a large area, wherein the coefficients of thermal expansion of substrate plate (2) and heat sink (4) differ at least by the factor 1.5, in particular by a factor greater than 2. The heat sink (4) has at least one preferably linear recess (6) on its side facing the rear side (B) of the substrate plate (2).
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: June 7, 2011
    Assignee: OSRAM Gesellschaft mit beschränkter Haftung
    Inventors: Robert Kraus, Steffen Straub
  • Patent number: 7956456
    Abstract: An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 7, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Siva Prakash Gurrum, Paul Joseph Hundt, Vikas Gupta
  • Patent number: 7952191
    Abstract: A semiconductor device of the present invention includes a wiring substrate, a plurality of semiconductor chips mounted on the wiring substrate, and a radiation plate arranged over a plurality of semiconductor chips, and having a cooling passage to flow water in a horizontal direction to the wiring substrate. A plurality of semiconductor chips are arranged along the cooling passage, and out of the plurality of semiconductor chips, the semiconductor chip arranged on an inflow side of the cooling passage, has a smaller amount of heat generation than the semiconductor chip arranged on an outflow side of the cooling passage. For example, a memory chip is arranged on the inflow side of the cooling passage, and a logic chip is arranged on the outflow side of the cooling passage.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: May 31, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Mitsutoshi Higashi
  • Patent number: 7952192
    Abstract: A melting temperature adjustable metal thermal interface material (TIM) and a packaged semiconductor including thereof are provided. The metal TIM includes about 20-98 wt % of In, about 0.03-4 wt % of Ga, and at least one element of Bi, Sn, Ag and Zn. The metal TIM has an initial melting temperature between about 60-144° C.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: May 31, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yuan-Chang Fann, Jenn-Dong Hwang, Cheng-Chou Wong
  • Patent number: 7944042
    Abstract: A semiconductor device includes an outer resin case having a peripheral wall and terminal mounting holes formed in the peripheral wall, and a layer assembly provided in the outer resin case. The layer assembly includes a semiconductor chip, an insulating circuit board on which the semiconductor chip is mounted, and a heat-dissipating metal base. External terminals having leg portions are arranged in mounting holes of the peripheral wall, and are press-fitted into the terminal-mounting holes. Bonding wires connect the terminal leg portions and a conductive pattern of the insulating circuit board or the semiconductor chip.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: May 17, 2011
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Katsuhiko Yoshihara, Rikihiro Maruyama, Masaaki Chino, Eiji Mochizuki, Motokiyo Yokoyama, Tatsuo Nishizawa, Tomonobu Sugiyama
  • Patent number: 7943430
    Abstract: A semiconductor device and a method for manufacturing the same are described. The semiconductor device comprises: a heat sink having at least one opening passing through the heat sink; at least one semiconductor chip disposed in the opening, wherein the semiconductor chip includes a first side and a second side on opposite sides; an electricity conducting thin film filling in a first depth portion of the opening, wherein the second side of the semiconductor chip is embedded in the electricity conducting thin film; a heat conducting thick film filling in a second depth portion of the opening, wherein the electricity conducting thin film is directly connected with the heat conducting thick film; at least one wire electrically connecting the semiconductor chip and an external circuit; and an encapsulant covering a portion of the heat sink, the semiconductor chip, the wire and an exposed portion of the electricity conducting thin film.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: May 17, 2011
    Inventor: Kuan-Chun Chen
  • Patent number: 7944045
    Abstract: A semiconductor module and a method of manufacturing the same are disclosed including a semiconductor element having an electrode, a heat radiation plate placed in thermal contact with a main surface of the semiconductor element and electrically connected to the electrode thereof, an insulation body directly formed on an outside surface of the heat radiation plate, a metallic body directly formed on an outside surface of the insulation body and having a thickness lower than that of the insulation body, and a mold resin unitarily molding the heat radiation plate, the semiconductor element and the insulation body. The insulation body is covered with the metallic body and the mold resin and the metallic body has an outside surface exposed to an outside of the mold resin.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: May 17, 2011
    Assignee: Denso Corporation
    Inventors: Chikage Noritake, Takanori Teshima, Kuniaki Mamitsu
  • Publication number: 20110108979
    Abstract: In a COF of an embodiment of the present invention, the smaller distance to edges of a heat-releasing member an area of the heat-releasing member has, the larger openings the area has. Accordingly, a volume per area (an area per length) of the heat-releasing member decreases toward the edges. The arrangement improves flexibility of the COF. This prevents a stress caused by bending the COF from concentrating at the edges. This makes it possible to prevent a line on an insulating film from being broken. Also, it becomes possible to prevent an anisotropic conductive resin from coming off which is used to bond the COF with a display panel in providing the COF in a display apparatus.
    Type: Application
    Filed: July 7, 2009
    Publication date: May 12, 2011
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tomokatsu Nakagawa, Yasunori Chikawa, Akiteru Rai, Tatsuya Katoh, Takuya Sugiyama
  • Patent number: 7939919
    Abstract: An LED-packaging arrangement, comprising: a first connection block with an enclosure groove at the bottom thereof; a second connection block with an enclosure groove at the bottom thereof; a light-emitting chip positioned at the top of the first connection block and via connection wires electrically coupled to the first and second connection blocks; a positioning/packaging body, and a transparent packaging body. Alternatively, a third connection block is provided with an enclosure groove at the bottom thereof. In this case, the electrical connection originally to the first connection block via the connection wire is changed to the third connection block. The first and second connection blocks are enclosed by the lower part of the positioning/packaging body in position such that the bottom surfaces of the first and second connection blocks are exposed. The upper part of the positioning/packaging body encloses the light-emitting chip so as to create a reflection cap.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: May 10, 2011
    Assignee: Lumenmax Optoelectronics Co., Ltd.
    Inventor: Chia-Han Hsieh
  • Patent number: 7936056
    Abstract: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: May 3, 2011
    Assignee: Olympus Corporation
    Inventor: Tomoyuki Hatakeyama
  • Patent number: 7932597
    Abstract: A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: April 26, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Makoto Terui, Yasushi Shiraishi
  • Patent number: 7928548
    Abstract: A heat spreader attached to a heat source that includes a semiconductor chip includes a silicon structure that provides a plurality of heat flux paths, including a lateral, in-plane heat flux path. The heat spreader is mounted in-plane with the heat source.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Sri M. Sri-Jayantha
  • Patent number: 7928562
    Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Amilcar R. Arvelo, Evan G. Colgan, John H. Magerlein, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jeffrey A. Zitz
  • Patent number: 7923665
    Abstract: An object of the present invention is to provide a wafer-type thermometer capable of adapting itself to automation and improving the heat resistance to measure temperature distribution of a wafer and a method for manufacturing the wafer-type thermometer. A plurality of temperature sensors are arranged in regions formed by segmenting the upper surface of a wafer into a plurality of regions. Output signals from the plurality of temperature sensors are converted into temperature data by a conversion processing circuit where further processes the temperature data. The conversion processing circuit is housed in a storage room surrounded by a heat insulating member made of a nanocrystalline silicon layer.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Toshiyuki Matsumoto, Tomohide Minami
  • Patent number: 7923826
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: April 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Takahashi, Mamoru Shishido
  • Patent number: 7923834
    Abstract: An interposer and a semiconductor device including the interposer, which can prevent thermal warpage of an insulative substrate. The interposer is provided with a semiconductor chip in a semiconductor device and may be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: April 12, 2011
    Assignee: ROHM Co., Ltd.
    Inventors: Yasumasa Kasuya, Sadamasa Fujii, Motoharu Haga
  • Patent number: 7919854
    Abstract: A semiconductor module with two cooling surfaces and method. One embodiment includes a first carrier with a first cooling surface and a second carrier with a second cooling surface. The first cooling surface is arranged in a first plane, the second cooling surface is arranged in a second plane, at an angle different from 0° relative to the first plane.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: April 5, 2011
    Assignee: Infineon Technologies AG
    Inventor: Thilo Stolze
  • Patent number: 7919852
    Abstract: A semiconductor device including: an insulating substrate including a ceramic substrate having first and second principal surfaces, a first metallic conductor fixed on the first principal surface, and a second metallic conductor fixed on the second principal surface; a semiconductor element disposed on the first metallic conductor on the first principal surface; and a base plate connected to the second metallic conductor on the second principal surface, and on which the insulating substrate being disposed. The second metallic conductor includes a joint area connected to the second principal surface, and a non-joint area formed around the joint area.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: April 5, 2011
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Junji Yamada
  • Patent number: 7915729
    Abstract: A load driving semiconductor apparatus includes: a driving transistor, which operates based on an input voltage from an external circuit; a power semiconductor device controlling power supply to a load in such a manner that the power semiconductor device supplies electric power to the load when the transistor operates, and the power semiconductor device stops supplying electric power to the load when the transistor stops operating; and a mounting board, on which the driving transistor and the power semiconductor device are mounted. The mounting board includes a heat radiation pattern for emitting heat generated in the power semiconductor device. The heat radiation pattern includes a heat receiving pattern, on which the driving transistor is mounted.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: March 29, 2011
    Assignee: Anden Co., Ltd.
    Inventors: Yoshimitsu Ukai, Kazunori Ozawa, Fukuo Ishikawa
  • Patent number: 7911050
    Abstract: A COF which can effectively dissipate the heat by using a simple structure and its manufacturing method. A semiconductor device of COF, which is formed over the main surface of a flexible substrate having no device hole and where a semiconductor chip is mounted over the inner lead interconnection, is characterized by forming a first resin layer over the second main surface of the flexible substrate opposite the side where the semiconductor chip is mounted and at the position corresponding to the semiconductor chip.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Nakajima
  • Patent number: 7911059
    Abstract: A method and apparatus for packaging semiconductor dies for increased thermal conductivity and simpler fabrication when compared to conventional semiconductor packaging techniques are provided. The packaging techniques described herein may be suitable for various semiconductor devices, such as light-emitting diodes (LEDs), central processing units (CPUs), graphics processing units (GPUs), microcontroller units (MCUs), and digital signal processors (DSPs). For some embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower cavity with one or more metal layers deposited therein to dissipate heat away from the semiconductor dies. For other embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower surface with one or more metal layers deposited thereon for efficient heat dissipation.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: March 22, 2011
    Assignee: SeniLEDS Optoelectronics Co., Ltd
    Inventors: Ching-Tai Cheng, Jui-Kang Yen
  • Patent number: 7911052
    Abstract: The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap.
    Type: Grant
    Filed: September 30, 2007
    Date of Patent: March 22, 2011
    Assignee: Intel Corporation
    Inventors: Unnikrishnan Vadakkanmaruveedu, Gregory Martin Chrysler, James G. Maveety
  • Patent number: 7898068
    Abstract: Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: March 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane
  • Patent number: 7893529
    Abstract: The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Ping-Chuan Wang, Xiaojin Wei, Huilong Zhu
  • Patent number: 7888793
    Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: February 15, 2011
    Assignee: Nuvotronics, LLC
    Inventors: David W. Sherrer, Larry J. Rasnake, John J. Fisher
  • Patent number: 7888852
    Abstract: A light-emitting diode (LED) heat dissipation structure is provided, including a package body, a heat dissipation frame, at least one light emitting die, a plurality of conductive leads, and a plurality of conductive wires. The package body forms a cavity and has an outside surface. The heat dissipation frame is coupled to the package body and has a portion disposed inside the cavity. The end section of the heat dissipation frame that projects beyond the lateral segment of the outside surface is bent to extend along the outside surface. The light emitting die is accommodated in the cavity and set on the heat dissipation frame. The conductive leads are disposed in the cavity and each extends through a side wall of the cavity to project beyond a lateral segment of the outside surface. The conductive wires connect the light emitting die and the conductive leads inside the cavity.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 15, 2011
    Inventor: Wen-Kung Sung