Abstract: An organic light emitting diode display includes a substrate main body, a semiconductor layer and a first capacitor electrode on the substrate main body, bottom surfaces of the semiconductor layer and first capacitor electrode being substantially coplanar, and each of the semiconductor layer and first capacitor electrode including an impurity-doped polysilicon layer, a gate insulating layer on the semiconductor layer and the first capacitor electrode, a gate electrode on the semiconductor layer with the gate insulating layer therebetween, and a second capacitor electrode on the first capacitor electrode with the gate insulating layer therebetween, the second capacitor electrode including a convex electrode portion and a concave electrode portion, the concave electrode portion being thinner than each of the convex electrode portion and the gate electrode.

Abstract: In an active matrix type liquid crystal display device, in which functional circuits such as a shift register circuit and a buffer circuit are incorporated on the same substrate, an optimal TFT structure is provided along with the aperture ratio of a pixel matrix circuit is increased. There is a structure in which an n-channel TFT, with a third impurity region which overlaps a gate electrode, is formed in a buffer circuit, etc., and an n-channel TFT, in which a fourth impurity region which does not overlap the gate electrode, is formed in a pixel matrix circuit. A storage capacitor formed in the pixel matrix circuit is formed by a light shielding film, a dielectric film formed on the light shielding film, and a pixel electrode. Al is especially used in the light shielding film, and the dielectric film is formed anodic oxidation process, using an Al oxide film.

Abstract: A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.

Abstract: A thin film transistor array substrate, a driving method therefore, and a liquid crystal display are disclosed.

Abstract: A display device includes a pixel array section, the pixel array section having pixels arranged in a matrix form, at least one of the pixels including an electro-optical element, a write transistor, a capacitor, a drive transistor, and a switching transistor. A write scan line is disposed for each pixel row of the pixel array section and adapted to convey a write signal to be applied to a gate electrode of the write transistor. The wiring structure of the write scan line does not cross a wiring pattern connected to a gate electrode of the drive transistor.

Abstract: An auxiliary capacitor (6) of each of sub-pixels (P) includes a transparent electrode, a pixel electrode, and a capacitor insulating film between the transparent electrode and the pixel electrode. Switching elements (5a) are connected, for every predetermined sub-pixel(s) (P) along a column direction of the sub-pixels (P) arranged in rows and columns, to the source lines (15a) different from each other. A plurality of transparent electrodes are each shared by a pair of the sub-pixels (P) which are adjacent to each other in a predetermined direction and are arranged in a corresponding one of the wide spaces each provided between adjacent two of gate lines (13). The transparent electrodes adjacent to each other in the row direction receive different signals.

Abstract: A thin-film semiconductor device includes a semiconductor device part and a capacitor part. The semiconductor device part includes: a light-transmitting first gate electrode; a light-shielding second gate electrode; a first insulating layer; a semiconductor layer; a second insulating layer; and a source electrode and a drain electrode. The capacitor part includes: a first capacitor electrode made of a light-transmitting conductive material; a dielectric layer; and a second capacitor electrode. The second gate electrode, the semiconductor layer, and the second insulating layer have outlines that are coincident with one another in a top view.

Abstract: A flat panel display device includes a pixel circuit provided on a substrate, a pixel wiring, an inspection pad connected to the pixel circuit through the pixel wiring, a main wiring separated from the inspection pad by a gap, and a common electrode covering substantially the entire substrate and electrically connecting the inspection pad to the main wiring.

Abstract: An organic light-emitting display device includes an organic light-emitting device, a thin film transistor (TFT) electrically connected to the organic light-emitting device, and a capacitor electrically connected to the organic light-emitting device, the capacitor including a first electrode layer and a second electrode layer opposite to each other, and a first insulating layer interposed as a single layer between the first electrode layer and the second electrode layer.

Abstract: A thin film transistor (TFT) substrate, an organic light-emitting display apparatus including the TFT substrate, and a method of manufacturing the TFT substrate that enable simple manufacturing processes and a decrease in the interference between a capacitor and other interconnections are disclosed. The TFT substrate may include a substrate, a TFT arranged on the substrate, the TFT including an active layer, a gate electrode, a source electrode, and a drain electrode, a pixel electrode electrically connected to one of the source electrode and the drain electrode, and a capacitor including a lower capacitor electrode and an upper capacitor electrode, the lower capacitor electrode formed from the same material as the active layer and arranged on the same layer as the active layer, and the upper capacitor electrode formed from the same material as the pixel electrode.

Abstract: A thin-film transistor (“TFT”) array substrate includes: a TFT including an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer disposed between the active layer and the gate electrode, and a second insulating layer disposed between the gate electrode, and the source and drain electrode; a pixel electrode including a transparent conductive oxide and disposed in an opening defined in the second insulating layer; a capacitor including a first electrode disposed on a layer on which the active layer is disposed, and a second electrode disposed on a layer on which the gate electrode is disposed; a pad electrode disposed on the second insulating layer and including a material substantially the same as a material in the source electrode and the drain electrode; a first protective layer disposed on the pad electrode; and a second protective layer disposed on the first protective layer.

Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.

Abstract: A semiconductor device includes a first insulating film formed on a memory cell region of the semiconductor substrate, a first polysilicon layer formed on the first insulating film, and memory cell transistors formed on the first polysilicon layer, each including a charge storage layer, an inter-electrode insulating film and a control gate electrode. The semiconductor device further includes a laminated structure formed on a peripheral circuit region of the semiconductor substrate that includes a second insulating film, a second polysilicon layer, a third insulating film, a third polysilicon layer, a fourth insulating film formed from the same material as a material of the inter-electrode insulating film, and a first electrode formed from the same material as a material of the control gate electrode. The third polysilicon layer, the fourth insulating film, and the first electrode are arranged in the peripheral circuit region to form a capacitance element.

Abstract: A pixel structure of a display panel includes a gate line, a first data line, a second data line, a first active switching device, a second active switching device, a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected to the first active switching device. The first pixel electrode includes a first main electrode disposed adjacent to one side of the first data line, and a second main electrode disposed adjacent to one side of the second data line. The second pixel electrode is electrically connected to the second active switching device. The second pixel electrode is disposed between the first main electrode and the second main electrode of the first pixel electrode.

Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract: A display device having fewer alignment defects is provided. A display device having a high aperture ratio and including a capacitor with increased charge capacity is provided. A display device having a high aperture ratio, including a capacitor with large charge capacity, and having fewer alignment defects is provided. The display device includes a pixel electrode, a transistor including a light-transmitting semiconductor layer connected to the pixel electrode, and a capacitor, a scan line, and a data line connected to the transistor. The transistor is arranged to overlap with the scan line. One of electrodes of the capacitor is formed on the same surface where the semiconductor layer is formed, and is formed in a region divided by the scan lines and the data lines. The other of the electrodes of the capacitor is a pixel electrode. The pixel electrode extends so as to intersect with the scan line.

Abstract: The present disclosure relates to the field of organic light-emitting display, and provides a pixel circuit, a driving method thereof, an organic light-emitting display panel and a display apparatus, comprising a driving transistor, a first storage capacitor, a collecting unit, a writing unit and a light-emitting unit; wherein, the collecting unit is used. for collecting the threshold voltage of the driving transistor and storing the threshold voltage into the first storage capacitor, under the control of the first scan signal; the writing unit is used for storing the data voltage inputted from the input terminal for the data voltage under the control of the second scan signal; and the light-emitting unit is used for emitting lights, driven by the data voltage and a voltage inputted from the input terminal for the controllable low voltage, under the control of the light-emitting control signal.

Abstract: Adverse effects of variation in threshold voltage are reduced. In a semiconductor device, electric charge is accumulated in a capacitor provided between a gate and a source of a transistor, and then, the electric charge accumulated in the capacitor is discharged; thus, the threshold voltage of the transistor is obtained. After that, current flows to a load. In the semiconductor device, the potential of one terminal of the capacitor is set higher than the potential of a source line, and the potential of the source line is set lower than the potential of a power supply line and the cathode side potential of the load.

Abstract: A method of manufacturing an organic light emitting diode (OLED) display includes forming an upper electrode power source line outside of a pixel area over a substrate, forming a lower electrode in the pixel area, forming at least one layer of an organic material layer in the pixel area and areas outside of the pixel area, forming an upper electrode in the pixel area, selectively removing portions of the organic material layer that are exposed outside of the upper electrode, thereby exposing the upper electrode power source line, and coating a conductive material between the upper electrode and the upper electrode power source line in a normal pressure condition such that the conductive material overlaps the upper electrode and the upper electrode power source line, thereby forming a connection portion.

Abstract: A pixel structure including a substrate, an active device located on the substrate, a second reflective pattern, and a third reflective pattern is provided. The active device includes a gate, a channel, a source, and a drain. The source and the drain are connected to the channel and are separated from each other. The channel and the gate are stacked in a thickness direction. The second reflective pattern and the third reflective pattern are electrically connected to the drain of the active device. The second reflective pattern has second contact openings. The third reflective pattern is stacked on the second reflective pattern and covers the second contact openings of the second reflective pattern. The second reflective pattern is located between the third reflective pattern and the substrate. Moreover, other kinds of pixel structures are also provided.

Abstract: A pixel structure includes a first conductive layer, a stacked layer, and a third conductive layer. The first conductive layer includes a first gate, a first scan line connected to the first gate, and a capacitor electrode separated from the first scan line. The stacked layer includes a semiconductor layer and a second conductive layer. The second conductive layer includes a data line, a first source connected to the data line, a second source, a first drain, a second drain, a connecting electrode connected to the second source and electrically connected to the first drain, and a coupling electrode connected to the second drain. The third conductive layer includes a first pixel electrode connected to the first drain, a second pixel electrode electrically connected to the connecting electrode, a first extending portion, and a second extending portion.

Abstract: A system suppresses a variation in luminance for each pixel by appropriately suppressing a variation in the parasitic capacitance of a sampling transistor.

Abstract: A thin film transistor array substrate having a pixel arrangement structure includes a first sub-pixel for displaying a first color and a second sub-pixel for displaying a second color alternately located in a first column, and a third sub-pixel for displaying a third color in a second column adjacent to the first column, and via holes of the first through third sub-pixels in a same row are at different positions.

Abstract: Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

Abstract: A display device includes a pixel array portion and a driving portion for driving the pixel array portion. The pixel array portion includes row scanning lines, column signal lines, and pixels arranged in a matrix form at intersections of the scanning lines and the signal lines. The driving portion includes a write scanner for supplying a control signal to each of the scanning lines by sequentially scanning the scanning lines in each field and a signal selector for supplying a video signal to each of the signal lines in synchronization with the sequential scanning. Each pixel includes a drive transistor for supplying driving current to the light-emitting element in accordance with the video signal stored in a storage capacitor.

Abstract: The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring.

Abstract: A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate.

Abstract: In an organic light emitting diode (OLED) display and a manufacturing method, an organic light emitting diode (OLED) display includes: a substrate; a semiconductor layer pattern formed on the substrate and including a first capacitor electrode; a gate insulating layer covering the semiconductor layer pattern; a first conductive layer pattern formed on the gate insulating layer and including a second capacitor electrode having at least a portion overlapping the first capacitor electrode; an interlayer insulating layer having a capacitor opening exposing a portion of the second capacitor electrode and covering the second capacitor electrode; and a second conductive layer pattern formed on the interlayer insulating layer, wherein the capacitor opening includes a first transverse side wall parallel to and overlapping the second capacitor electrode, a second transverse side wall parallel to and not overlapping the second capacitor electrode, and a longitudinal side wall connecting the first transverse side wall an

Abstract: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.

Abstract: An organic light-emitting display device includes a capacitor lower electrode that includes a semiconductor material doped with ion impurities. A first insulating layer covers an active layer and the capacitor lower electrode. A gate electrode includes a gate lower electrode formed of a transparent conductive material and a gate upper electrode formed of metal. A pixel electrode is electrically connected to the thin film transistor. A capacitor upper electrode is at the same level as the pixel electrode. An etch block layer is formed between the first insulating layer and the capacitor upper electrode. Source and drain electrodes are electrically connected to the active layer. A second insulating layer has an opening completely exposing the capacitor upper electrode. A third insulating layer exposes the pixel electrode. An intermediate layer includes an emissive layer. An opposite electrode faces the pixel electrode.

Abstract: A thin film transistor array substrate includes a plurality of pixels, each of the pixels including a capacitor comprising a first electrode, and a second electrode located above the first electrode, a data line extending in a first direction, configured to provide a data signal, located above the capacitor, and overlapping a part of the capacitor, and a driving voltage line configured to supply a driving voltage, located between the capacitor and the data line, and comprising a first line extending in the first direction, and a second line extending in a second direction substantially perpendicular to the first direction.

Abstract: An array substrate disclosed herein includes: scanning signal lines (16i and 16j); data signal lines (15x, 15y, 15X, and 15Y) to each of which a data signal is supplied; a first pixel region column; and a second pixel region column adjacent to the first pixel region column, each of the first and second pixel region columns including pixel regions, wherein: two data signal lines corresponding to the first pixel region column are provided, two data signal lines corresponding to the second pixel region column are provided, a gap between two adjacent data signal lines (15y and 15X) is provided, one of the two adjacent data signal lines being corresponding to the first pixel region column, and the other of the two adjacent data signal lines being corresponding to the second pixel region column; and a gap line 41 is provided within the gap, a Vcom signal being supplied to the gap line 41.

Abstract: A display unit is provided with pixels arranged in a matrix form, and each of the pixels includes: an electro-optical device; a transistor; and a capacitor formed by providing a metal layer between a first semiconductor layer and a second semiconductor layer, the first semiconductor layer forming a source region and a drain region of the transistor, and the second semiconductor layer formed in a layer different from a layer where the first semiconductor layer is formed, in which a voltage allowing a capacity value of the capacitor to be increased is applied to the metal layer during light emission from the electro-optical device.

Abstract: A semiconductor device comprises a thin film transistor provided over a substrate having an insulating surface, and an electrode penetrating the substrate. The thin film transistor is provided between a first structural body and a second structural body, which has a higher rigidity than the first structural body, which serve as protectors because the structural bodies have resistance to a pressing force such as a tip of a pen or bending stress applied from outside so malfunction due to the pressing force and the bending stress can be prevented.

Abstract: The present invention provides a manufacturing method of array substrate, which comprises: substrate; source, drain, driving electrode, and first capacitance electrode being formed on substrate; a first dielectric layer being formed to cover source, drain, driving electrode, and first capacitance electrode; first dielectric layer comprising first section covering first capacitance and second section covering the driving electrode; second section being thicker than first section; second capacitance electrode being formed on the first section of the first dielectric layer; first capacitor being formed with second capacitance electrode, first capacitance electrode, and first dielectric layer in between. Through this invention, the glue sealing of display device with present invention of array substrate is more effective.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.

Abstract: Embodiments of the present invention provide a method of manufacturing a pixel unit, in which only a single patterning process and a single doping process are performed on a polysilicon layer so as to form heavily doped regions of a thin film transistor and a lower electrode of a storage capacitor respectively, thereby reducing numbers of photolithography and masking processes required to manufacture a LTPS-TFT, shortening time periods for development and mass production, and reducing complexity of processes as well as monitoring difficulty, and decreasing the production cost. The present invention further provides a pixel unit manufactured according to the method, an array substrate and a display device including the same.

Abstract: It is an object to provide a liquid crystal display device including a thin film transistor with high electric characteristics and high reliability. As for a liquid crystal display device including an inverted staggered thin film transistor of a channel stop type, the inverted staggered thin film transistor includes a gate electrode, a gate insulating film over the gate electrode, a microcrystalline semiconductor film including a channel formation region over the gate insulating film, a buffer layer over the microcrystalline semiconductor film, and a channel protective layer which is formed over the buffer layer so as to overlap with the channel formation region of the microcrystalline semiconductor film.

Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Abstract: In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring.

Abstract: There are provided a back plane for a flat panel display and a method of manufacturing the back plane, and more particularly, a back plane for an organic light-emitting display device, which enables front light-emitting, and a method of manufacturing the back plane. The back plane for a flat panel display includes: a substrate; a gate electrode on the substrate; a first capacitor on the substrate, the first capacitor comprising a first electrode, an insulation pattern layer on the first electrode, and a second electrode on the insulation pattern layer; a first insulation layer on the substrate to cover the gate electrode and the first capacitor; an active layer on the first insulation layer to correspond to the gate electrode; and a source electrode and a drain electrode on the substrate to contact a portion of the active layer.

Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.

Abstract: A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.

Abstract: In a display apparatus including a switching transistor, a correction voltage for eliminating an effect of a variation in a characteristic of a driving transistor is stored in a storage capacitor. The switching transistor is disposed between one current terminal of the driving transistor and a light emitting element. The switching transistor turns off during the non-light emission period thereby to electrically disconnect the light emitting element from the one current terminal of the driving transistor thereby preventing a leakage current from flowing through the light emitting element during the period in which the correction unit operates, and thus preventing the correction voltage from having an error due to the leakage current.

Abstract: An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode.

Abstract: A thin film transistor (TFT) array substrate includes a TFT including an active layer, a gate electrode, source and drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer and a third insulating layer between the gate electrode and the source and drain electrodes, the first insulating layer and the second insulating layer extending in the TFT, a pixel electrode including a transparent conductive oxide material, the pixel electrode being on the first insulating layer and the second insulating layer and being connected to the source or drain electrodes via an opening in the third insulating layer, a capacitor including a first electrode on a same layer as the gate electrode and a second electrode on a same layer as the pixel electrode; and a fourth insulating layer covering the source and drain electrodes and exposing the pixel electrode via an opening.

Abstract: A voltage equal to the threshold value of a TFT (106) is held in capacitor unit (109). When a video signal is inputted from a source signal line, the voltage held in the capacitor unit is added thereto and a resultant signal is applied to a gate electrode of the TFT (106). Even when a threshold value is varied for each pixel, each threshold value is held in the capacitor unit (109) for each pixel. Thus, the influence of a variation in threshold value can be eliminated. Further, holding of the threshold value is conducted by only the capacitor unit (109) and a charge does not move at writing of a video signal so that a voltage between both electrodes is not changed. Thus, it is not influenced by a variation in capacitance value.

Abstract: Disclosed is a method for manufacturing an array substrate, comprising: step A, sequentially forming patterns of a first conduction layer, source and drain electrodes, an active layer, and an insulation layer on one side of the substrate, wherein at least one via hole is provided on the insulation layer; step B, sequentially forming a gate metal layer and a passivation layer on the substrate on which the first conduction layer, the source and drain electrodes, the active layer, and the insulation layer have been formed, wherein the gate metal layer comprises a gate electrode and a gate line, and the gate metal layer is coupled to the first conduction layer through the at least one via hole to form a path for dispersing static electricity.