Heat Dissipating Element Has High Thermal Conductivity Insert (e.g., Copper Slug In Aluminum Heat Sink) Patents (Class 257/720)
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Publication number: 20090309214Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.Type: ApplicationFiled: August 24, 2009Publication date: December 17, 2009Inventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
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Publication number: 20090309215Abstract: A semiconductor module (10) includes a heat sink (1), an electronic component (2), a semiconductor device (3), and a thermally-conductive sheet member (4). The thermally-conductive sheet member (4) covers a part of the semiconductor device (3) and has a lower part (4b) and a side part (4c). The lower part (4b) is in contact with a mounting face (11a) of the heat sink (1). The side part (4c) extends from the lower part (4b) and covers a first side surface (3c) of the semiconductor device (3). The electronic component (2) is disposed across the side part (4c) of the thermally-conductive sheet member (4) from the semiconductor device (3).Type: ApplicationFiled: September 13, 2007Publication date: December 17, 2009Inventor: Makoto Kitabatake
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Patent number: 7629682Abstract: A wafer level package including a semiconductor chip having a plurality of bonding pads on a front surface thereof; a lower insulation layer formed on the semiconductor chip to expose the bonding pads; re-distribution lines formed on the lower insulation layer to be connected to the bonding pads at first ends thereof; an upper insulation layer formed on the lower insulation layer including the re-distribution lines, with portions of the re-distribution lines exposed; solder balls attached to the exposed portions of the re-distribution lines; and a cap covering a rear surface of the semiconductor chip.Type: GrantFiled: December 29, 2006Date of Patent: December 8, 2009Assignee: Hynix Semiconductor Inc.Inventors: Seung Taek Yang, Qwan Ho Chung
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Patent number: 7629684Abstract: An electronic package which includes a substrate (e.g., a chip carrier substrate or a PCB), an electronic component (e.g., a semiconductor chip), a heatsink and a thermal interposer for effectively transferring heat from the chip to the heatsink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.Type: GrantFiled: April 4, 2006Date of Patent: December 8, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: David J. Alcoe, Varaprasad V. Calmidi
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Patent number: 7626259Abstract: Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs.Type: GrantFiled: October 24, 2008Date of Patent: December 1, 2009Assignee: Entorian Technologies, LPInventors: James Douglas Wehrly, Jr., James Wilder, Paul Goodwin, Mark Wolfe
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Patent number: 7622803Abstract: An assembly for supporting a substrate during vacuum processing operations includes a thermally conductive heat sink tray including at least one wafer pocket recessed therein, and a thermally conductive heat sink carrier in the at least one wafer pocket. The heat sink carrier includes a first surface in contact with a surface within the at least one wafer pocket and a second surface opposite the first surface. A heat sink is affixed to the second surface of the heat sink carrier.Type: GrantFiled: August 24, 2006Date of Patent: November 24, 2009Assignee: Cree, Inc.Inventors: Winston T. Parker, Van Mieczowski, Jim Wood, Daniel Cronin, David Emerson
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Patent number: 7615862Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure.Type: GrantFiled: August 19, 2005Date of Patent: November 10, 2009Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Cheng-Hsu Hsiao
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Publication number: 20090273062Abstract: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.Type: ApplicationFiled: July 6, 2009Publication date: November 5, 2009Inventors: Virgil Cotoco Ararao, Il Kwon Shim, Seng Guan Chow, Sheila Marie L. Alvarez
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Patent number: 7612446Abstract: A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottomType: GrantFiled: November 22, 2006Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Hien P. Dang, Vinod Kamath, Vijayeshwar D. Khanna, Gerard McVicker, Sri M. Sri-Jayantha, Jung H. Yoon
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Patent number: 7612448Abstract: A power module includes a power semiconductor, a non-power semiconductor, one resin substrate, and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device is disposed in order to cool the power semiconductor.Type: GrantFiled: December 1, 2005Date of Patent: November 3, 2009Assignee: Daikin Industries, Ltd.Inventors: Junichi Teraki, Mitsuhiro Tanaka
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Patent number: 7608923Abstract: A package module is provided. The package module includes a substrate having a surface including a die region. A die is disposed in the die region of the surface on the substrate. A flexible heat spreader conformally covers the surface of the substrate and the die. The invention also discloses an electronic device with the package module.Type: GrantFiled: October 12, 2007Date of Patent: October 27, 2009Assignee: Via Technologies, Inc.Inventor: Chi-Hsing Hsu
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Patent number: 7608924Abstract: A plurality of direct die cooled semiconductor power device packages are vertically stacked with both coolant and electrical interfacing to form a liquid cooled power electronic circuit. The packages are individually identical, and selectively oriented prior to stacking in order to form the desired circuit connections and laterally stagger the package leads.Type: GrantFiled: May 3, 2007Date of Patent: October 27, 2009Assignee: Delphi Technologies, Inc.Inventors: Bruce A. Myers, Joseph M. Ratell
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Patent number: 7602060Abstract: A microelectronic package with enhanced thermal management using an embedded heat spreader is disclosed. The microelectronic package comprises a die mounted on a substrate, a thermal interface material disposed in thermal conductive communication with the die and a heat spreader disposed in thermal conductive communication with the thermal interface material. A mold material is provided to enclose the die and the thermal interface material, and partially embedding the heat spreader to expose at least a surface of the heat spreader to an ambient environment. The heat spreader may include an anchor portion to reinforce coupling of the heat spreader to the mold material. If and when required, the heat spreader may be coupled in thermal communication with an external heat sink.Type: GrantFiled: June 25, 2007Date of Patent: October 13, 2009Assignee: Intel CorporationInventor: Kean Hock Yeh
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Patent number: 7595540Abstract: A semiconductor device including a package (2) having a plurality of wall portions (9a) and a plurality of conductor portions (4), a semiconductor element such as a solid-state image pickup device (1) mounted in an internal space of the base, thin metal wires (5) electrically connecting the semiconductor element and the conductor portions (4) between the wall portions (9a), a resin sealing material (7) implanted in the spaces between the wall portions (9a), and a closing member such as a cover glass (6). The region for connecting the thin metal wires (5) and the wall portion (9a) region overlap each other, so that the device can be reduced in size and in height. The cover glass (6) can not move easily from the correct position because the wall portions (9a) serve as supporting columns, thereby improving the yield.Type: GrantFiled: July 18, 2006Date of Patent: September 29, 2009Assignee: Panasonic CorporationInventors: Toshiyuki Fukuda, Eizou Fujii, Yutaka Fukai, Yutaka Harada, Kiyokazu Itoi
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Patent number: 7589401Abstract: A hermetically sealed package for electronic circuit components includes a generally hollow, titanium body, having a reduced thickness bottom wall/floor, whose interior surface is laminated with a relatively low mass, insert, upon which electronic circuit components are mounted. The insert has a high thermal conductivity and a low coefficient of thermal expansion, approximate to that of the housing body.Type: GrantFiled: August 9, 2006Date of Patent: September 15, 2009Assignees: SRI Hermetics Inc., H-Tech, LLCInventor: Edward Allen Taylor
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Patent number: 7586191Abstract: An integrated circuit apparatus with heat removal has an electrical interconnection network. The electrical interconnection network has a plurality of electrically and thermally conductive vias in electrical communication with terminals of at least one semiconductor device. An electrically insulating heat spreader is chemically bonded to each of the vias at an upper layer of the electrical interconnection network. At the upper layer the vias are electrically isolated from each other. In some embodiments the electrically insulating heat spreader is a polycrystalline diamond body with a metallized undersurface. The metallized undersurface may be etched away between vias.Type: GrantFiled: August 11, 2005Date of Patent: September 8, 2009Inventors: David R. Hall, H. Tracy Hall, Paul Moody, Scott Dahlgren, Marshall Soares
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Patent number: 7582959Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).Type: GrantFiled: March 11, 2005Date of Patent: September 1, 2009Assignee: Panasonic CorporationInventor: Hiroyuki Fukusako
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Patent number: 7579686Abstract: The formation of electronic assemblies including a heat spreader coupled to a die through a thermal interface material is described. In one embodiment, the heat spreader includes a surface having a structure extending a distance outward therefrom. The thermal interface material includes a first region having a first thickness and a second region having a second thickness, the first thickness being smaller than the second thickness. The structure extending a distance outward from the heat spreader is positioned on the first region of the thermal interface material. The total of the first thickness of the thermal interface material and the distance the structure extends outward from the surface of the heat spreader is substantially the same as the second thickness. In one aspect of certain embodiments, the first region of the thermal interface material and the structure on the heat spreader are in alignment with a hot spot on the die. Other embodiments are described and claimed.Type: GrantFiled: December 29, 2006Date of Patent: August 25, 2009Assignee: Intel CorporationInventors: Xuejiao Hu, Chia-Pin Chiu
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Patent number: 7579687Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.Type: GrantFiled: January 13, 2006Date of Patent: August 25, 2009Assignee: Entorian Technologies, LPInventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
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Patent number: 7573131Abstract: A printed circuit substrate is disposed on a bottom side of a stiffener. An IC die is disposed on a top side of the stiffener. The die is electrically connected onto the printed circuit substrate by wire bonding through an open slot in the stiffener. The die is not wire bonded to the stiffener. Solder balls are attached on a bottom side of the substrate and electrically connected to ground bond fingers of the substrate, and also are directly attached to solderable pads on the bottom side of the stiffener through open holes or plated through-holes on the substrate, so as to have the stiffener function as a ground plane and as a heat sink for power dissipation.Type: GrantFiled: October 27, 2006Date of Patent: August 11, 2009Assignee: Compass Technology Co., Ltd.Inventors: Cheng Qiang Cui, Kai C. Ng, Chee Wah Cheung
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Patent number: 7564124Abstract: A semiconductor package including stacked packages is disclosed. The semiconductor die package includes a first heat sink structure, a first semiconductor die attached to the first heat sink structure and having a first exterior surface, an intermediate conductive element attached to the first semiconductor die, a second semiconductor die attached to the second heat sink structure, and a second heat sink structure attached to the second semiconductor die and comprising a second exterior surface. A molding material is disposed around the first and second semiconductor dice, where the molding material exposes the first exterior surface of the first heat sink structure and exposes the second exterior surface of the second heat sink structure.Type: GrantFiled: August 29, 2006Date of Patent: July 21, 2009Assignee: Fairchild Semiconductor CorporationInventors: SangDo Lee, Tiburcio A. Maldo
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Patent number: 7564129Abstract: A power semiconductor module according to the present invention includes: a planar base plate having a plurality of insulated substrates soldered on the top surface, the insulated substrates each having power semiconductor elements to be cooled mounted thereon; a plurality of radiation fins projecting from the bottom surface side of the base plate; and a peripheral wall projecting from the bottom surface side of the base plate so as to surround the radiation fins, the projecting length of the radiation fins is less than or equal to that of the peripheral wall, and the peripheral wall has end surfaces present in the same plane.Type: GrantFiled: March 24, 2008Date of Patent: July 21, 2009Assignee: Nichicon CorporationInventors: Raita Nakanishi, Toshiaki Kawamura
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Patent number: 7557438Abstract: A stacked die package includes a substrate (210, 310), a first die (220, 320) above the substrate, a spacer (230, 330) above the first die, a second die (240, 340) above the spacer, and a mold compound (250, 370) disposed around at least a portion of the first die, the spacer, and the second die. The spacer includes a heat transfer conduit (231, 331, 333, 351, 353) representing a path of lower overall thermal resistance than that offered by the mold compound itself. The heat transfer path created by the heat transfer conduit may result in better thermal performance, higher power dissipation rates, and/or lower operating temperatures for the stacked die package.Type: GrantFiled: April 27, 2006Date of Patent: July 7, 2009Assignee: Intel CorporationInventors: Gregory M. Chrysler, Rajashree Baskaran
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Patent number: 7557442Abstract: A power semiconductor arrangement has an electrically insulating and thermally conductive substrate, which is provided with structured metallization on at least one side, a cooling device which is in thermal contact with the other side of the substrate, at least one semiconductor component which is arranged on the substrate and is electrically connected to the structured metallization, an entirely or partially electrically insulating film which is arranged at least on that side of the substrate at which the at least one semiconductor component is placed, and which is laminated without any cavities onto the substrate including or excluding the at least one semiconductor component, and a contact-pressure device which exerts a force on the substrate locally and via the at least one semiconductor component such that the substrate is pressed against the cooling device.Type: GrantFiled: April 15, 2005Date of Patent: July 7, 2009Assignee: Infineon Technologies AGInventor: Thomas Licht
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Publication number: 20090166852Abstract: A method comprises providing a layer of nano particles between a semiconductor die and a slug; and sintering the layer of nano particles to provide thermal interface material to bond the semiconductor die to a heat spreader formed by the slug. The sintering temperature of the nano particles is around 50° C. to around 200° C.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventor: Chuan Hu
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Patent number: 7554179Abstract: A multi-leadframe semiconductor package and method of manufacture includes a first leadframe having a die pad and a plurality of contact leads around the periphery of the die pad. A die is attached to the die pad and electrically connected to the plurality of contact leads. A heat spreader leadframe having a heat spreader and a plurality of terminal leads around the periphery of the heat spreader is provided. The die pad is attached to the heat spreader, and the plurality of contact leads is attached to the plurality of terminal leads.Type: GrantFiled: February 7, 2005Date of Patent: June 30, 2009Assignee: Stats Chippac Ltd.Inventors: Il Kwon Shim, Seng Guan Chow, Jeffrey D. Punzalan, Pandi Chelvam Marimuthu
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Patent number: 7554808Abstract: An apparatus may include a thermally-conductive heat sink core having at least one surface, a solid-state heat pump including a first surface and a second surface, the first surface in contact with the at least one surface of the core, and a thermally-conductive unit in contact with the second surface of the solid-state heat pump. Also included may be a stop in contact with the thermally-conductive unit, disposed at least partially over the first end of a cavity defined by the thermally-conductive unit, and defining an opening, and a fastener passing through the cavity, in contact with the core, and to bias the core toward the stop.Type: GrantFiled: June 22, 2006Date of Patent: June 30, 2009Assignee: Intel CorporationInventors: Brian A. Scott, Paul J. Gwin, Ioan Sauciuc
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Patent number: 7547966Abstract: A power semiconductor module with its thermal resistance and overall size reduced. Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering. Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing. Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders. The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader.Type: GrantFiled: October 17, 2007Date of Patent: June 16, 2009Assignee: Hitachi, Ltd.Inventors: Sunao Funakoshi, Katsumi Ishikawa, Tasao Soga
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Publication number: 20090146295Abstract: The present invention relates to a ceramic substrate having a thermal via passing through the substrate for purposes of radiating heat to the outside, wherein the ceramic substrate has a reinforcing structure that divides the opening of the thermal via into two or more parts, and the height of the reinforcing structure is less than the height of the thermal via.Type: ApplicationFiled: December 11, 2007Publication date: June 11, 2009Inventors: Hidefumi Narita, Akira Inaba
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Publication number: 20090114934Abstract: An LED light emitter with heat sink holder and a method for manufacturing it are both disclosed. The LED light emitter with heat sink holder includes a heat sink holder and at least an LED chip. The heat sink holder is made of high thermal conductivity coefficient, and includes a reflecting mirror having a central portion and a reflecting portion surrounding the central portion. A normal of a top surface of the reflecting portion forms an acute angle relative to a normal of a top surface of the central portion. The LED chip is unitarily connected with a top surface of the central portion, and an electrode unit connecting with and Ohmic contacting the light emitting film for supplying power for the light emitting film. The LED light emitter with heat sink holder improves heat dissipation and working duration.Type: ApplicationFiled: January 25, 2008Publication date: May 7, 2009Inventors: Ray-Hua Horng, Dong-Sing Wuu, Cheng-Chung Chiang, Hsiang-Yun Hsiao, Tsang-Lin Hsu, Heng-I Lin
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Patent number: 7528413Abstract: This invention relates to a high thermal conductivity composite material which comprises diamond particles and a copper matrix useful as electronic heat sinks for electronics parts, particularly for semiconductor lasers, high performance MPUs (micro-processing units), etc., also to a process for the production of the same and a heat sink using the same. According to the high thermal conductivity diamond sintered compact of the present invention, in particular, there can be provided a heat sink having a high thermal conductivity as well as matching of thermal expansions, most suitable for mounting a large sized and high thermal load semiconductor chip, for example, high output semiconductor lasers, high performance MPU, etc. Furthermore, the properties such as thermal conductivity and thermal expansion can freely be controlled, so it is possible to select the most suitable heat sink depending upon the features and designs of elements to be mounted.Type: GrantFiled: October 16, 2002Date of Patent: May 5, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsuhito Yoshida, Hideaki Morigami, Takahiro Awaji, Tetsuo Nakai
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Patent number: 7528483Abstract: A cooling system for a semiconductor substrate includes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.Type: GrantFiled: November 9, 2006Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Howard Hao Chen, Louis L. Hsu, Joseph F. Shepard, Jr.
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Patent number: 7521794Abstract: A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the device, and methods of fabricating the device and package are provided. In one embodiment, the semiconductor device comprises a thick thermally conductive plane (e.g., copper plane) mounted on a thin support substrate and interfaced with a die. Thermally conductive via interconnects extending through the substrate conduct heat generated by the die from the conductive plane to conductive balls mounted on traces on the opposing side of the substrate. In another embodiment, the semiconductor devices comprises a thick thermally conductive plane (e.g., copper foil) sandwiched between insulative layers, with signal planes (e.g., traces, bonding pads) disposed on the insulative layers, a die mounted on a first signal plane, and solder balls mounted on bonding pads of a second signal plane.Type: GrantFiled: August 31, 2006Date of Patent: April 21, 2009Assignee: Micron Technology, Inc.Inventors: Pak Hong Yee, Teck Kheng Lee
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Patent number: 7521789Abstract: An electrical assembly, comprising a heat producing semiconductor device supported on a first major surface of a direct bond metal substrate that has a set of heat sink protrusions supported by its second major surface. In one preferred embodiment the heat sink protrusions are made of the same metal as is used in the direct bond copper.Type: GrantFiled: December 18, 2004Date of Patent: April 21, 2009Assignee: Rinehart Motion Systems, LLCInventors: Lawrence E. Rinehart, Guillermo L. Romero
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Patent number: 7521791Abstract: An apparatus (100) is provided for dispersing heat from an integrated circuit (202) to a heat sink (404). The apparatus (100) is formed on a nonconductive body (102) having at least two conductive surfaces (110, 112) disposed thereon. One of the conductive surfaces (110) is reflowed to a heat generating lead of the integrated circuit (202), and the other conductive surface (112) provides a surface for contacting a heat sink (404). The apparatus (100) and integrated circuit provide a package (200) which can be tape and reeled (300) for easy mounting to a printed circuit board (402) of a communication device (400).Type: GrantFiled: March 8, 2006Date of Patent: April 21, 2009Assignee: Motorola, Inc.Inventors: Justin R. Wodrich, Michael S. Beard, Hal R. Canter, Anbuselvan Kuppusamy, Zalman Schwartzman, James L. Stephens, Kathleen Farrell, legal representative, Kevin C. Farrell
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Patent number: 7518233Abstract: A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.Type: GrantFiled: June 9, 2000Date of Patent: April 14, 2009Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.Inventors: Kouichi Takahashi, Kenichi Kasai, Takahiro Daikoku, Takayuki Uda, Toshitada Netsu, Takeshi Yamaguchi, Takahiko Matsushita, Osamu Maruyama
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Patent number: 7514782Abstract: An objective is to provide a reliability-improved semiconductor device in which heat radiation characteristics are superior, and warpage of the semiconductor device occurring due to heat generation of a semiconductor chip or to varying of the usage environment is also suppressed. The semiconductor device is provided that includes a thermal-conductive sheet 3 formed on a base board 4, including thermal-conductive resin 6, a heat sink 2 provided on the base board 4 through the thermal-conductive sheet 3, a semiconductor chip 1 mounted on the heat sink 2, and a ceramic-embedded region 31 selectively provided in a region of the thermal-conductive sheet 3 under the semiconductor chip 1, including a ceramic component 5. In this semiconductor device, superior thermal conductivity can be ensured, and warpage and peeling in the semiconductor device occurring due to heat generation of the semiconductor chip or to varying of the usage environment can also be reduced.Type: GrantFiled: April 5, 2007Date of Patent: April 7, 2009Assignee: Mitsubishi Electric CorporationInventors: Seiki Hiramatsu, Kei Yamamoto, Atsuko Fujino, Hiromi Ito
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Publication number: 20090079063Abstract: A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Gregory M. Chrysler, Ravi V. Mahajan, Chia-Pin Chiu
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Patent number: 7508066Abstract: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.Type: GrantFiled: November 3, 2005Date of Patent: March 24, 2009Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Chih-Ming Huang
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Patent number: 7504670Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.Type: GrantFiled: June 7, 2006Date of Patent: March 17, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Satoshi Shiraishi, Yoichi Kazama
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Patent number: 7505109Abstract: The heat dissipation structure of the backlight module of the present invention comprises a circuit board, a heat-conductive element (such as thermally conductive glue) and a light-emitting diode (LED) chip, wherein the circuit board has an electric circuit layer and a heat conductive layer respectively formed on two opposite surfaces thereof. The circuit board has a plurality of through holes penetrating through the electric circuit layer and the heat-conductive layer of the circuit board, wherein each of the through holes is filled with heat-conductive material. The heat-conductive element is placed on the circuit layer and covers the through holes, and the LED chip is disposed on the heat-conductive element and is electrically connected to the electric circuit layer.Type: GrantFiled: June 28, 2006Date of Patent: March 17, 2009Assignee: AU Optronics CorporationInventors: Chi-Chen Cheng, Ya-Ting Ho, Meng-Chai Wu
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Patent number: 7502398Abstract: A directly cooled diode-laser bar package includes a diode-laser bar bonded to a heat-sink. The operating temperature of the diode-laser bar can be selectively varied by varying the thermal impedance of the heat-sink in or near a region of the heat-sink on which the diode-laser bar is bonded. The thermal impedance is selectively varied by varying the insertion depth of screws inserted into corresponding screw holes extending into the heat-sink close to or immediately adjacent the region on which the diode-laser bar is bonded.Type: GrantFiled: November 2, 2006Date of Patent: March 10, 2009Assignee: Coherent, Inc.Inventors: David Schleuning, C. David Nabors, R. Russel Austin
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Patent number: 7479695Abstract: An assembly comprises a stiffener, a circuit substrate and an integrated circuit (IC) chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers the first region, while the IC chip overlies at least a portion of each of the first and second regions. Moreover, the assembly further comprises a plurality of first solder bumps and a plurality of second solder bumps. The first solder bumps contact both the IC chip and the circuit substrate. The second solder bumps are larger than the first solder bumps, contact the IC chip and are disposed above the second region of the stiffener.Type: GrantFiled: March 14, 2006Date of Patent: January 20, 2009Assignee: Agere Systems Inc.Inventors: Mark Adam Bachman, David L. Crouthamel
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Patent number: 7476967Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.Type: GrantFiled: February 22, 2006Date of Patent: January 13, 2009Assignee: Intel CorporationInventor: Valery M. Dubin
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Publication number: 20090008773Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.Type: ApplicationFiled: July 2, 2008Publication date: January 8, 2009Applicant: JDS Uniphase CorporationInventors: Andre Wong, Sukbhir Bajwa
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Patent number: 7464462Abstract: A method for forming a heat spreading apparatus for semiconductor devices is disclosed. The method includes extruding a frame material to form multiple individual cells including fillable openings within the frame material; filling a first group of the individual cells with one or more high thermal conductivity materials; filling at least a second group of the individual cells with one or more materials of lower thermal conductivity than in the first group of the individual cells; and implementing a reflowing process following filling the multiple individual cells so as to infiltrate the materials within the individual cells, wherein defined walls of the frame material remain following the reflowing.Type: GrantFiled: October 15, 2007Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: David L. Edwards, Thomas Fleischman, Paul A. Zucco
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Patent number: 7456052Abstract: Apparatus and system, as well as fabrication methods therefor, may include a thermal intermediate structure comprised of a plurality of carbon nanotubes some of which have organic moieties attached thereto to tether the nanotubes to at least one of a die and a heat sink. The organic moieties include thiol linkers and amide linkers.Type: GrantFiled: December 30, 2003Date of Patent: November 25, 2008Assignee: Intel CorporationInventors: Bryan M. White, Paul A. Koning, Yuegang Zhang, C. Michael Garner
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Patent number: 7446412Abstract: Some aspects include a heat sink base, an upper metal cladded to an upper surface of the heat sink base, the upper metal defining at least one groove, and a heat sink fin disposed in the groove and secured to the upper metal. Some aspects may also include a lower metal cladded to a lower surface of the heat sink base, and a pedestal secured to the lower cladding.Type: GrantFiled: March 28, 2006Date of Patent: November 4, 2008Assignee: Intel CorporationInventor: Paul J Gwin
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Patent number: 7446407Abstract: A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.Type: GrantFiled: August 31, 2005Date of Patent: November 4, 2008Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Chun-Hung Lin, Geng-Shin Shen
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Patent number: 7446408Abstract: A package is provided for a semiconductor device including a semiconductor device support substrate having at least one interconnect metal therein connectible to a ground and having at least one opening exposing the surface of the interconnect metal. A heat sink has elastic means integral therewith for cooperating with the opening to position and secure the heat sink to the semiconductor support substrate.Type: GrantFiled: June 16, 2003Date of Patent: November 4, 2008Assignee: ST Assembly Test Services Pte LtdInventors: Il Kwon Shim, Seng Guan Chow, Gerry Balanon