Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a front surface and a back surface, forming first and second through holes in the substrate, filling the first and second through holes with metals, forming a subassembly on the front surface of the substrate. The subassembly includes a first metal layer and a second metal layer insulated from the first metal layer, the first metal layer is electrically connected to the metal filled in the first through hole, the second metal layer is electrically connected to the metal filled in the second through hole, and a metal connection pad is on the substrate and surrounds the subassembly. The method also includes providing a cap assembly including a metal connection member, bonding the cap assembly to the subassembly, and thinning the back surface of the substrate to expose the first and second through holes.

Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.

Abstract: A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer.

Abstract: A system includes a magnetic field sensor arrangement and a controller. The magnetic field sensor arrangement includes a first sensor chip having an integrated circuit differential magnetic field sensor circuit configured to generate a first output signal comprising first signal pulses, a second sensor chip having an integrated second differential magnetic field sensor circuit configured to generate a second output signal comprising second signal pulses, and at least one output signal terminal configured to output the first and the second output signals. The controller receives the first and the second signal pulses from the at least one output signal terminal, evaluates the first and the second signal pulses, and detects an error of an operation of the magnetic field sensor arrangement in response to the first and the second signal pulses not satisfying an expected output pattern of the first and the second signal pulses.

Abstract: A module (101) includes a substrate (1) having a main surface (1a) and a conductor column (4) disposed on the main surface (1a). The conductor column (4) includes a conductor column body (4a) and an overhanging part (4b) overhanging from an outer periphery of the conductor column body (4a) in a middle of a height direction of the conductor column body (4a).

Abstract: An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.

Abstract: A semiconductor package that effectively controls heat generated from a semiconductor chip is provided. A semiconductor device with improved product reliability and performance is provided.

Abstract: The present disclosure provides an image capturing assembly and its packaging method, a lens module and an electronic device. The packaging method includes: providing a photosensitive chip; mounting an optical filter on the photosensitive chip; providing a carrier substrate and temporarily bonding the photosensitive chip and functional components on the carrier substrate; and forming an encapsulation layer on the carrier substrate and at least between the photosensitive chip and the functional components.

Abstract: An electronic component-embedded substrate includes a first wiring layer, a first electronic component disposed on the first wiring layer, a first insulating material covering at least a portion of each of the first wiring layer and the first electronic component, a second wiring layer disposed on the first insulating material, a second electronic component disposed on the second wiring layer and connected to the first electronic component in an electrical parallel connection, a second insulating material disposed on the first insulating material and covering at least a portion of each of the second wiring layer and the second electronic component, and a first via penetrating through the first insulating material and connecting the first electronic component and the second wiring layer.

Abstract: Discussed are a device for self-assembling semiconductor light-emitting diodes, in which the device includes an assembly chamber having a space for accommodating a fluid; a magnetic field forming part having at least one magnet for applying a magnetic force to the semiconductor light-emitting diodes dispersed in the fluid and a moving part for changing positions of the at least one magnet so that the semiconductor light-emitting diodes move in the fluid; and a substrate chuck having a substrate support part configured to support a substrate, and a vertical moving part for lowering the substrate so that one surface of the substrate is in contact with the fluid in a state in which the substrate is supported by the substrate support part, wherein the vertical moving part provided at the substrate chuck lowers the substrate on to the fluid so that a force of buoyancy by the fluid is applied to the substrate.

Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

Abstract: The present disclosure provides a display device, including a substrate, a plurality of semiconductor light emitting devices arranged on the substrate, a first wiring electrode and a second wiring electrode extended from the semiconductor light emitting devices, respectively, to supply an electric signal to the semiconductor light emitting devices, a plurality of pair electrodes arranged on the substrate to generate an electric field when an electric current is supplied, and provided with first and second pair electrodes formed on an opposite side to the first and second wiring electrodes with respect to the semiconductor light emitting devices, and a dielectric layer formed to cover the pair electrodes, wherein the plurality of pair electrodes are arranged in parallel to each other along a direction.

Abstract: A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test.

Abstract: An electronic apparatus that includes a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on the substrate; a spacer attached to the substrate and situated between the first and second semiconductor chips; a lid mounted on the substrate and enclosing the first and second semiconductor chips and the spacer, the spacer having an adhesive material adhesively attached to the lid; and underfill material underneath the first and second semiconductor chips, underneath the spacer and between the spacer and the first and second semiconductor chips.

Abstract: A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

Abstract: The present disclosure provides a camera assembly and a packaging method thereof, a lens module, and an electronic device.

Abstract: A package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure includes a composite dielectric layer, a plurality of under bump metallization patterns, a dielectric layer, and a plurality of conductive patterns. The composite dielectric layer includes a first sub-layer and a second sub-layer stacked on the first sub-layer. The under bump metallization patterns are over the first sub-layer and penetrate through the composite dielectric layer. The dielectric layer is disposed on the second sub-layer of the composite dielectric layer. The conductive patterns are embedded in the dielectric layer. The die and the conductive structures are on the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is over the conductive structures, the encapsulant, and the die.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.

Abstract: A stack package includes a supporting substrate that supports first and second semiconductor dies. The supporting substrate is disposed on a package substrate and is supported by first and second connection bumps. Redistributed line (RDL) patterns are disposed on the supporting substrate to electrically connect the first semiconductor die to the first and second connection bumps. The second semiconductor dies are connected to the package substrate by bonding wires.

Abstract: Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a substrate, an array of NAND memory cells above the substrate, and a first bonding layer above the array of NAND memory cells. The first bonding layer includes first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer above the first bonding layer and including second bonding contacts, a peripheral circuit and an array of PCM cells above the second bonding layer, and a semiconductor layer above and in contact with the peripheral circuit. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.

Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

Abstract: An electronic medical device is disclosed here. An exemplary embodiment of the medical device includes a printed circuit board assembly, a protective inner shell surrounding at least a portion of the printed circuit board assembly, and an outer shell surrounding at least a portion of the protective inner shell. The printed circuit board assembly has a printed circuit board, electronic components mounted to the printed circuit board, a battery mounted to the printed circuit board, and an interface compatible with a physiological characteristic sensor component. The protective inner shell is formed by overmolding the printed circuit board assembly with a first material having low pressure and low temperature molding properties. The outer shell is formed by overmolding the protective inner shell with a second material that is different than the first material.

Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Abstract: A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.

Abstract: A semiconductor device may include: a first chip, configured to receive a command and an address; and a second chip, configured to receive the command and the address. The first chip may include: a weak cell address storage circuit configured to store a weak cell address; a refresh control circuit configured to generate a refresh address based on the weak cell address, when the second chip is selected by a chip address; and a bank in which a refresh operation is performed by the refresh address.

Abstract: A method includes bonding a plurality of dies to a substrate. A first die of the plurality of dies is larger than a second die of the plurality of dies. The method includes adhering a first stress relief structure to the substrate. A distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method includes adhering a second stress relief structure to the substrate. A distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance. The first stress relief structure is discontinuous with respect to the second stress relief structure.

Abstract: A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes an image sensing element arranged within a substrate. One or more isolation structures are arranged within one or more trenches disposed on opposing sides of the image sensing element. The one or more isolation structures extend from a first surface of the substrate to within the substrate. The one or more isolation structures respectively include a reflective element configured to reflect electromagnetic radiation.

Abstract: A semiconductor device includes: a first chip to restrict current flow in a first direction through a current path; a second chip to restrict the current flow in a second direction opposite to the first direction, through the current path; a wiring having one end connected to the first chip and the other end connected to the second chip, and provided as a part of the current path by relaying the first chip and the second chip; a lead frame having a first lead arranged and fixed with the first chip and a second lead is arranged and fixed with the second chip; and molding resin sealing the first chip, the second chip, the wiring and the lead frame. The wiring is a shunt resistor having a resistive body. The lead frame further has a sense terminal to detect a voltage drop across the resistive body.

Abstract: A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The three-dimensional package structure is applicable to a POL, (Point of Load) converter.

Abstract: An electrical chip includes a plurality of electrical signal processing circuits arranged side by side on a chip board, the electrical signal processing circuits that processes electrical signals transmitted to each of a plurality of lanes for each lane; and a power supply wiring network provided in an area overlapping with each of the plurality of electrical signal processing circuits and including wires formed into a mesh shape for supplying power to each of the plurality of electrical signal processing circuits, wherein the power supply wiring network includes a slit obtained by separating a part of the wires in each area corresponding to a boundary between the lanes.

Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Abstract: A semiconductor package structure includes a conductive trace layer, a semiconductor die over the conductive trace layer, a structure enhancement layer surrounding the semiconductor die, and an encapsulant covering the semiconductor die and the structure enhancement layer. The structure enhancement layer coincides with a mass center plane of the semiconductor package structure. The mass center plane is parallel to a top surface of the semiconductor die. A method for manufacturing the semiconductor package structure is also provided.

Abstract: An ultrasonic fingerprint sensor system of the present disclosure may be provided with a thick electrically nonconductive acoustic layer and thin electrode layer coupled to a piezoelectric layer of an ultrasonic transmitter or transceiver. The thick electrically nonconductive acoustic layer may have a high density or high acoustic impedance value, and may be adjacent to the piezoelectric layer. The thin electrode layer may be divided into electrode segments. The ultrasonic fingerprint sensor system may use flexible or rigid substrates, and may use an ultrasonic transceiver or an ultrasonic transmitter separate from an ultrasonic receiver.

Abstract: A bezel-free display comprises a display substrate and an array of pixels. Pixel rows and pixel columns are separated by row and column distances and connected by row and column lines, respectively. A column driver is electrically connected to each of the column lines and a row driver is electrically connected to each of the row lines. Row-connection lines are electrically connected to each of the row lines or row drivers. In certain embodiments, each pixel in the column of pixels closest to a display substrate edge is spatially separated from the edge by a distance less than or equal to the column distance. At least one row driver is spatially separated from the corresponding row by a distance less than the column or row distance, at least one column driver is spatially separated from the corresponding column by a distance less than the column or row distance, or both.

Abstract: Chip package structures are provided. The chip package structure includes a protection layer and a first chip disposed over the protection layer. The chip package structure further includes a first photosensitive layer formed around sidewalls of the first chip and covering a top surface of the first chip and a second chip disposed over the first photosensitive layer. In addition, the first chip and the second chip are separated by the first photosensitive layer.

Abstract: An electronic component embedded substrate includes a first electronic component; a first insulating material covering at least a portion of the first electronic component; a first wiring layer disposed on one surface of the first insulating material; a second electronic component disposed on the first wiring layer and connected to the first electronic component by the first wiring layer; and a second insulating material covering at least a portion of the second electronic component, wherein the at least a portion of the first electronic component is exposed from the other surface of the first insulating material, opposite to the one surface of the first insulating material.

Abstract: A Microelectromechanical systems (MEMS) structure comprises a MEMS wafer. A MEMS wafer includes a handle wafer with cavities bonded to a device wafer through a dielectric layer disposed between the handle and device wafers. The MEMS wafer also includes a moveable portion of the device wafer suspended over a cavity in the handle wafer. Four methods are described to create two or more enclosures having multiple gas pressure or compositions on a single substrate including, each enclosure containing a moveable portion. The methods include: A. Forming a secondary sealed enclosure, B. Creating multiple ambient enclosures during wafer bonding, C. Creating and breaching an internal gas reservoir, and D. Forming and subsequently sealing a controlled leak/breach into the enclosure.

Abstract: An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.

Abstract: A semiconductor device including one or more semiconductor dice, a lead frame including an array of signal-carrying leads electrically coupled with the semiconductor die, and a power supply connection for the at least one semiconductor die arranged centrally thereof.

Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.

Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.