Abstract: A device including a stack of dies. Each of the dies can have unit stair-step conductive paths of connection features which include through-die via structures and routing structures. The unit stair-step conductive paths of one of the dies can be interconnected to another one of the unit stair-step conductive paths of another one of the dies to form one of a plurality conductive stair-case structures through two or more of the dies. The unit stair-step conductive paths can be connected to reduce signal cross talk between the conductive stair-case structures whereby at least some of the conductive stair-case structures are connected to transmit a same polarity of electrical signals are spatially separated in a dimension that is perpendicular to a major surface of the dies. A method of manufacturing the device is also disclosed.

Abstract: A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

Abstract: The present application discloses a method for fabricating a semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled. method includes providing an active interposer comprising a programmable unit; providing a first logic die and bonding a first side of the active interposer onto the first logic die; providing a first memory die comprising a storage unit; and bonding the first memory die onto a second side of the active interposer, wherein the second side of the active interposer is parallel to the first side of the active interposer.

Abstract: Optical sensor modules and methods of fabrication are described. In an embodiment, an optical component is mounted on a module substrate. In an embodiment, a pillar of stacked wireballs adjacent the optical component is used for vertical connection between the module substrate and a top electrode pad of the optical component.

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Abstract: A first microchip includes holes or sockets along or in a top face or surface of the first microchip and a second microchip includes nodules extending from a edge of the second microchip. The nodules of the second microchip are received in the holes or sockets along or in the top face or surface of the first microchip, whereupon the first and second microchips are positioned transverse or perpendicular to each other.

Abstract: The present application provides a pixel circuit, a display panel, and a temperature compensation method for a display panel. The display panel includes a plurality of pixel units. At least one of the plurality of pixel units includes: a display layer comprising a light emitting element; and a thermoelectric conversion layer comprising a thermoelectric element having a first terminal and a second terminal, wherein the first terminal is disposed adjacent to the light emitting element and in thermal contact with the light emitting element, and the second terminal is disposed away from the light emitting element. The thermoelectric element has a first signal terminal and a second signal terminal, and is configured to generate a temperature difference voltage signal between the first signal terminal and the second signal terminal according to a temperature difference between the first terminal and the second terminal.

Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.

Abstract: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

Abstract: An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network.

Abstract: A semiconductor device disclosed herein may include: a semiconductor element including an electrode on a surface of the semiconductor element; and a terminal bonded to the electrode via a bonding material, wherein the electrode may include a protrusion portion that protrudes toward the terminal and is in contact with the bonding material.

Abstract: A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate. The package has a cap coupled to the non-conductive coupling element through ultrasonic plastic welding. The package protects the dice from an outside environment or external stresses or both. A method is desired to form package to reduce glue overflow defects in the package. Fabrication of the package comprises drilling holes in a substrate; forming trenches in the substrate; forming a non-conductive coupling element in the through holes and the trenches to form a locking mechanism; allowing the non-conductive coupling element to harden and cure; coupling a die or dice to the substrate; and coupling a cap to the non-conductive coupling element to protect the die or dice from an outside environment or external stresses or both.

Abstract: Monolithic multi-dimensional integrated circuits and memory architecture are provided. Exemplary integrated circuits comprise an electronic board having a first side and a second side, a multi-dimensional electronic package having multiple planes, and one or more semiconductor wafers mounted on the first side and the second side of the electronic board and on the multiple planes of the electronic package. Exemplary monolithic multi-dimensional memory architecture comprises one or more tiers, one or more monolithic inter-tier vias spanning the one or more tiers, at least one multiplexer disposed in one of the tiers, and control logic determining whether memory cells are active and which memory cells are active and controlling usage of the memory cells based on such determination. Each tier has a memory cell, and the inter-tier vias act as crossbars in multiple directions. The multiplexer is communicatively coupled to the memory cell in the respective tier.

Abstract: A wireless connection is established between at least two electronic modules (M1, M2) disposed separate from one another in a smartcard having a coupling frame so that the two modules may communicate (signals, data) with each other. The two modules may each have module antennas (MA-1, MA-2), and may be disposed in respective two openings (MO-1, MO-2) of a coupling frame (CF). A coupling antenna (CPA) having two coupler coils (CC-1, CC-2) disposed close to the two modules antennas of the two modules. The coupling antenna may have only the two coupler coils (CC-1, CC-2), connected with one another, without the peripheral card antenna (CA) component of a conventional booster antenna (BA). Energy harvesting is disclosed.

Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Abstract: An RFID system includes an antenna of a reader/writer and an antenna of an RFID tag. Transmission and reception of a high-frequency signal of a UHF band is performed between the antenna of the reader/writer and the antenna of the RFID tag that are arranged so as to be adjacent to each other. A loop antenna including a loop conductor is used as the antenna of the reader/writer, and coil antennas including a plurality of laminated coil conductors are used as the antenna of an RFID tag. In addition, the conductor width of the loop conductor in the loop antenna is greater than the conductor widths of the coil conductors in the coil antennas.

Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

Abstract: A radio frequency module includes a module board including a first principal surface and a second principal surface on opposite sides thereof; a transmission power amplifier; a control circuit configured to control the transmission power amplifier; a first transmission filter and a second transmission filter; and a first switch configured to switch connection of an output terminal of the transmission power amplifier between the first transmission filter and the second transmission filter. The control circuit is disposed on the first principal surface, and the first switch is disposed on the second principal surface.

Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.

Abstract: A microwave or radio frequency (RF) device includes stacked printed circuit boards (PCBs) mounted on a flexible PCB having at least one ground plane and a signal terminal. Each of the stacked PCBs includes through-holes the sidewalls of which are coated with a conductive material. Microwave components are mounted on the flexible PCB within the through-holes, such that signal terminals of the components bond to signal terminals of respective through-holes. A conductive cover is mounted on the PCBs such that the cover is in electrical contact with the ground plane of the flexible PCB through the conductive material, forming shielding cavities around the components. The flexible PCB is folded such that the cover of one PCB faces the cover of the second PCB. The flexible PCB includes striplines or microstrips that carry RF or microwave signals to the signal terminals.

Abstract: Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

Abstract: An electronic component includes an electronic device including a substrate, and a wiring board including a conductor unit electrically connected to the electronic device and an insulation unit configured to support the conductor unit. The substrate includes a front surface including a first region, a back surface including a second region, and an end surface connecting the front surface and the back surface. The substrate further includes a first portion located between the first region and the second region and a second portion having a thickness smaller than that of the first portion. The insulation unit of the wiring board is located between a virtual plane surface located between the first region and the second region and the second portion.

Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a front surface and a back surface, forming first and second through holes in the substrate, filling the first and second through holes with metals, forming a subassembly on the front surface of the substrate. The subassembly includes a first metal layer and a second metal layer insulated from the first metal layer, the first metal layer is electrically connected to the metal filled in the first through hole, the second metal layer is electrically connected to the metal filled in the second through hole, and a metal connection pad is on the substrate and surrounds the subassembly. The method also includes providing a cap assembly including a metal connection member, bonding the cap assembly to the subassembly, and thinning the back surface of the substrate to expose the first and second through holes.

Abstract: A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer.

Abstract: A module (101) includes a substrate (1) having a main surface (1a) and a conductor column (4) disposed on the main surface (1a). The conductor column (4) includes a conductor column body (4a) and an overhanging part (4b) overhanging from an outer periphery of the conductor column body (4a) in a middle of a height direction of the conductor column body (4a).

Abstract: A system includes a magnetic field sensor arrangement and a controller. The magnetic field sensor arrangement includes a first sensor chip having an integrated circuit differential magnetic field sensor circuit configured to generate a first output signal comprising first signal pulses, a second sensor chip having an integrated second differential magnetic field sensor circuit configured to generate a second output signal comprising second signal pulses, and at least one output signal terminal configured to output the first and the second output signals. The controller receives the first and the second signal pulses from the at least one output signal terminal, evaluates the first and the second signal pulses, and detects an error of an operation of the magnetic field sensor arrangement in response to the first and the second signal pulses not satisfying an expected output pattern of the first and the second signal pulses.

Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.

Abstract: An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

Abstract: A semiconductor package that effectively controls heat generated from a semiconductor chip is provided. A semiconductor device with improved product reliability and performance is provided.

Abstract: The present disclosure provides an image capturing assembly and its packaging method, a lens module and an electronic device. The packaging method includes: providing a photosensitive chip; mounting an optical filter on the photosensitive chip; providing a carrier substrate and temporarily bonding the photosensitive chip and functional components on the carrier substrate; and forming an encapsulation layer on the carrier substrate and at least between the photosensitive chip and the functional components.

Abstract: An electronic component-embedded substrate includes a first wiring layer, a first electronic component disposed on the first wiring layer, a first insulating material covering at least a portion of each of the first wiring layer and the first electronic component, a second wiring layer disposed on the first insulating material, a second electronic component disposed on the second wiring layer and connected to the first electronic component in an electrical parallel connection, a second insulating material disposed on the first insulating material and covering at least a portion of each of the second wiring layer and the second electronic component, and a first via penetrating through the first insulating material and connecting the first electronic component and the second wiring layer.

Abstract: Discussed are a device for self-assembling semiconductor light-emitting diodes, in which the device includes an assembly chamber having a space for accommodating a fluid; a magnetic field forming part having at least one magnet for applying a magnetic force to the semiconductor light-emitting diodes dispersed in the fluid and a moving part for changing positions of the at least one magnet so that the semiconductor light-emitting diodes move in the fluid; and a substrate chuck having a substrate support part configured to support a substrate, and a vertical moving part for lowering the substrate so that one surface of the substrate is in contact with the fluid in a state in which the substrate is supported by the substrate support part, wherein the vertical moving part provided at the substrate chuck lowers the substrate on to the fluid so that a force of buoyancy by the fluid is applied to the substrate.

Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

Abstract: The present disclosure provides a display device, including a substrate, a plurality of semiconductor light emitting devices arranged on the substrate, a first wiring electrode and a second wiring electrode extended from the semiconductor light emitting devices, respectively, to supply an electric signal to the semiconductor light emitting devices, a plurality of pair electrodes arranged on the substrate to generate an electric field when an electric current is supplied, and provided with first and second pair electrodes formed on an opposite side to the first and second wiring electrodes with respect to the semiconductor light emitting devices, and a dielectric layer formed to cover the pair electrodes, wherein the plurality of pair electrodes are arranged in parallel to each other along a direction.

Abstract: A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test.

Abstract: An electronic apparatus that includes a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on the substrate; a spacer attached to the substrate and situated between the first and second semiconductor chips; a lid mounted on the substrate and enclosing the first and second semiconductor chips and the spacer, the spacer having an adhesive material adhesively attached to the lid; and underfill material underneath the first and second semiconductor chips, underneath the spacer and between the spacer and the first and second semiconductor chips.

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

Abstract: A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

Abstract: The present disclosure provides a camera assembly and a packaging method thereof, a lens module, and an electronic device.

Abstract: A package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure includes a composite dielectric layer, a plurality of under bump metallization patterns, a dielectric layer, and a plurality of conductive patterns. The composite dielectric layer includes a first sub-layer and a second sub-layer stacked on the first sub-layer. The under bump metallization patterns are over the first sub-layer and penetrate through the composite dielectric layer. The dielectric layer is disposed on the second sub-layer of the composite dielectric layer. The conductive patterns are embedded in the dielectric layer. The die and the conductive structures are on the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is over the conductive structures, the encapsulant, and the die.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.

Abstract: A stack package includes a supporting substrate that supports first and second semiconductor dies. The supporting substrate is disposed on a package substrate and is supported by first and second connection bumps. Redistributed line (RDL) patterns are disposed on the supporting substrate to electrically connect the first semiconductor die to the first and second connection bumps. The second semiconductor dies are connected to the package substrate by bonding wires.

Abstract: Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a substrate, an array of NAND memory cells above the substrate, and a first bonding layer above the array of NAND memory cells. The first bonding layer includes first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer above the first bonding layer and including second bonding contacts, a peripheral circuit and an array of PCM cells above the second bonding layer, and a semiconductor layer above and in contact with the peripheral circuit. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.