Abstract: A stacked semiconductor package includes first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units. A spacer including a spacer body may be interposed between the first semiconductor chip and the second semiconductor chip, with an inverter chip embedded in the spacer body. Wiring patterns formed on the spacer body may connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip.

Abstract: Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate.

Abstract: An electrical and/or electronic device including: an electrical and/or electronic component; two layers of material forming front and back faces of the device and between which the electrical and/or electronic component is encapsulated, the component including at least two opposite faces placed facing the two layers of material; an electrical contact element placed in contact with one of the faces of the electrical and/or electronic component; an element based on at least one elastic material placed between one of the two layers of material and the electrical contact element, forming a first layer of elastic material covering the one of the two layers of material; and a second layer based on at least one elastic material with an elastic stiffness less than the stiffness of the elastic material in the first layer, placed in contact with the first layer of elastic material.

Abstract: A semiconductor device that is resistant to bending stress and has a structure in which an antenna circuit, an electric double layer capacitor for storing electricity, and the like are formed over a signal processing circuit that is provided over a substrate and has a charging circuit. The signal processing circuit having the charging circuit is provided over a substrate, and the antenna circuit and the electric double layer capacitor are provided over the signal processing circuit. The antenna circuit is electrically connected to the signal processing circuit, and the electric double layer capacitor is electrically connected to the charging circuit. With such a structure, a wiring for connecting the charging circuit and the electric double layer capacitor can be made short. Accordingly, a semiconductor device that is resistant to bending stress can be provided.

Abstract: The invention relates to a power semiconductor module including a module underside, a module housing, and at least two substrates spaced from each other. Each substrate has a topside facing an interior of the module housing and an underside facing away from the interior of the module housing. The underside of each substrate includes at least one portion simultaneously forming a portion of the module underside. At least one mounting means disposed between two adjacent substrates enables the power semiconductor module to be secured to a heatsink.

Abstract: A semiconductor device which includes a substrate, a semiconductor chip which is mounted on the substrate, a package in which an upper surface of the substrate and the semiconductor chip are sealed using an insulating material, and a molding material which is exposed to the upper surface of the package. In addition, the device includes a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package.

Abstract: An integrated circuit (IC) package has a package member having a first surface and a second surface opposite the first surface. A first plurality of contact members is physically and electrically fixed to the second surface. An interposer substrate having a second plurality of contact members on one surface thereof which make physical and electrical contact with respective ones of the first plurality of contact members. The interposer substrate is configured to have at least one circuit member mounted to a second surface thereof opposite the one surface thereof.

Abstract: A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: a base substrate having grooves formed between a plurality of semiconductor device mounting areas; semiconductor devices mounted on the semiconductor device mounting areas of the base substrate; and a molding formed on the base substrate and in inner portions of the grooves.

Abstract: An improved light emitting diode (LED) device with a thermoelectric module is provided. In the preferred embodiment, the LED device herein includes a heat sink/housing containing a LED light, heat slug, and LED circuit board attached to a first side of a thermoelectric module and a heat sink on a second side of the thermoelectric module. Heat is conducted from the LED light and through the circuit board to the first side of the thermoelectric module. The heat sink housing dissipates heat from the second side of the thermoelectric module to create a temperature differential across the thermoelectric module and generate electricity.

Abstract: In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Abstract: In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.

Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.

Abstract: A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.

Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.

Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

Abstract: A power module includes a first heat sink, first and second power chips, a thermo-conductive insulating layer, a lead frame and a molding compound. The first heat sink has a first area and a second area. The first power chip is disposed in the first area. The thermo-conductive insulating layer is disposed in the second area. The second power chip is disposed on the heat sink through the thermo-conductive insulating layer. The lead frame is electrically connected to at least one of the first and second power chips. The molding compound covers the first and second power chips, the thermo-conductive insulating layer and a portion of the lead frame. The first heat sink is electrically connected to at least one of the first and second power chips. Because the first power chip is not disposed on the first heat sink through the thermo-conductive insulating layer, the cost can be reduced.

Abstract: According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided.

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

Abstract: A three-dimensional semiconductor module and an electronic system including the same are provided. The semiconductor module includes a module substrate, a logic device formed on a part of the module substrate, and a plurality of memory devices formed on another part of the module substrate, wherein the plurality of memory devices are disposed perpendicular to the logic device, and the module substrate on which the plurality of memory devices are formed is supported by a supporter. The electronic system includes the semiconductor module.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.

Abstract: An electro-optic apparatus has an electro-optic panel, driver semiconductor chips bonded onto the terminal portion of the electro-optic panel, and two protection films either or both of which are transparent, wherein the electro-optic panel is sealed by being sandwiched between the two protection films, and one protection film that covers the terminal portion has openings for exposing the driver semiconductor chips.

Abstract: An electret accelerometer is provided in which a diaphragm, an electret, a back plate and an electronic circuit are placed in a casing and the casing is sealed to isolate the diaphragm from external acoustic signals.

Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.

Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Abstract: A semiconductor package includes a print circuit part, a lower chip, an upper chip, a thermal conductivity part, and an encapsulation resin. The lower chip and the upper chip are mounted on the print circuit part through wire bonding connection. The thermal conductivity part efficiently dissipates heat from the chips to the outside of the package. The encapsulation resin entirely seals the package while exposing the thermal conductivity part. A adhesive sheet is hardened to form a bonding layer between the thermal conductivity part and the upper chip, a bonding layer between the semiconductor chips, and a bonding layer between the semiconductor chip and the wired component. The configuration contributes to miniaturization, high integration, and heat resistance reduction of a semiconductor package using high-heat-generating ICs.

Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

Abstract: A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer.

Abstract: A sensor module includes a housing and a chip system disposed therein, the chip system being disposed on a substrate and being embedded in a sealing layer deposited on the substrate. The chip system is disposed in a window region of a frame structure disposed on the substrate, the frame structure featuring substantially the same thermal expansion properties as the substrate.

Abstract: A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode.

Abstract: The semiconductor device has a unit stack body including a plurality of units stacked on one another. Each unit includes a power terminal constituted of a lead part and a connection part. The connection part is formed with a projection and a recess. When the units are stacked on one another, the projection of one unit is fitted to the recess of the adjacent unit, so that the power terminals of the respective unit are connected to one another.

Abstract: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.

Abstract: A circuit includes a plurality of integrated circuits or dies having corresponding circuits, the plurality of integrated circuits or dies include a first plurality of integrated circuits or dies having corresponding millimeter wave interfaces and a second plurality of integrated circuits or dies having corresponding inductive interfaces. The first plurality of integrated circuits or dies communicate first signals therebetween via the corresponding millimeter wave interfaces and the second plurality of integrated circuits or dies communicate second signals therebetween via the corresponding inductive interfaces.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.

Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Abstract: A plurality of semiconductor elements is adjacently mounted on a substrate by a solder with a melting point of 200° C. or lower, an electronic part other than the semiconductor elements is mounted on the substrate between the adjacently mounted semiconductor elements by a solder with a melting point of 200° C. or lower, and spaces between the plurality of semiconductor elements and the substrate, spaces between the electronic part and the substrate, and spaces between the plurality of semiconductor elements and the electronic part are integrally molded with a molding resin.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Abstract: A power semiconductor module includes a plurality of sets of semiconductor switching elements, a molded resin casing containing the semiconductor switching elements, screw holders for receiving mounting screws formed at bottom regions of four corners of the molded resin casing, first terminal blocks having main circuit terminals, and arranged on a central region of a top surface of the molded resin casing, and second terminal blocks having control terminals arranged at a side edge of the molded resin casing apart. Insulating separation walls having a configuration of a rib erect from a surface of the second terminal blocks, and are interposed between groups of the control terminals corresponding to the sets of semiconductor switching elements, and between the screw holder including the mounting screw therein on the molded resin casing and the control terminal at a high voltage side adjacent to the screw holder.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region.

Abstract: A semiconductor module includes a module housing, at least one substrate, a number N of at least two controllable power semiconductor chips arranged inside the module housing and one after another in a lateral direction, a single main load terminal arranged outside the module housing and electrically connected to the first main electrodes, and an auxiliary terminal arranged outside the module housing and electrically connected to the first main electrodes via an auxiliary terminal connecting conductor.

Abstract: Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.

Abstract: A tape adhesive type material is directionally conductive. According to an example embodiment of the present invention, carbon nanotubes (212, 214, 216, 218) are configured in a generally parallel arrangement in a tape base type material (210). The carbon nanotubes conduct (e.g., electrically and/or thermally) in their generally parallel direction and the tape base type material inhibits conduction in a generally lateral direction. In some implementations, the tape base material is arranged between integrated circuit components (220, 230), with the carbon nanotubes making a conductive connection there between. This approach is applicable to coupling a variety of components together, such as integrated circuit dies (flip chip and conventional dies) to package substrates, to each other and/or to leadframes.

Abstract: A method and apparatus for placing quartz SAW (Surface Acoustic Wave) devices together with a clock/oscillator have been disclosed. Mounting on a single lead frame both a SAW device and an integrated circuit (IC).

Abstract: A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.