Portion Of Housing Of Specific Materials Patents (Class 257/729)
  • Patent number: 11923319
    Abstract: A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Woo Park
  • Patent number: 11367692
    Abstract: A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall thickness of less than 0.2 mm and a thinned area surrounding the lens so that in the thinned area the wall thickness is reduced by at least 35%.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 21, 2022
    Assignee: SCHOTT AG
    Inventors: Robert Hettler, Reinhard Ecker, Martin Lindner-Stettenfeld, Georg Mittermeier
  • Patent number: 11335650
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 17, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
  • Patent number: 11217557
    Abstract: An electronic device includes a substrate, a first pad disposed on the substrate, a second pad disposed opposite to the first pad, and a conductive particle disposed between the first pad and the second pad. The first pad has a recess, and a part of the conductive particle sinks in the recess.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 4, 2022
    Assignee: InnoLux Corporation
    Inventor: Pai-Chiao Cheng
  • Patent number: 11153977
    Abstract: A circuit carrier includes a first side, two layers arranged to define an intermediate space there between, with at least one of the two layers being electrically conductive and attached to the first side. The at least one of the two layers has a region deformed such as to exhibit an indentation and has a trace structure in the indentation. A first insulating material fills the intermediate space, and a second insulating material fills the indentation, A second side in opposition to the first side is shaped to have in the deformed region a cut-out for receiving a bare die such as to come into an electrical contact with the at least one of the two layers.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: October 19, 2021
    Assignee: Siemens Aktiengesellschaft
    Inventor: Stefan Pfefferlein
  • Patent number: 11122969
    Abstract: There is provided an endoscopic device, including: an image sensor section including an image sensor that senses and converts lights into an electrical signal; a substrate that is electrically connected to the image sensor section; and an intermediate unit, interposed between the image sensor section and the substrate, that electrically connects the image sensor section and the substrate.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 21, 2021
    Assignees: SONY OLYMPUS MEDICAL SOLUTIONS INC., SONY CORPORATION
    Inventors: Naoyuki Ohno, Masahiro Kojima, Shigeru Teshigahara
  • Patent number: 11043551
    Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Juncheol Shin, Jeongho Lee, Hokyoon Kwon, Yanghee Kim
  • Patent number: 11004928
    Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Juncheol Shin, Jeongho Lee, Hokyoon Kwon, Yanghee Kim
  • Patent number: 10893625
    Abstract: A plurality of electronic circuit boards (2), on which electronic components are mounted, is inserted in parallel through an electronic circuit insertion port (11) of a casing body (1). A gap (3) is formed between front panels (22) of inserted and adjacent electronic circuit boards (2) inserted. A bridge body (5) constituting conduction means electrically conducts a first conductive side portion (22a) of a front panel (22) in one electronic circuit board (2) of adjacent electronic circuit boards (2) and a second conductive side portion (22b) of a front panel (22) in another electronic circuit board (2) that faces the first conductive side portion (22a) via a gap (3).
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 12, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuji Ando, Chiharu Miyazaki
  • Patent number: 10886210
    Abstract: A cover for an electronic device includes a support body having a through-passage. An optical element which allows light to pass is mounted on said support body in a position extending across the through-passage. A surface of the optical element includes an electrically-conducting track configured as a security detection element. At least two electrical connection leads are rigidly attached to the support body and include first uncovered portions internal to the support body and electrically connected to spaced apart locations on the electrically-conducting track. The at least two electrical connection leads further including second uncovered portions external to said support body. The cover is mounted on a support plate carrying an electronic chip situated in the through-passage at a distance from the optical element.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 5, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Romain Coffy
  • Patent number: 10782187
    Abstract: Infrared (IR) temperature measurement and stabilization systems, and methods related thereto are provided. One or more embodiments passively stabilizes temperatures of objects in proximity and within the path between an infrared (IR) sensor and target object. An overmolded sensor assembly may include an IR sensor, which may include a sensing element or IR element and a circuit or signal processor. The IR element may be thermally bonded with a frame or conductive top hat.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 22, 2020
    Assignee: CVG MANAGEMENT CORPORATION
    Inventor: Robert Maston
  • Patent number: 10329141
    Abstract: An encapsulated device of semiconductor material wherein a chip of semiconductor material is fixed to a base element of a packaging body through at least one pillar element having elasticity and deformability greater than the chip, for example a Young's modulus lower than 300 MPa. In one example, four pillar elements are fixed in proximity of the corners of a fixing surface of the chip and operate as uncoupling structure, which prevents transfer of stresses and deformations of the base element to the chip.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 25, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Tocchio, Carlo Valzasina, Luca Guerinoni, Giorgio Allegato
  • Patent number: 10285287
    Abstract: An electronic component includes a main body and signal terminals projecting in a projection direction of a module control terminal, the signal terminals being arranged in an arrangement direction. Through-holes are formed in a control board, and the signal terminals are inserted into the through-holes. In a case, an opening that opens in the projection direction is formed, and ends of the signal terminals are positioned in the projection direction. At a position adjacent to a through-hole group including the through-holes in the arrangement direction, a communication space is formed which makes a first space, which is positioned at a side of electronic component in the projection direction, communicate with a second space opposite to the first space. When a length of the through-hole group is a, and a distance between the through-hole group and the communication space is b, a length of the communication space is longer than a+b.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: May 7, 2019
    Assignee: DENSO CORPORATION
    Inventor: Yukinori Mizuno
  • Patent number: 10260954
    Abstract: Infrared (IR) temperature measurement and stabilization systems, and methods related thereto are provided. One or more embodiments passively stabilizes temperatures of objects in proximity and within the path between an infrared (IR) sensor and target object. A protective housing may encase an IR sensor, which may include a sensing element or IR element, a circuit or signal processor, and a housing seal plug. The IR element may be thermally bonded with a frame or conductive top hat.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 16, 2019
    Assignee: CVG MANAGEMENT CORPORATION
    Inventor: Robert A. Maston
  • Patent number: 10199549
    Abstract: A structure according to embodiments of the invention includes a semiconductor light emitting device and an optical element disposed over the semiconductor light emitting device. The semiconductor light emitting device is disposed in a recess in the optical element. A reflector is disposed on a bottom surface of the optical element. A method according to embodiments of the invention includes disposing a semiconductor light emitting device on a substrate and forming a reflector adjacent the semiconductor light emitting device. An optical element is formed over the semiconductor light emitting device. The semiconductor light emitting device is removed from the substrate.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: February 5, 2019
    Assignee: Lumileds LLC
    Inventors: Jerome Chandra Bhat, Grigoriy Basin, Kenneth Vampola
  • Patent number: 10177677
    Abstract: An inverter structure for a vehicle is provided. The inverter includes a capacitor for receiving direct current supplied from a battery, a power module assembly including a plurality of power modules and a plurality of coolers, and an output bus-bar connected to the plurality of power modules to output three-phase alternating current to a motor. In particular, inside of the power module, power modules of a plurality of power modules are connected to the capacitor to convert the direct current into the three-phase alternating current, and coolers of a plurality of coolers are alternately stacked one above another such that each cooler comes into contact at its upper and lower surfaces with adjacent power modules to enable heat transfer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 8, 2019
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventor: Yun Ho Kim
  • Patent number: 10076031
    Abstract: An electronic device includes an insulating base substrate having a through electrode, an electronic element provided on one surface of the insulating base substrate and connected to the through electrode, a lid provided on the one surface of the insulating base substrate, and an external electrode covering an end face of the through electrode that is exposed on another surface of the insulating base substrate different from the one surface thereof. The external electrode has a conductive film, a first electrolytic plating film provided on the conductive film, and a second electrolytic plating film provided on the first electrolytic plating film. The conductive film is provided on the exposed end face of the through electrode and on portions of the another surface of the insulating base substrate in the vicinity of the exposed end face of the through electrode.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: September 11, 2018
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Atsushi Kozuki, Hideshi Hamada, Yoshifumi Yoshida
  • Patent number: 9985400
    Abstract: An electrical junction box includes an electrical junction box main body having a mount portion and a separate attachment body removably attached to the mount portion, a pair of connectors are respectively provided on opposing surfaces of the mount portion and the attachment body are connected to each other, and a vibration suppressing member is between the opposing surfaces, the vibration suppressing member suppressing vibration of the attachment body by exerting a frictional force on the opposing surfaces.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: May 29, 2018
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Kiyofumi Kawaguchi, Yukitaka Saitou, Jyun Yamaguchi, Itsurou Kikkawa, Yuuichi Hattori, Takuya Inoue
  • Patent number: 9837338
    Abstract: A terminal case formed by integrally molding a lead frame and a case that has internally an inner face on which the lead frame is mounted and has externally a step portion fixed to a circuit block having an insulating substrate and semiconductor chips formed on the insulating substrate. An opening portion is formed between the step portion and the inner face so as to extend through them, and the opening portion is filled with an adhesive to bond the insulating substrate to the step portion. Since a connecting area to which a bonding wire of the lead frame is ultrasonically bonded is fixed, it is possible to reduce the bonding failures of the lead frames.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 5, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tadahiko Sato
  • Patent number: 9826131
    Abstract: Compact camera module can include auxiliary spacers to facilitate use of dam-and-fill encapsulation techniques. An encapsulant disposed on side edges of the auxiliary spacer can close off a gap between the auxiliary spacer and a support on which an image sensor is mounted so as to substantially seal off an area in which bond wires or other components are located. In some cases, the thickness of a transmissive substrate in the module can be reduced near its periphery to provide more head room for the bond wires, which can result in a smaller overall footprint for the module.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: November 21, 2017
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Jukka Alasirniö, Stephan Heimgartner
  • Patent number: 9773084
    Abstract: A heat dissipation simulator of a component on a printed circuit board (PCB) includes a simulation board and a simulated heat source. The simulation board includes an iron layer and a plastic layer. The simulated heat source includes a simulation chip, a thermal, and a heat sink. The simulation chip, the thermal piece, and the heat sink are mounted on the simulation board in that order. The heat dissipation simulator replaces a sample of the PCB with the component for simulating working states of the component on the PCB.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: September 26, 2017
    Assignee: ScienBiziP Consulting(Shenzhen)Co., Ltd.
    Inventors: Wan-Li Ning, Li-Ren Fu, Yu Han, Jun-Hui Wang, Al-Ling He, He Feng, Kun Li, Shu-Ni Yi, Lei Liu, An-Gang Liang, Ping-Chuan Deng, Ming-Yu Liu, Xia-Bing Gao, Han-Bing Zhang, Zheng-Heng Sun
  • Patent number: 9730354
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a chassis and a circuit board. The chassis may have one or more structural posts. The circuit board may mechanically couple to the chassis, and the circuit board may comprise a substrate having formed therein one or more through-holes and one or more hooks each configured to mechanically couple the circuit board to the chassis via a corresponding structural post of the one or more structural posts, each of the one or more hooks comprising one or more mounting features, wherein each of the one or more mounting features is sized and shaped to engage with a corresponding one of the one or more through-holes in order to mechanically couple such hook to the substrate.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: August 8, 2017
    Assignee: Dell Products L.P.
    Inventors: Corey Dean Hartman, Michael Dennis Marcade
  • Patent number: 9385091
    Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Cheng-Chieh Hsieh, Tsung-Shu Lin
  • Patent number: 9209138
    Abstract: An integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion of especial utility in conjunction with magnetoresistive random access memory (MRAM) and other devices requiring magnetic shielding.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: December 8, 2015
    Assignee: Aeroflex Colorado Springs, Inc.
    Inventors: Scott Popelar, Matthew Von Thun, Richard Jadomski, Karen Jackson
  • Patent number: 9165858
    Abstract: An arrangement having a cooling circulation, a plurality of modular power semiconductor modules and at least one capacitor, wherein a power semiconductor module has a power electronics switch and a cooling device, which is capable of carrying a flow of a cooling fluid, for cooling the switch, the cooling device having at least one cooling face, and four connection devices for the cooling fluid. The connection devices are arranged in pairs on main sides of the power semiconductor module. The power semiconductor modules have their main sides strung together modularly by connecting corresponding connection devices on successive power semiconductor modules. To this end, at least two successive power semiconductor modules have a capacitor arranged between them which, for its part, is cooled by means of the cooling circulation of the cooling fluid as provided by the arrangement.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 20, 2015
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventors: Jürgen Steger, Markus Knebel, Andreas Maul, Susanne Kalla
  • Patent number: 9116145
    Abstract: A flexible IC/microfluidic hybrid integration and packaging method and resulting device. A single flexible elastomer substrate, such as polydimethylsiloxane (PDMS), has dedicated microchannels filled with liquid metals (or low melting point solders) to provide electrical interconnects to a solid-state IC die, such as CMOS, and additional microchannels for hybrid integration with microfluidics without performing any post-processing on the IC die. The liquid metal used can be a gallium-indium-tin eutectic alloy (also called Galinstan).
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 25, 2015
    Assignee: The George Washington University
    Inventors: Zhenyu Li, Mona E. Zaghloul, Bowei Zhang, Can E. Korman
  • Patent number: 9070745
    Abstract: In one embodiment, a method for forming a direct fusion bond between fractional components of a semiconductor laminate structure can include generating one or more direct bonding surfaces on each of a plurality of semiconductor wafers. A first fractional component and a second fractional component can be cut from at least one of the plurality of semiconductor wafers. A second direct bonding surface of the second fractional component can be placed into contact with a first direct bonding surface of the first fractional component to define an initial contact area. An angle of approach between the second direct bonding surface of the second fractional component and the first direct bonding surface of the first fractional component can be closed to create a direct fusion bond of a semiconductor laminate structure. The direct fusion bond can be larger than the initial contact area.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: June 30, 2015
    Assignee: LAM RESEARCH CORPORATION
    Inventor: John F. Stumpf
  • Patent number: 9013036
    Abstract: A sealing member is disclosed, which includes a first structure and a second structure. The first structure includes a groove with an opening towards the outside of the sealing member, wherein the second structure is disposed in the groove. The first structure includes a first material, and the second structure includes a second material, wherein the water absorption rate of the second material is greater than the water absorption rate of the first material. Also, an electronic device using the sealing member is disclosed.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 21, 2015
    Assignee: Wistron Corp.
    Inventor: Chih-Feng Yeh
  • Patent number: 9003637
    Abstract: A method of manufacturing a microphone assembly having an ear set function includes assembling a mike cell unit; obtaining a region for connection with the mike cell unit on a PCB, mounting only a conductive member in the region, and mounting other remaining components outside the region; adhering the mike cell unit to a corresponding region of the PCB; and sealing an adhering portion between the mike cell unit and the PCB. Assembling the mike cell unit includes inserting a mike cell case having a sound hole and a curing portion into a diaphragm assembly; stacking a spacer on the diaphragm assembly; inserting a back electrode plate into an insulating ring base; mounting the insulating ring base on the spacer; mounting a metal ring base on the insulating ring base; and curing or clamping a curing portion of the mike cell case.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 14, 2015
    Assignee: BSE Co., Ltd.
    Inventors: Dong Sun Lee, Hyoung Joo Kim
  • Patent number: 8937380
    Abstract: A semiconductor package includes a lead spaced apart from a semiconductor die. The die includes a diaphragm disposed at a first side of the die and is configured to change an electrical parameter responsive to a pressure difference across the diaphragm. The die further includes a second side opposite the first side, a lateral edge extending between the first and second sides and a terminal at the first side. An electrical conductor connects the terminal to the lead. An encapsulant is disposed along the lateral edge of the die so that the terminal and the electrical conductor are spaced apart from the encapsulant. The encapsulant has an elastic modulus of less 10 MPa at room temperature. A molding compound covers and contacts the lead, the electrical conductor, the encapsulant, the terminal and part of the first side of the die so that the diaphragm is uncovered by the molding compound.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 20, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Vaupel, Uwe Fritzsche Schindler
  • Patent number: 8907473
    Abstract: In accordance with one or more embodiments, a semiconductor device comprises a semiconductor die having a heat region disposed on at least one portion of the semiconductor die, and a diamond substrate disposed proximate to the semiconductor die, wherein the diamond substrate is capable of dissipating heat from the diamond substrate via at least one or more bumps coupling the diamond substrate to the heat region of the semiconductor die.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: December 9, 2014
    Assignee: Estivation Properties LLC
    Inventors: Jeffrey Dale Crowder, Dave Rice
  • Patent number: 8896105
    Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a radiation sensitive component in and/or on a microelectronic device, placing a curable component in and/or on the microelectronic device, and forming a barrier in and/or on the microelectronic device to at least partially inhibit irradiation of the radiation sensitive component. The radiation sensitive component can be doped silicon, chalcogenide, polymeric random access memory, or any other component that is altered when irradiated with one or more specific frequencies of radiation. The curable component can be an adhesive, an underfill layer, an encapsulant, a stand-off, or any other feature constructed of a material that requires curing by irradiation.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Kristy A. Campbell
  • Patent number: 8866290
    Abstract: Embodiments of the present disclosure describe techniques and configurations for molded heat spreaders. In some embodiments, a heat spreader includes a first insert having a first face and a first side, the first face positioned to form a bottom surface of a first cavity, and a second insert having a second face and a second side, the second face positioned to form a bottom surface of a second cavity. The second cavity may have a depth that is different from a depth of the first cavity. The heat spreader may further include a molding material disposed between the first and second inserts and coupled with the first side and the second side, the molding material forming at least a portion of a side wall of the first cavity and at least a portion of a side wall of the second cavity. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Zhizhong Tang, Syadwad Jain, Paul R. Start
  • Patent number: 8865522
    Abstract: A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallization region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallization region.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten von Koblinski, Gerald Lackner, Karin Schrettlinger, Markus Ottowitz
  • Patent number: 8860306
    Abstract: An object is to provide a highly reliable light emitting device which is thin and is not damaged by external local pressure. Further, another object is to manufacture a light emitting device with a high yield by preventing defects of a shape and characteristics due to external stress in a manufacture process. A light emitting element is sealed between a first structure body in which a fibrous body is impregnated with an organic resin and a second structure body in which a fibrous body is impregnated with an organic resin, whereby a highly reliable light emitting device which is thin and has intensity can be provided. Further, a light emitting device can be manufactured with a high yield by preventing defects of a shape and characteristics in a manufacture process.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Shingo Eguchi, Mitsuo Mashiyama, Masatoshi Kataniwa, Hironobu Shoji, Masataka Nakada, Satoshi Seo
  • Patent number: 8845909
    Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Shih Shen
  • Publication number: 20140252591
    Abstract: A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the reinforcement plate to the die.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Cheng-Chieh Hsieh, Tsung-Shu Lin
  • Patent number: 8816485
    Abstract: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventors: Chris Apanius, Robert A. Shick, Hendra Ng, Andrew Bell, Wei Zhang, Phil Neal
  • Patent number: 8803165
    Abstract: A nitride semiconductor light emitting device includes an n-type GaN substrate (101) that is a nitride semiconductor substrate, a nitride semiconductor layer including a p-type nitride semiconductor layer formed on the n-type GaN substrate (101). The p-type nitride semiconductor layer includes a p-type AlGaInN contact layer (108), a p-type AlGaInN cladding layer (107) under the p-type AlGaInN contact layer (108), and a p-type AlGaInN layer (106). A protection film (113) made of a silicon nitride film is formed above a current injection region formed in the p-type nitride semiconductor layer.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: August 12, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takeshi Kamikawa
  • Patent number: 8803312
    Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallization region is formed on the machined second surface of the semiconductor wafer.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: August 12, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten von Koblinski, Gerald Lackner, Karin Schrettlinger, Markus Ottowitz
  • Patent number: 8796697
    Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
  • Patent number: 8796845
    Abstract: An electronic device according to the invention includes: a substrate; an MEMS structure formed above the substrate; and a covering structure defining a cavity in which the MEMS structure is arranged, wherein the covering structure has a first covering layer covering from above the cavity and having a through-hole in communication with the cavity and a second covering layer formed above the first covering layer and closing the through-hole, the first covering layer has a first region located above at least the MEMS structure and a second region located around the first region, the first covering layer is thinner in the first region than in the second region, and a distance between the substrate and the first covering layer in the first region is longer than a distance between the substrate and the first covering layer in the second region.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: August 5, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Yoko Kanemoto, Akira Sato, Shogo Inaba
  • Patent number: 8772924
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Mathew J. Manusharow
  • Patent number: 8766269
    Abstract: It is an object to provide a flexible light-emitting device with high reliability in a simple way. Further, it is an object to provide an electronic device or a lighting device each mounted with the light-emitting device. A light-emitting device with high reliability can be obtained with the use of a light-emitting device having the following structure: an element portion including a light-emitting element is interposed between a substrate having flexibility and a light-transmitting property with respect to visible light and a metal substrate; and insulating layers provided over and under the element portion are in contact with each other in the outer periphery of the element portion to seal the element portion. Further, by mounting an electronic device or a lighting device with a light-emitting device having such a structure, an electronic device or a lighting device with high reliability can be obtained.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kaoru Hatano, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura
  • Patent number: 8723339
    Abstract: Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: May 13, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Masaki Kasai, Osamu Miyata
  • Patent number: 8698262
    Abstract: The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which an integrated circuit is sealed by films. In particular, the films sealing the integrated circuit have a hollow structure; therefore the wireless chip can have a new function.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Koji Dairiki, Naoto Kusumoto
  • Patent number: 8680669
    Abstract: An electronic component includes a unit including an electronic device; and an opposite member opposing the electronic device, wherein the unit and the opposite member are bonded together with an adhering member disposed between the unit and the opposite member and having light-cured resin and inorganic particles dispersed in the light-cured resin; and wherein in a particle-diameter distribution of the inorganic particles by volume, a particle diameter having a cumulative value of distribution of 50 is 0.5 ?m or more, and a particle diameter having a cumulative value of distribution of 90% is 5.0 ?m or less.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Kurihara, Koji Tsuduki, Hiroaki Kobayashi
  • Patent number: 8664779
    Abstract: Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Masaki Kasai, Osamu Miyata
  • Patent number: 8643165
    Abstract: A plastic package (100) in which a semiconductor chip (101) is adhesively (102) attached to a metal stripe (110a) having an agglomerate structure, and electrically connected to bondable and solderable metal stripes (120) having particulate structures; metal stripes (120) are touching metal stripes (110b) of agglomerate structure to form vertical stacks (150); coats of solder (140) are welded to the agglomerate metal stripes (100a and 110b).
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: February 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Darvin R. Edwards, Siva Prakash Gurrum, Masood Murtuza, Matthew D. Romig, Kazunori Hayata
  • Patent number: 8643020
    Abstract: It is an object to provide a flexible light-emitting device with high reliability in a simple way. Further, it is an object to provide an electronic device or a lighting device each mounted with the light-emitting device. A light-emitting device with high reliability can be obtained with the use of a light-emitting device having the following structure: an element portion including a light-emitting element is interposed between a substrate having flexibility and a light-transmitting property with respect to visible light and a metal substrate; and insulating layers provided over and under the element portion are in contact with each other in the outer periphery of the element portion to seal the element portion. Further, by mounting an electronic device or a lighting device with a light-emitting device having such a structure, an electronic device or a lighting device with high reliability can be obtained.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kaoru Hatano, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura