Portion Of Housing Of Specific Materials Patents (Class 257/729)
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Patent number: 7566957Abstract: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.Type: GrantFiled: October 31, 2007Date of Patent: July 28, 2009Assignee: SAES Getters S.p.A.Inventor: Marco Amiotti
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Publication number: 20090184417Abstract: Disclosed are photosensitizers that include a polyol moiety covalently bonded to a fused aromatic moiety. Also disclosed is a method for improving UV laser ablation performance of a coating, such as a cationic UV curable coating, by incorporating an oxalyl-containing additive into the cationic UV curable or other coating. Oxalyl-containing sensitizers having the formula Q-O—C(O)—C(O)—O—R1, wherein Q represents a fused aromatic moiety and R1 is an alkyl or aryl group, are also disclosed, as are oxalyl-containing oxetane resins, oxalyl-containing polyester polyols, and cationic UV curable coating formulations that include oxalyl-containing additives.Type: ApplicationFiled: April 21, 2007Publication date: July 23, 2009Inventors: Dean C. Webster, Zhigang Chen
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Publication number: 20090179325Abstract: Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead.Type: ApplicationFiled: January 7, 2009Publication date: July 16, 2009Inventors: Sung-min Park, Keun-hyuk Lee, Seung-Won Lim
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Patent number: 7554196Abstract: A plastic package and to a semiconductor component including such a plastic package, as well as to a method for its production is disclosed. In one embodiment, the plastic package includes plastic outer faces, which include lower outer contact faces on a lower side of the plastic package and upper outer contact faces on an upper side, which are connected together via outer conductor tracks. The conductor tracks include conduction paths which are formed on exposed conducting deposits in the plastic package.Type: GrantFiled: October 11, 2005Date of Patent: June 30, 2009Assignee: Infineon Technologies AGInventors: Ulrich Bachmaier, Michael Bauer, Robert-Christian Hagen
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Publication number: 20090121347Abstract: Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.Type: ApplicationFiled: June 28, 2006Publication date: May 14, 2009Applicant: ROHM CO., LTD.Inventors: Masaki Kasai, Osamu Miyata
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Patent number: 7504670Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.Type: GrantFiled: June 7, 2006Date of Patent: March 17, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Satoshi Shiraishi, Yoichi Kazama
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Patent number: 7489032Abstract: A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.Type: GrantFiled: December 20, 2004Date of Patent: February 10, 2009Assignees: Casio Computer Co., Ltd., CMK CorporationInventor: Hiroyasu Jobetto
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Publication number: 20090001565Abstract: A MEMS device including a getter film formed inside a hermetic chamber provides stable performance of the MEMS device by electrically stabilizing the getter film. The MEMS device includes a movable portion and a fixed portion formed inside the hermetic chamber. The hermetic chamber is formed by a base material of the MEMS device and glass substrates and 32 having a cavity and cavities made therein. A part of any continuous getter film formed inside the hermetic chamber connects to only one of any one or a plurality of predetermined electrical potentials of the fixed portion and a ground potential of the fixed portion through the base material of the MEMS device.Type: ApplicationFiled: June 26, 2008Publication date: January 1, 2009Inventors: Tsuyoshi Takemoto, Hiroshi Nishida, Osamu Torayashiki, Takashi Ikeda, Ryuta Araki
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Publication number: 20090001564Abstract: Devices and methods for their formation, including electronic assemblies having a shape memory material structure, are described. In one embodiment, a device includes a package substrate and an electronic component coupled to the package substrate. The device also includes a shape memory material structure coupled to the package substrate. In one aspect of certain embodiments, the shape memory material structure is formed from a material selected to have a martensite to austenite transition temperature in the range of 50-300 degrees Celsius. In another aspect of certain embodiments, the shape memory material structure is positioned to extend around a periphery of the electronic component. Other embodiments are described and claimed.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Stewart Ongchin, King Gonzalez, Vadin Sherman, Stephen Tisdale, Xiaoqing Ma
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Publication number: 20080303140Abstract: To provide a semiconductor device which can increase reliability with respect to external force, especially pressing force, while the circuit size or the capacity of memory is maintained. A pair of structure bodies each having a stack of fibrous bodies of an organic compound or an inorganic compound, which includes a plurality of layers, especially three or more layers, is impregnated with an organic resin, and an element layer provided between the pair of structure bodies are included. The element layer and the structure body can be fixed to each other by heating and pressure bonding. Further, a layer for fixing the element layer and the structure body may be provided. Alternatively, the structure body fixed to an element layer can be formed in such a way that after a plurality of fibrous bodies is stacked over the element layer, the fibrous bodies are impregnated with an organic resin.Type: ApplicationFiled: May 29, 2008Publication date: December 11, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Eiji Sugiyama
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Patent number: 7439616Abstract: A silicon condenser microphone package includes a transducer unit, a substrate, and a cover. The substrate includes an upper surface transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and either the cover or the substrate includes an aperture.Type: GrantFiled: February 10, 2006Date of Patent: October 21, 2008Assignee: Knowles Electronics, LLCInventor: Anthony D. Minervini
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Patent number: 7436077Abstract: A semiconductor device includes a first surface faced to a mounting board when the semiconductor device is placed over the mounting board and a second surface opposed to the first surface. The semiconductor device also includes a position reference portion which is provided in an area including sides of the second surface and which has an optical reflection factor different from that of the mounting board.Type: GrantFiled: October 31, 2002Date of Patent: October 14, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Kiyoshi Hasegawa
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Patent number: 7427786Abstract: A diode device is disclosed, comprising a pair of electrodes separated by bellows. The corrugated walls of the bellows create a tortuous thermal pathway thereby reducing parasitic heat losses and increasing the device's efficiency. The bellows' also allow for a controlled environment to be sustained within the device. In a preferred embodiment the controlled environment is a vacuum. In one embodiment, a modified electrode for use in a diode device of the present invention is disclosed, in which indents are made on the surface of the electrode. In a further embodiment the bellows comprise shape memory alloys: previously deformed bellows are attached to the diode device and then grown to set the gap between the electrodes. In further embodiments the use of corrugation is applied to other parts of the diode device to elongate its thermal pathway and thereby increase its efficiency.Type: GrantFiled: January 24, 2007Date of Patent: September 23, 2008Assignee: Borealis Technical LimitedInventor: Isaiah Watas Cox
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Patent number: 7425758Abstract: Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed.Type: GrantFiled: August 28, 2006Date of Patent: September 16, 2008Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
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Patent number: 7425764Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Type: GrantFiled: August 17, 2007Date of Patent: September 16, 2008Inventor: Mou-Shiung Lin
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Publication number: 20080191344Abstract: An integrated circuit includes a substrate including an active area and a gas phase deposited packaging material encapsulating the active area.Type: ApplicationFiled: February 13, 2007Publication date: August 14, 2008Inventors: Louis Vervoot, Joachim Mahler
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Patent number: 7408259Abstract: A sheet to form a protective film for chips includes a release sheet and a protective film forming layer formed on a detachable surface of the release sheet. The protective film forming layer includes a thermosetting and/or energy ray-curable component and a binder polymer component.Type: GrantFiled: April 25, 2005Date of Patent: August 5, 2008Assignee: Lintec CorporationInventors: Hideo Senoo, Takashi Sugino, Osamu Yamazaki
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Patent number: 7405477Abstract: A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.Type: GrantFiled: December 1, 2005Date of Patent: July 29, 2008Assignee: Altera CorporationInventors: Yuming Tao, Jon M. Long, Anilkumar Raman Pannikkat
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Publication number: 20080157352Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventors: Shripad Gokhale, Kathy Wei Yan, Bijay S. Saha, Samir Pandey, Ngoc K. Dang, Munehiro Toyama
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Patent number: 7384698Abstract: A metal article intended for at least partially coating with a substance, which includes a metal solder, a plastic, a glass, or a ceramic. The metal article itself may include, in particular, connecting, supporting, or conducting components for an electronic component. The metal article has macroscopically smooth surface portions and a multiplicity of multiply curved nanopores in the region of at least one surface portion.Type: GrantFiled: November 12, 2004Date of Patent: June 10, 2008Assignee: Infineon Technologies AGInventors: Edmund Riedl, Wolfgang Schober
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Patent number: 7372142Abstract: A vertical conduction power electronic device package and corresponding assembly method comprising at least a metal frame suitable to house at least a plate or first semiconductor die having at least a first and a second conduction terminal on respective opposed sides of the first die. The first conduction terminal being in contact with said metal frame and comprising at least an intermediate frame arranged in contact with said second conduction terminal.Type: GrantFiled: May 31, 2005Date of Patent: May 13, 2008Assignee: STMicroelectronics, S.r.l.Inventors: Maurizio Maria Ferrara, Angelo Magri, Agatino Minotti
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Patent number: 7358605Abstract: A heat dissipation structure for an electronic device comprises a plurality of covering members made of a compressed wooden material, and a metal heat dissipation frame held between the covering members, and a portion of the heat dissipation frame is exposed outside of the electronic device.Type: GrantFiled: February 22, 2005Date of Patent: April 15, 2008Assignee: Olympus CorporationInventor: Tatsuya Suzuki
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Publication number: 20080073780Abstract: A semiconductor device includes a semiconductor element including a semiconductor substrate having an element region, a laminated film formed on the semiconductor substrate and including a low dielectric constant insulating film, and a laser-machined groove provided to cut at least the low dielectric constant insulating film. The semiconductor element is connected to a wiring substrate via a bump electrode. An underfill material is filled between the semiconductor element and the wiring substrate. The fillet length Y (mm) of the underfill material satisfies a condition of Y>?0.233X+3.5 (where X>0, and Y>0) with respect to the width X (?m) of the laser-machined groove.Type: ApplicationFiled: September 20, 2007Publication date: March 27, 2008Inventor: Yoshihisa Imori
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Publication number: 20080042263Abstract: A reinforced semiconductor package (500, 700) with a stiffener (400, 600) is provided. The stiffener is composed of an inner ring (410) disposed on the upper surface (512) of a substrate (510) and surrounding a semiconductor chip (520), and an outer ring (420) also disposed on the upper surface of the substrate but surrounding the inner ring. The inner ring and the outer ring are connected with each other by means of at least one tie bar (430), and cooperatively cover a majority portion of the upper surface of the substrate. Accordingly, the strength and rigidity of the substrate of the present semiconductor package can be reinforced to efficiently prevent warpage thereof.Type: ApplicationFiled: August 14, 2007Publication date: February 21, 2008Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tong-hong Wang, Ching-chun Wang
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Patent number: 7332809Abstract: A press mold for fabricating a glass substrate, the glass substrate comprising a substrate; and a terrace-shaped flat portion formed on the substrate and having a grooved portion formed therein, is characterized in that the press mold comprises a top mold and a bottom mold; at least one of the top mold and the bottom mold having an indented portion formed therein so as to correspond to the terrace-shaped flat portion, the indented portion having an entire periphery surrounded by a mold reference surface.Type: GrantFiled: September 26, 2005Date of Patent: February 19, 2008Assignee: Asahi Glass Company, LimitedInventors: Takeshi Shimazaki, Masatoshi Ohyama, Hiroshi Wakatsuki
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Patent number: 7329861Abstract: An integrally packaged imaging module includes an integrated circuit (IC), including an image sensing device formed on a semiconductor substrate, and wafer level packaging enclosing the IC. The wafer level packaging includes a transparent enclosure portion adapted to permit image acquisition of an image by the image sensing device over a desired range of wavelengths, and a first spacing structure providing a cavity between an inner surface of the transparent enclosure portion and the image sensing device. A depth of the cavity is configurable along an axis perpendicular to the semiconductor substrate to control a distance between an outer surface of the transparent enclosure portion and the image sensing device.Type: GrantFiled: October 14, 2003Date of Patent: February 12, 2008Assignee: Micron Technology, Inc.Inventors: Guolin Ma, Bahram Afshari
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Patent number: 7323238Abstract: In a printed board having a land as an electrode, a colored thermoplastic resin film is arranged on a land forming surface of a thermoplastic resin member so as to set a difference in light reflectivity between the land and the colored thermoplastic resin film, to be greater than that between the land and the thermoplastic resin member. An opening portion is provided in the colored thermoplastic resin film so that at least a part of the land is exposed from the opening portion. Because the colored thermoplastic resin film is positioned on the circumference portion of the opening portion, the difference in light reflectivity of the land with respect to its circumference portion can be effectively increased. As a result, a recognition ratio of the land can be effectively improved.Type: GrantFiled: September 22, 2005Date of Patent: January 29, 2008Assignees: DENSO Corporation, NEC Electronics CorporationInventors: Koji Kondo, Ryohei Kataoka, Tomohiro Yokochi, Makoto Nakagoshi, Tadashi Murai, Akimori Hayashi, Katsunobu Suzuki
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Patent number: 7301224Abstract: A surface acoustic wave device has a SAW device element 10 and a package 20 housing the SAW device element. The package includes a resin substrate 20 having metal patterns 21 and 22 formed on both surfaces thereof, and a resin cap 32. The SAW device element is mounted on one of the metal patterns of the resin substrate. The resin cap is adhered to the resin substrate to cover the SAW device element. The surfaces of the resin substrate are flush with corresponding end surfaces of the resin cap.Type: GrantFiled: August 29, 2005Date of Patent: November 27, 2007Assignee: Fujitsu Media Devices LimitedInventors: Naoyuki Mishima, Takumi Kooriike
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Patent number: 7298039Abstract: In order to provide a low-cost and high heat-radiating electronic circuit device featuring high compactness, little warpage, high air tightness, high moldability, high mass productivity, high reliability against thermal shocks, and high oil-proof reliability, a module structure made by packing a whole multi-layer circuit board which connects a semiconductor operating element, semiconductor memory elements, and passive elements thereon and part of a supporting material on which said multi-layer circuit board is placed into a single package by transfer-molding; wherein said multi-layer circuit board and said supporting material are bonded together with a compound metallic material made up from copper oxide and at least one metal selected from a set of gold, silver, and copper.Type: GrantFiled: August 4, 2004Date of Patent: November 20, 2007Assignee: Hitachi, Ltd.Inventors: Nobutake Tsuyuno, Toshiaki Ishii, Toshiya Satoh, Mitsuhiro Masuda
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Patent number: 7298046Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.Type: GrantFiled: January 10, 2003Date of Patent: November 20, 2007Assignee: Kyocera America, Inc.Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
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Patent number: 7279239Abstract: In a laminate product formed by an organic member and/or an inorganic member, high strength adhesion between the organic member and the inorganic member is achieved by providing an adhesion layer which includes amorphous carbon nitride (a-CNx:H) particularly between the organic member and the inorganic member. Further, in order to protect a laminate product formed by an organic member and/or an inorganic member, for example, an organic electronic element including an organic compound layer, such as an organic electroluminescence element, a protective film including at least amorphous carbon nitride and a protective layer having a laminate structure formed by sandwiching a vapor deposition inorganic film between plasma polymerized films are used. Thus, a protective film which is optimum to an organic electronic element, having high bending stress resistance, high shielding effect against moisture and oxygen existing in the air, and excellent resistance to high temperature and high humidity can be provided.Type: GrantFiled: August 7, 2003Date of Patent: October 9, 2007Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Kunio Akedo, Koji Noda, Atsushi Miura, Hisayoshi Fujikawa, Yasunori Taga
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Patent number: 7253029Abstract: A process for preparing an electronic package comprising: (a) providing a ceramic housing defining an internal cavity for receiving a micro device and having one or more interface portions; (b) treating the housing to form a tungsten layer on the interface portions; and (c) overlaying a palladium layer on the tungsten layer.Type: GrantFiled: March 10, 2004Date of Patent: August 7, 2007Assignee: M/A-Com, Inc.Inventors: Carl Geisler, Dennis O'Keefe
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Patent number: 7247940Abstract: An optoelectronic device, comprising a package body (57) and at least one semiconductor chip (50) arranged on the package body (57). The surface of the package body (57) has a metallized subregion (15) and a non-metallized subregion (20). The package body (57) includes at least two different plastics (53, 54), one of the plastics being non-metallizable (54) and this plastic determining the non-metallized subregion (20). A method for producing such components and a method for the patterned metallization of a plastic-containing body are also provided.Type: GrantFiled: March 1, 2004Date of Patent: July 24, 2007Assignee: Osram Opto Semiconductor GmbHInventors: Thomas Höfer, Herbert Brunner, Frank Möllmer, Günter Waitl, Rainer Sewald, Markus Zeiler
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Patent number: 7217999Abstract: In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.Type: GrantFiled: October 4, 2000Date of Patent: May 15, 2007Assignee: NEC Electronics CorporationInventor: Hirokazu Honda
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Patent number: 7208827Abstract: A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.Type: GrantFiled: December 13, 2000Date of Patent: April 24, 2007Assignee: Infineon Technologies AGInventors: Christian Hauser, Simon Muff, Jens Pohl, Friedrich Wanninger
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Patent number: 7192870Abstract: A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the semiconductor chip opposite from the solid device.Type: GrantFiled: May 5, 2005Date of Patent: March 20, 2007Assignee: Rohm Co., Ltd.Inventors: Kazutaka Shibata, Junji Oka, Yasumasa Kasuya
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Patent number: 7189449Abstract: In a metal/ceramic bonding substrate 10 wherein a circuit forming metal plate 14 is bonded to one side of a ceramic substrate 12 and a radiating metal base plate 16 is bonded to the other side thereof, a difference in level is provided along the entire circumference of the bonding surface of the ceramic substrate 12 to the metal base plate 16. The difference in level is provided by forming at least one of a rising portion 16a and a groove portion 116b on and in the metal base plate 16.Type: GrantFiled: October 12, 2004Date of Patent: March 13, 2007Assignee: Dowa Mining Co., Ltd.Inventors: Hideyo Osanai, Takayuki Takahashi, Makoto Namioka
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Patent number: 7180197Abstract: The present invention provides a semiconductor device having a structure that can be mounted on a wiring substrate, as for the semiconductor device formed over a thin film-thickness substrate, a film-shaped substrate, or a sheet-like substrate. In addition, the present invention provides a method for manufacturing a semiconductor device that is capable of raising a reliability of mounting on a wiring substrate. One feature of the present invention is to bond a semiconductor element formed on a substrate having isolation to a member that a conductive film is formed via a medium having an anisotropic conductivity.Type: GrantFiled: September 29, 2004Date of Patent: February 20, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuo Nishi, Hiroki Adachi, Naoto Kusumoto, Yuusuke Sugawara, Hidekazu Takahashi, Daiki Yamada, Yoshikazu Hiura
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Patent number: 7176567Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.Type: GrantFiled: July 6, 2005Date of Patent: February 13, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
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Patent number: 7173325Abstract: Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.Type: GrantFiled: August 30, 2004Date of Patent: February 6, 2007Assignee: C-Core Technologies, Inc.Inventors: Kalu K. Vasoya, Bharat M. Mangrolia
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Patent number: 7166910Abstract: A silicon condenser microphone package is disclosed. The silicon condenser microphone package comprises a transducer unit, a substrate, and a cover. The substrate includes an upper surface having a recess formed therein. The transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and includes an aperture.Type: GrantFiled: June 21, 2001Date of Patent: January 23, 2007Assignee: Knowles Electronics LLCInventor: Anthony D. Minervini
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Patent number: 7145230Abstract: The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.Type: GrantFiled: December 30, 2004Date of Patent: December 5, 2006Assignee: NEC Electronics CorporationInventor: Futoshi Hosoya
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Patent number: 7122243Abstract: There is provided a metal/ceramic bonding substrate having improved reliability to heat cycles, and a method for producing the same. In a metal/ceramic bonding substrate 10 wherein a circuit forming metal plate 14 is bonded to one side of a ceramic substrate 12 and a radiating metal base plate 16 is bonded to the other side thereof, at least part of the ceramic substrate 12 is embedded in the metal base plate 16. The ceramic substrate 12 is arranged substantially in parallel to the metal base member 16.Type: GrantFiled: October 19, 2004Date of Patent: October 17, 2006Assignee: Dowa Mining Co., Ltd.Inventors: Hideyo Osanai, Takayuki Takahashi, Makoto Namioka
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Patent number: 7115989Abstract: An adhesive sheet for producing a semiconductor device, which includes a base layer and an adhesive layer and is used in the process for producing the semiconductor device including the step of sealing a semiconductor element connected to an electric conductor with a sealing resin on the adhesive layer, wherein the adhesive layer of the adhesive sheet includes a rubber component and an epoxy resin component and the ratio of the rubber component in organic materials in the adhesive layer is from 5 to 40% by weight. According to this adhesive sheet, pollution is not caused by silicon components, a sufficient elastic modulus can be kept even at high temperature, and a problem that paste remains is not easily caused.Type: GrantFiled: August 23, 2004Date of Patent: October 3, 2006Assignee: Nitto Denko CorporationInventor: Kazuhito Hosokawa
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Patent number: 7109575Abstract: Provided are a flexible film package module and a method of manufacturing the same that can be adapted for manufacture at lower cost and/or to adapt the characteristics of the flexible film package module for specific applications. The lower-cost flexible film package module includes a tape film that combines both a first insulating substrate, typically formed from a higher-cost polyimide material, and a second insulating substrate, typically formed from an insulating material or materials that are less expensive and/or provide modified performance when compared with the first insulating material. Both the first and second substrates will include complementary circuit patterns that will be electrically and physically connected to allow the composite substrate to function as a unitary substrate. The first and second substrates will also include connection regions that may be adapted for connection to printed circuit boards and/or electronic devices such as liquid crystal displays.Type: GrantFiled: June 8, 2004Date of Patent: September 19, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Sa-Yoon Kang, Dong-Han Kim, Ye-Chung Chung
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Patent number: 7102228Abstract: A semiconductor device comprising a substrate, a semiconductor element mounted on the substrate, an inner annular stiffener provided on the substrate in an outer side of the semiconductor element, and an outer annular stiffener provided on the substrate in an outer side of the inner annular stiffener. The inner annular stiffener and the outer annular stiffener are made of different materials. Particularly, the thermal expansion coefficient of the inner annular stiffener is selected to be smaller than that of the substrate, and the thermal expansion coefficient of the outer annular stiffener is selected to be larger than that of the substrate. The amount of deformation of the substrate is thus decreased.Type: GrantFiled: March 25, 2005Date of Patent: September 5, 2006Assignee: Fujitsu LimitedInventor: Takashi Kanda
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Patent number: 7081661Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.Type: GrantFiled: March 13, 2002Date of Patent: July 25, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa
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Patent number: 7078804Abstract: A micro-electro-mechanical system (MEMS) package with a side sealing member and a method of manufacturing the package are disclosed. In the MEMS package and method of the present invention, a sealing member is formed on a side surface of a lid glass that is mounted on a spacer surrounding MEMS elements provided on a base substrate and covers the MEMS elements, so that the sealing member hermetically seals the MEMS elements from the external environment.Type: GrantFiled: September 28, 2004Date of Patent: July 18, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Suk-Kee Hong, Yeong-Gyu Lee, Heung-Woo Park
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Patent number: 7071548Abstract: An article comprises a semiconductor substrate and a coating mixture on the semiconductor substrate. The coating mixture Is comprised of adhesion promoter and photopolymer. The adhesion promoter contains ?-amino propyltriethoxysilane in organic solution.Type: GrantFiled: October 30, 2003Date of Patent: July 4, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Albert Hua Jeans, Ping Mei
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Patent number: 7053494Abstract: A semiconductor device includes a film substrate having an interconnection pattern provided on a surface thereof, a semiconductor chip mounted on the film substrate and having an electrode provided on a surface thereof, and an insulative resin portion provided between the film substrate and the semiconductor chip, the resin portion having been formed by applying an insulative resin on at least one of the film substrate and the semiconductor chip and filling a space defined between the film substrate and the semiconductor chip with the resin when the semiconductor chip is mounted on the film substrate, wherein the interconnection pattern has a projection which has a sectional shape tapered toward the electrode of the semiconductor chip and intrudes in the electrode thereby to be electrically connected to the electrode.Type: GrantFiled: May 6, 2004Date of Patent: May 30, 2006Assignee: Sharp Kabushiki KaishaInventor: Toshiharu Seko