Portion Of Housing Of Specific Materials Patents (Class 257/729)
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Patent number: 7042075Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.Type: GrantFiled: December 19, 2002Date of Patent: May 9, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: John Liebeskind
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Patent number: 7038327Abstract: Enhanced ACF bonding pads for use in conjunction with anisotropic conductive film (ACF) in electronic devices, such as, liquid crystal display panels and plasma display panels have at least two finger-like portions. Such bonding pads, typically provided on a flexible wiring lead, when bonded to other metal structures via the ACF film, make better electrical contact with the other metal structures because the spaces between the finger-like portions of the improved bonding pads allow the ACF film's binder material to reside between the finger-like portions preventing the bonding pad metal in the center region of the bonding pad from separating away from the other metal structures.Type: GrantFiled: February 26, 2004Date of Patent: May 2, 2006Assignee: AU Optronics Corp.Inventors: Sheng-Hsiung Ho, Chuan-Mao Wei, Ke-Feng Lin
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Patent number: 6984867Abstract: A magnetic memory device having a packaged magnetic memory chip is disclosed, which comprises a package structure including a magnetic memory chip, and a magnetic guide of a high-permeability magnetic material, forming a structural member of the package structure.Type: GrantFiled: September 4, 2003Date of Patent: January 10, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Kentaro Nakajima
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Patent number: 6982484Abstract: The present invention relates to an adhesive-backed tape for semiconductors which is characterized in that it is composed of a laminate of an insulating film layer having the following characteristics (1) and (2) and at least one adhesive agent layer in the semi-cured state. (1) The coefficient of linear expansion in the film transverse direction (TD) at 50–200° C. is 17–30 ppm/° C. (2) The tensile modulus of elasticity is 6–12 GPa By means of this construction the present invention can provide, on an industrial basis, an adhesive-backed tape suitable for producing semiconductor devices, together with copper-clad laminates, semiconductor connecting substrates and semiconductor devices employing said tape, and it enables, the reliability of semiconductor devices for high density mounting to be enhanced.Type: GrantFiled: August 22, 2001Date of Patent: January 3, 2006Assignee: Toray Industries, Inc.Inventors: Mikihiro Ogura, Syouji Kigoshi, Masami Tokunaga, Yasuaki Tsutsumi, Ryuichi Kamei, Ken Shimizu
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Patent number: 6972486Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier for temporarily mounting a non-wafer form device. The low-profile carrier holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses which are machined or otherwise formed in the low-profile carrier.Type: GrantFiled: September 12, 2003Date of Patent: December 6, 2005Assignee: Atmel CorporationInventors: Ken M. Lam, Julius A. Kovats
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Patent number: 6964918Abstract: A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers are deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.Type: GrantFiled: January 15, 2004Date of Patent: November 15, 2005Assignee: Asat Ltd.Inventors: Chun Ho Fan, Kwok Cheung Tsang
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Patent number: 6963131Abstract: The present invention relates to an integrated circuit system with at least one integrated circuit, a cooling body to dissipate the heat generated by the integrated circuit and a latent heat storage module having a latent heat storage medium. The latent heat storage module is thermally connected to the cooling body in order to temporarily store the heat generated by the integrated circuit and to convey it to the cooling body. The integrated circuit has at least one semiconductor component which is assembled on a substrate and the substrate is in direct thermal contact with the latent heat storage module.Type: GrantFiled: October 24, 2003Date of Patent: November 8, 2005Assignee: Tyco Electronics AMP GmbHInventors: Michael Frisch, Ralf Ehler
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Patent number: 6958446Abstract: A solder joint or seal attaching components having dissimilar coefficients of thermal expansion is made thin (e.g., less than 20 ?m and preferably about 5 ?m) and of a solder such as an indium-based solder that has a tendency to creep. The solder is toroidal or otherwise shaped to avoid tensile stress in the solder. Axial shearing stress in the solder causes reversible creep without causing failure of the joint or seal. In one embodiment, a toroidal solder seal has a diameter, a footprint, and a thickness in approximate proportions of 5000:200:1.Type: GrantFiled: April 17, 2002Date of Patent: October 25, 2005Assignee: Agilent Technologies, Inc.Inventors: Giles Humpston, Yoshikatsu Ichimura, Nancy M. Mar, Daniel J. Miller, Michael J. Nystrom, Heidi L. Reynolds, Gary R. Trott
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Patent number: 6930398Abstract: A package structure for optical image sensing devices is disclosed. The package structure includes an image sensing integrated circuit chip having a light receiving side and a backside. The image sensing integrated circuit chip has a light sensing area on the light receiving side. A plurality of light sensing devices are arranged in the light sensing area for converting incident light into electrical signals. A plurality of bonding pads are arranged along one or two sides of the light sensing area. Black sealing glue is asymmetrically coated on the outskirts of the light sensing area. The black sealing glue has at least two coating widths. A glass lid is glued over the light sensing area with the sealing glue.Type: GrantFiled: March 24, 2004Date of Patent: August 16, 2005Assignee: United Microelectronics Corp.Inventors: Cheng-Kuang Sun, Kuang-Chih Cheng, Kuang-Shin Lee
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Patent number: 6911605Abstract: In order to provide low-cost, long fatigue life flexible printed circuit, low profile electrolytic foil is used as copper foil for a circuit 3 of the flexible printed circuit 10. Crack which does not penetrate the copper foil should preferably be formed on the low profile electrolytic foil. For methods to form cracks on the low profile electrolytic foil, methods such as pre-bending and etching can be employed. Due to the weakness of the low profile electrolytic foil, the base film 1, the cover layer 5, and the bonding agent 2, 4 which are disposed on the both sides of the low profile electrolytic foil should preferably be plastic film of which elasticity ratio is equal to 108 Pa or more.Type: GrantFiled: April 3, 2002Date of Patent: June 28, 2005Assignee: Fujikura Ltd.Inventors: Kenichi Okada, Nobuo Tanabe
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Patent number: 6906412Abstract: A sensor package P is a surface-mounted sensor package which is adapted to be mounted on a printed board 200. The sensor package P includes a case 1 for accommodating a semiconductor acceleration sensor chip 100 having output pads 101. The case has a bottom wall 10, which is divided into a center area 10a for supporting the sensor chip 100 and a peripheral area 10b. Output electrodes 15 to be connected to the output pads 101 are formed on external surfaces of the peripheral area. These output electrodes 15 are soldered to the printed board 200 for electrical connection between the sensor chip and an electric circuit of the printed board as well as for holding the sensor package physically on the printed board. The feature of the present invention resides in that grooves 12 are formed in an interior surface of the bottom wall 10 between the center area 10a and the peripheral area 10b.Type: GrantFiled: May 29, 2003Date of Patent: June 14, 2005Assignee: Matsushita Electric Works, Ltd.Inventors: Eiichi Furukubo, Masami Hori, Kazuya Nohara
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Patent number: 6906396Abstract: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The thickness of the shielding can be tailored to a customer's specific needs, and can be applied after all high temperature processing, such that a degaussed shield can be provided despite use of strong magnetic fields during high temperature processing, which fields are employed to maintain pinned magnetic layers within the integrated circuit.Type: GrantFiled: January 15, 2002Date of Patent: June 14, 2005Assignee: Micron Technology, Inc.Inventors: Mark E. Tuttle, James G. Deak
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Patent number: 6888239Abstract: The invention provides a ceramic package, a ceramic package having such a sealing structure and a fabrication method of thereof. In the ceramic package, a wall layer made of a plurality of laminated ceramic sheets and having a cavity formed in a central portion thereof is stacked on a top of a base layer made of a plurality of laminated ceramic sheets. A metal layer is coated on the wall layer around the cavity to expose an outer peripheral portion of the wall layer. A glass layer is coated on the outer peripheral portion of the wall layer, which is not coated with the metal layer, to contact with the metal layer. A lid is attached on the metal layer to seal the cavity. The glass layer is coated around the metal layer, which is attached on the ceramic wall layer around the cavity, to reinforce the bonding force between the metal layer and the underlying ceramic wall layer thereby potentially preventing creation of cracks between the metal layer and the underlying ceramic wall layer.Type: GrantFiled: February 27, 2004Date of Patent: May 3, 2005Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Yong Wook Kim
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Patent number: 6879038Abstract: An optically transparent, hermetic coating is locally formed on die and other components already assembled in an existing nonhermetic structure. The local hermetic sealing of an OSA includes providing an OSA having at least one exposed optoelectronic component, and providing a paralene source. The method provides for positioning a mask between the paralene source and the OSA, the mask including an opening aligned with a first region of the OSA. The first region includes at least one of the exposed optoelectronic components. The paralene source is then caused to generate paralene such that a permanent paralene coating is deposited through the opening and on the first region of the OSA. The permanent paralene coating essentially hermetically seals the first region. The permanent paralene coating is chosen to be transparent to the wavelength of light emitted and/or used in the optical sub-assembly.Type: GrantFiled: March 12, 2003Date of Patent: April 12, 2005Assignee: Optical Communication Products, Inc.Inventor: William Kit Dean
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Patent number: 6873033Abstract: A coin-shaped IC tag which can be endowed with a predetermined weight is described. The coin-shaped IC tag ensures a normal operation and affords a satisfactory feeling of weightiness as a value medium. Methods of manufacturing the coin-shaped IC tag are also described. The coin-shaped IC tag comprises an IC tag core. The IC tag core comprises an IC packaging base member including a base and an electronic circuit for communicating data and for recording data, the electronic circuit mounted on the base. The IC tag core also comprises a high specific gravity resin layer joined to the IC packaging base member.Type: GrantFiled: August 8, 2003Date of Patent: March 29, 2005Assignee: Omron CorporationInventors: Wakahiro Kawai, Yoshiki Iwamae
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Patent number: 6873042Abstract: Power semiconductor devices, and particularly a power semiconductor device which contains a plurality of power semiconductor elements. The power semiconductor device capable of reducing differences in impedance caused by differences in length among wire interconnections, facilitating the electric connection between main circuit terminals and the outside, and lightening restrictions on the number and layout of the power semiconductor elements installed. In the power semiconductor device, a rectangular-loop-shaped interconnection board is disposed above a bottom substrate to cover an area above edges of the bottom substrate, with an opening above the center part of the bottom substrate. A main collector electrode terminal and a main emitter electrode terminal pass through the opening to protrude from an opening of a resin case so that they can be electrically connected to the outside.Type: GrantFiled: April 2, 2001Date of Patent: March 29, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazufumi Ishii, Shinichi Iura
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Patent number: 6861763Abstract: A method for forming packaged substrates includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the active surface of the substrate which includes one or more flip-chip dice. In addition, the invention encompasses forming a similar layer on a second substrate to be joined to the first substrate. Contact pads of the second substrate are exposed through the layer thereon to facilitate joining of the two substrates. Semiconductor devices formed by the method are also disclosed.Type: GrantFiled: December 11, 2002Date of Patent: March 1, 2005Assignee: Micron Technology, Inc.Inventor: Salman Akram
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Patent number: 6855418Abstract: A resin tie bar 1A is formed from a base material 10, 11 of a heat-resistant resin whose melting point is higher than the temperature during resin molding and an insulative adhesive layer 12 on the base material 10, 11 and formed from an insulative adhesive agent that may or may not be removable prior to resin molding depending upon its composition. The resin tie bar 1A is applied to the surface of the leads 22 of a lead frame, and resin molding is then performed, during which the resin tie bar 1A is pressed by a heated mold 3, which softens the insulative adhesive agent of the resin tie bar 1A and pushes it into the gaps 23 between the leads 22 of the lead frame. Thus the resin tie bar 1A can be easily formed into a shape that is favorable for the leads 22 of the lead frame.Type: GrantFiled: May 17, 2002Date of Patent: February 15, 2005Assignee: LINTEC CorporationInventors: Osamu Yamazaki, Hideo Senoo, Kazuyoshi Ebe
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Patent number: 6853049Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.Type: GrantFiled: March 13, 2002Date of Patent: February 8, 2005Assignee: Matrix Semiconductor, Inc.Inventor: S. Brad Herner
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Patent number: 6847115Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.Type: GrantFiled: September 6, 2001Date of Patent: January 25, 2005Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria
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Patent number: 6844632Abstract: In a semiconductor pressure sensor device comprising a housing (1) having a cavity (3), a semiconductor sensor chip (2) mounted within the cavity, leads (4) for conveying pressure detection signals, and bonding wires (6) electrically connecting the sensor chip and the leads, a sensitive portion (2a) of sensor chip (2), leads (4) and bonding wires (6) are covered with an electrically insulating fluorochemical gel material which has a penetration of 30-60 according to JIS K2220, a Tg of up to ?45° C., and a degree of saturation swelling in gasoline at 23° C. of up to 7% by weight. The sensor device is improved in operation reliability and durability life.Type: GrantFiled: July 9, 2003Date of Patent: January 18, 2005Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Mikio Shiono, Kenichi Fukuda
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Patent number: 6838748Abstract: A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.Type: GrantFiled: May 9, 2003Date of Patent: January 4, 2005Assignee: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Yoshihide Iwazaki, Shinji Suminoe
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Publication number: 20040247949Abstract: In a laminate product formed by an organic member and/or an inorganic member, high strength adhesion between the organic member and the inorganic member is achieved by providing an adhesion layer which includes amorphous carbon nitride (a-CNx:H) particularly between the organic member and the inorganic member. Further, in order to protect a laminate product formed by an organic member and/or an inorganic member, for example, an organic electronic element including an organic compound layer, such as an organic electroluminescence element, a protective film including at least amorphous carbon nitride and a protective layer having a laminate structure formed by sandwiching a vapor deposition inorganic film between plasma polymerized films are used. Thus, a protective film which is optimum to an organic electronic element, having high bending stress resistance, high shielding effect against moisture and oxygen existing in the air, and excellent resistance to high temperature and high humidity can be provided.Type: ApplicationFiled: April 12, 2004Publication date: December 9, 2004Inventors: Kunio Akedo, Koji Noda, Atsushi Miura, Hisayoshi Fujikawa, Yasunori Taga
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Patent number: 6825558Abstract: The present invention relates to a carrier module for micro-BGA (&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.Type: GrantFiled: February 26, 2003Date of Patent: November 30, 2004Assignee: Mirae CorporationInventor: Sang Jae Yun
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Patent number: 6822265Abstract: A light emitting element is disclosed. When the light emitting diode is used as a backlight source for a liquid crystal display, the distance from the light emitting element 25 to the light receiving surface of the light guide plate 11 is reduced to increase the light spreading angle &thgr;2 of the light introduced from the light emitting element 25 into the light guide plate 11 and also increase the amount of light entering the light guide plate 11, thus enhancing the level of brightness of the liquid crystal display. The light emitting diode comprises: a mother board 8 having an opening 9; a pair of electrodes 23, 24 arranged on one surface of the mother board 8; a light guide plate 11 arranged on the other surface of the mother board 8; a light emitting element 25 arranged in the opening 9 of the mother board 8 and mounted to one of the pair of electrodes 23, 24; and a positioning means 30 mounted on the one electrode to position the light emitting element 25 close to the light guide plate 11.Type: GrantFiled: June 5, 2002Date of Patent: November 23, 2004Assignee: Citizen Electronics Co., Ltd.Inventors: Koichi Fukasawa, Hirohiko Ishii
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Patent number: 6822326Abstract: A method for providing encapsulation of an electronic device which obtains an encapsulating member configured to enclose the electronic device, prepares a surface of the encapsulating member for non-adhesive direct bonding, prepares a surface of a device carrier including the electronic device for non-adhesive direct bonding, and bonds the prepared surface of the encapsulating member to the prepared surface of the device carrier to form an encapsulation of the electronic device. As such, an encapsulated electronic device results which includes the device carrier having a first bonding region encompassing the electronic device, includes the encapsulating member having at least one relief preventing contact between the electronic device and the encapsulating member and having a second bonding region bonded to the first bonding region of the device carrier, and includes a non-adhesive direct bond formed between the first and second bonding regions thereby to form an encapsulation of the electronic device.Type: GrantFiled: September 25, 2002Date of Patent: November 23, 2004Assignee: ZiptronixInventors: Paul M. Enquist, Qin-Yi Tong, Gaius Gillman Fountain, Jr., Robert Markunas
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Patent number: 6822320Abstract: An electrically conductive article such as a sheet having holes therein is coated with a dielectric polymer using a multi-stage electrophoretic deposition process. A coating of uncured polymer is deposited electrophoretically and then cured. After the first polymer is cured, the part is subject to a further electrophoretic deposition process and further curing. Use of a second electrophoretic deposition step allows effective coating of parts having small holes without plugging the holes. The coated parts may be used as microelectronic connection components such as chip carriers used in packaging semiconductor chips.Type: GrantFiled: September 25, 2002Date of Patent: November 23, 2004Assignee: Tessera, Inc.Inventor: Belgacem Haba
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Patent number: 6822880Abstract: A thin film hydrogen getter and EMI shielding are provided for protecting GaAs circuitry sealed in an hermetic package. The thin film getter comprises a multilayer metal film that is deposited by vacuum evaporation techniques onto a conductive metal, such as aluminum or copper, that serves as the EMI shielding. The conductive layer is first formed on an interior surface. The multilayer hydrogen getter film comprises (1) a titanium film and (2) a palladium film that is deposited on the titanium film. Both the titanium and the palladium are deposited during the same coating process run, thereby preventing the titanium from being oxidized. The palladium continues to prevent the titanium from being oxidized once the getter is exposed to the atmosphere. However, hydrogen is easily able to diffuse through the palladium into the titanium where it is chemically bound up, since palladium is highly permeable to hydrogen.Type: GrantFiled: November 25, 2003Date of Patent: November 23, 2004Assignee: Raytheon CompanyInventors: Alan L. Kovacs, Matthew H. Peter, Kurt S. Ketola, Jacques F. Linder
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Patent number: 6818979Abstract: A high-frequency semiconductor device is provided with a ceramic substrate, an element group including semiconductor elements and passive components mounted onto a bottom portion of the ceramic substrate, and a composite resin material layer formed on the bottom portion of the ceramic substrate so as to bury the element group. The composite resin material layer is formed by a composite resin material including an epoxy resin and an inorganic filler material, and has a flat bottom surface on which electrodes for connecting to the outside are formed. As packaging of a structure in which the receiving system and the transmitting system are formed in a single unit, such as an RF module, the high-frequency semiconductor device achieves a small size, a high mounting density, and excellent heat release properties.Type: GrantFiled: August 4, 2003Date of Patent: November 16, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa, Seiichi Nakatani
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Patent number: 6815810Abstract: A high-frequency semiconductor device is provided with a ceramic substrate, an element group including semiconductor elements and passive components mounted onto a bottom portion of the ceramic substrate, and a composite resin material layer formed on the bottom portion of the ceramic substrate so as to bury the element group. The composite resin material layer is formed by a composite resin material including an epoxy resin and an inorganic filler material, and has a flat bottom surface on which electrodes for connecting to the outside are formed. As packaging of a structure in which the receiving system and the transmitting system are formed in a single unit, such as an RF module, the high-frequency semiconductor device achieves a small size, a high mounting density, and excellent heat release properties.Type: GrantFiled: October 15, 2002Date of Patent: November 9, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa, Seiichi Nakatani
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Patent number: 6815253Abstract: Stereolithographically fabricated conductive elements and semiconductor device components and assemblies including these conductive elements. The conductive elements may have multiple superimposed, contiguous, mutually adhered layers of conductive material. In semiconductor device assemblies, the stereolithographically fabricated conductive elements may be used to electrically connect different components to one another. The conductive elements may also be used as the conductive traces and vias on circuit boards. The stereolithographically fabricated conductive elements are also useful for rerouting the bond pad locations of a semiconductor die, such as in chip-scale packages.Type: GrantFiled: December 31, 2002Date of Patent: November 9, 2004Assignee: Micron Technology, Inc.Inventor: Vernon M. Williams
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Patent number: 6815808Abstract: The present invention comprises a first main face (22a) on the surface side of a substrate (21a). An island portion (26) is formed on the first main face (22a) and a semiconductor chip (29), etc. are adhered onto the first main face (22a). The semiconductor chip (29), etc. are sealed in a hollow space made by a column portion (23) and a transparent glass plate (36). Then, the column portion (23) and the glass plate (36) are adhered by the light-shielding adhesive resin made of epoxy resin. Accordingly, there can be provided the semiconductor device and a method of manufacturing the same, which can prevent the direct incidence of the light onto the semiconductor chip (29) and the degradation of the characteristic of the semiconductor chip (29) can be suppressed.Type: GrantFiled: September 26, 2001Date of Patent: November 9, 2004Assignee: Sanyo Electric, Co., Ltd.Inventors: Haruo Hyodo, Shigeo Kimura, Yasuhiro Takano
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Patent number: 6803656Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.Type: GrantFiled: August 13, 2001Date of Patent: October 12, 2004Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Walter L. Moden, Larry D. Kinsman
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Patent number: 6791162Abstract: A unit cell is disclosed that facilitates the creation of a layout of at least a portion of a microelectromechanical system. The unit cell includes a plurality of electrical traces. Some of these electrical traces pass through the unit cell. Other electrical traces extend only part way through the unit cell. At least certain boundary conditions exist for the unit cell that allow the same to be tiled in a row and in a manner that results in adjacently disposed unit cells in the row being electrically interconnected in the desired manner.Type: GrantFiled: March 16, 2002Date of Patent: September 14, 2004Assignee: MEMX, Inc.Inventor: Samuel Lee Miller
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Patent number: 6784765Abstract: A mulitlayer ceramic device improves device functionality, reduces overall device size and profile, makes manufacturing easier, and improves reliability. A first ceramic layer 1 has a first multilayer circuit pattern 2 electrically connected through via holes 3. A second ceramic layer 2 also has a second multilayer circuit pattern 2 electrically connected through via holes 3. A thermosetting resin sheet 17 is disposed between the first and second ceramic layers. The thermosetting resin sheet has through holes filled with a conductive paste for electrically connecting one of multiple circuit pattern layers in the first ceramic layer with one of multiple circuit pattern layers in the second ceramic layer.Type: GrantFiled: February 24, 2003Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toru Yamada, Kazuhide Uriu, Tsutomu Matsumura, Toshio Ishizaki
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Patent number: 6784536Abstract: An improved structure for an organic ball-grid array chip carrier having an organic substrate attached to a metal heat sink plate to prevent the chip carrier from warping. A supplemental organic substrate is attached to the metal heat sink plate on the side opposite from the functional organic substrate to provide symmetry to the bending forces resulting from the mismatch in coefficients of thermal expansion between the organic substrate and the metal heat sink plate.Type: GrantFiled: August 23, 2001Date of Patent: August 31, 2004Assignee: Altera CorporationInventor: Mohammad Eslamy
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Patent number: 6781832Abstract: A cooling unit comprises a heat sink arranged adjacent to a heat generating component, the heat sink having area dimensions greater than the heat generating component. A heat diffusing member is arranged between the heat generating component and the heat sink. A first heat conducting member is interposed between the heat generating component and the heat diffusing member, and a second heat conducting member is interposed between the heat diffusing member and the heat sink. The heat diffusing member has a thermal conductivity higher than the second heat conducting member and area dimensions greater than the heat generating component.Type: GrantFiled: February 28, 2002Date of Patent: August 24, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Nobuto Fujiwara
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Publication number: 20040155331Abstract: Methods and apparatuses for packaging a microelectronic device. One embodiment can include a packaged microelectronic device comprising a microelectronic die, an interposer substrate, and a casing encapsulating at least a portion of the die. The microelectronic die can have a first side attached to the substrate, a plurality of contacts on the first side, and an integrated circuit coupled to the contacts. The die can also include a second side with a plurality of first interconnecting elements on the second side of the die, such as first non-planar features. The casing can include an interior surface and a plurality of second interconnecting elements on the interior surface, such as second non-planar features. The first non-planar features on the second side of the die mate with second non-planar features on the interior surface of the casing. Accordingly, delamination along the interface between the microelectronic die and the casing is inhibited.Type: ApplicationFiled: February 11, 2003Publication date: August 12, 2004Inventors: Blaine Thurgood, David Corisis
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Patent number: 6774468Abstract: A polygonal nut 5 for receiving a clamping bolt 7 is securely inserted in a nut insertion hole 6 which is formed in the thin portion 1a of the resin case 1, and the polygonal nut is engaged with an inner surface 6a of the nut insertion hole 6. The inner surface 6a of the nut insertion hole 6 has a round-shaped notch concave portion 6b formed at a position confronting to a corresponding corner portion 5b of the polygonal nut 5 so that the corner portion 5b of the polygonal nut 5 is not in contact with a resin case member to thereby prevent the resin case from being cracked.Type: GrantFiled: September 8, 2003Date of Patent: August 10, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takeshi Ogawa
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Patent number: 6770956Abstract: A vibration gyro which is a sensor circuit module includes a packaging substrate, a vibrator mounted on the substrate, a chip type semiconductor element mounted by flip-chip bonding, a chip element, and a cover. The portion of the end surfaces of the packaging substrate in which no through-hole terminals are formed is coated with a light-shielding coating material which is a light-transmission-stopping member. Preferably, the color of the light-shielding coating material is as dark as possible, and is black, if possible.Type: GrantFiled: April 23, 2002Date of Patent: August 3, 2004Assignee: Murata Manufacturing Co., Ltd.Inventors: Katsumi Fujimoto, Keiichi Okano, Masato Koike
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Patent number: 6768196Abstract: A packaged microchip has a stress sensitive microchip having a microchip coefficient of thermal expansion, a package having a package coefficient of thermal expansion, and an isolator having an isolator coefficient of thermal expansion. The isolator is connected between the stress sensitive microchip and the package. The microchip coefficient of thermal expansion illustratively is closer to the isolator coefficient of thermal expansion than it is to the package coefficient of thermal expansion.Type: GrantFiled: September 4, 2002Date of Patent: July 27, 2004Assignee: Analog Devices, Inc.Inventors: Kieran Harney, Lewis Long
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Patent number: 6764773Abstract: A heat-dissipating substrate is made of a composite material comprising a first composition primarily composed of aluminum and a second composition primarily composed of silicon carbide and/or silicon The heat-dissipating substrate has a recess in one of its main faces. The main faces have fine unevenness, and the maximum amplitude of the fine unevenness in the depth direction of a main face is smaller than the maximum length in the depth direction of composite particles comprising the first composition and the second composition or particles of the second composition, the particles being exposed at the surface of the main face.Type: GrantFiled: August 28, 2002Date of Patent: July 20, 2004Assignee: Sumitomo Electric Industrial Co., Ltd.Inventors: Masahiro Omachi, Akira Fukui
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Patent number: 6765289Abstract: Reinforcing material having Rockwell hardness of 60 or above and comprising base material and adhesive is formed, and then the reinforcing material is attached to one side of silicon wafer on which circuits are not formed prior to dicing.Type: GrantFiled: April 25, 2001Date of Patent: July 20, 2004Assignee: Lintec CorporationInventors: Yasukazu Nakata, Yuichi Iwakata, Takeshi Kondo, Hideo Senoo
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Patent number: 6764875Abstract: A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques.Type: GrantFiled: May 24, 2001Date of Patent: July 20, 2004Assignee: Silicon Light MachinesInventor: James Gill Shook
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Patent number: 6762502Abstract: A method for forming semiconductor device packages including one or more semiconductor dice, leads in communication with bond pads of the dice, and a protective layer, or package, over at least the active surfaces of the semiconductor dice. The protective layer covers at least the bond pads, the proximate regions of the corresponding leads, and the conductive elements between the bond pads and their corresponding leads. The leads are at least electrically exposed through the protective layer. A portion of each lead may be physically exposed through the protective layer so as to facilitate connection of each lead to external circuitry. The packages may also include protective layers over the back sides or the edges of the semiconductor dice. A stereolithographic process is used for precisely forming the protective layers of the package. A machine vision system is used in connection with stereolithographic equipment to locate individual dice, features thereof, or leads.Type: GrantFiled: August 31, 2000Date of Patent: July 13, 2004Assignee: Micron Technology, Inc.Inventor: Salman Akram
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Patent number: 6762485Abstract: A conductive plastic lead frame and method of manufacturing, the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.Type: GrantFiled: August 30, 2001Date of Patent: July 13, 2004Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Jerrold L. King
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Patent number: 6759736Abstract: A semiconductor device (20) comprising a substrate (1) is provided with a first semiconductor element (3) on a first side (2), of the substrate and with a security coating (14) comprising a matrix, a first filler and a second filler. The second filler is an absorber of radiation of a wavelength of between 800 and 1400 nm and the refractive index of the first filler differs at least 0.3 from that of the matrix. As a result, the security coating inhibits transmission of radiation with a wavelength of between 400 and 1400 nm to a very large extent. The semiconductor device (20) can be incorporated in a smartcard.Type: GrantFiled: December 6, 2000Date of Patent: July 6, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Marcel René Bohmer, Nicolaas Kooyman
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Patent number: 6756670Abstract: An electronic device comprising a substrate having a frame, a metal lead and an electronic parts in a bonding structure, and a molding of an organic resin formed on the substrate, wherein the surface of the organic resin is provided with a hardened water-resistant or carbonaceous film or wherein pores at the surface of the organic resin are filled within an inactive gas such as argon because of a plasma treatment of the resin surface with the inactive gas whereby impurities are prevented from entering into the organic resin through the pores.Type: GrantFiled: October 30, 2000Date of Patent: June 29, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Mitsunori Tsuchiya, Kazuo Urata, Itaru Koyama, Shinji Imatou, Shigenori Hayashi, Naoki Hirose, Mari Sasaki, Noriya Ishida, Kouhei Wada
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Publication number: 20040119161Abstract: The present invention provides an economical package for housing semiconductor chip that allows a semiconductor chip to operate normally and stably over long periods by efficiently transferring heat generated during the operation of the semiconductor chip to the package mount substrate.Type: ApplicationFiled: December 2, 2003Publication date: June 24, 2004Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., A.L.M.T. CORP.Inventors: Hirohisa Saito, Takashi Tsuno, Chihiro Kawai, Shinya Nishida, Motoyoshi Tanaka
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Publication number: 20040113270Abstract: A method for producing a semiconductor component with the following steps. A semiconductor chip is provided having electrical contacts in a contact making region. A housing including a rear plate and a side area is provided and surrounds the semiconductor chip. A first compliant buffer layer is applied on a rear plate. The semiconductor chip is applied to the first compliant buffer layer, and a second compliant buffer layer is applied to and around the semiconductor chip except in the contact making region. A contact passage plate is provided with an opening over the contact areas and the contact passage plate is fixed to the second compliant buffer layer.Type: ApplicationFiled: August 15, 2003Publication date: June 17, 2004Inventors: Harry Hedler, Thorsten Meyer, Barbara Vasquez