Abstract: A resin-molded unit (1) includes a semiconductor bear chip (2) arranged inside and sealed in an epoxy resin mold (3). The resin-molded unit is entirely covered with a magnetic loss film (5) as a high-frequency current suppressor. It is preferable that the magnetic loss film is made of a granular magnetic material. A plurality of lead frames (4) may be extended from the semiconductor bear chip to the outside through the epoxy resin mold.

Abstract: A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid scaling region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques.

Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.

Abstract: An electronic package comprising a semiconductor chip mounted on a substrate is formed by bonding a structure which covers at least an outer surface of the semiconductor chip and has the same or about the same thermal expansion coefficient as the substrate to the semiconductor chip's side surface of the substrate. This reduces warp and deformation caused by temperature changes during package operation.

Abstract: The present invention provides a ball grid array (“BGA” ) assembly and process of manufacturing for reducing warpage caused by the encapsulation of the associated semiconductor chip. The assembly and process includes coupling a substrate between a semiconductor chip and a BGA structure; attaching a stabilizing plate to the substrate adjacent the BGA structure; and encapsulating the semiconductor chip.

Abstract: A packaging process and structure of electronic device provides first a substrate having a carrying surface and a mounting surface wherein the carrying surface is divided into a device disposing region and a device peripheral region. Then a hydrophobic Fluorine-containing layer is formed in the device peripheral region of the substrate. Subsequently, an electronic device is attached in the device disposing region and is electrically connected to the substrate. Then, a molding compound is employed to encapsulate the electronic device. The bondability between the hydrophobic Fluorine-containing layer and the molding compound is weaker than the bondability between the molding compound and the substrate. Finally, a degating process is performed to remove the excess molding compound positioned at the hydrophobic Fluorine-containing layer to accomplish the packaging process of the electronic device.

Abstract: A method for operating a microwave amplifier wherein a packaging arrangement is provided. The packaging arrangement includes: (i) a mounting thermally conducting mounting flange; (ii) an isomorphic, thermally conductive material disposed on the flange; (iii) a circuit comprising a semiconductor chip having a transistor arranged as the amplifier, such amplifier being adapted to operate at a nominal microwave frequency with a band of frequencies, disposed on a portion of a surface of the isomorphic, thermally conductive material, other surface portions of the thermally conductive material extending laterally beyond the portion of the material having the semiconductor chip disposed thereon; (iv) a corral having an aperture through an inner region thereof, the isothermal material being disposed within the aperture, such corral having an outer region thereon mounted to surface portions of the flange. The amplifier is biased for Class C operation.

Abstract: A substrate comprising, for example, a copper-beryllium oxide ceramic-copper sandwich permits a laser diode along with cooperative components to be soldered in place using a high temperature solder. The sandwich structure is operative to move the effective thermal properties of the copper more towards that of the beryllium oxide thus reducing, for example, any stress which might occur between the solder, the substrate, and the laser diode. The use of high temperature solder provides for significantly improved operation.

Abstract: A chip scale package mainly comprises a semiconductor chip disposed on an upper surface of a substrate and sealed by a package body. The package body comprises a resin base material divided into a first region and a second region. The resin base material contains a plurality of filler particles having the percentage by weight of the filler particles in the first and second regions being different. Thus, in accordance with the present invention, the package provides better buffering effect for stresses due to CTE mismatch between the substrate and the chip, and significantly reduces the moisture from surrounding diffusing into the package thereby reducing the problems of delamination or die-cracking.

Abstract: A heat resisting resin sheet is bonded to a semiconductor chip as a protective cap for protecting a beam structure provided on the semiconductor chip, through a heat resisting adhesive. The heat resisting resin sheet is composed of a polyimide base member and the heat resisting adhesive is composed of silicone adhesive. The heat resisting resin sheet is not deformed during a manufacturing process of the semiconductor chip. In addition, grinding water does not invade into the semiconductor chip during dicing-cut.

Abstract: A packaged semi-conductor substrate includes a package encapsulant pouring area, a layout provided on the substrate, a layer of solder mask deposited on the layout, and a film provided on the solder mask. When the package encapsulant is pouted into the package encapsulant pouring area, the package encapsulant is isolated from the solder mask by the film. An adhering force between the film and the package encapsulant is greater than an adhering force between the film and the mask such that the film is degated along with the package encapsulant in the pouring channel during a degating procedure of the pouring channel after a pouring procedure of the package encapsulant. Thus, the film and the package encapsulant are not residual on the substrate.

Abstract: A curable silicon composition, comprising (A) 100 parts by weight of an organopolysiloxane containing silicon-bonded aryl groups and at least two alkenyl groups per molecule, and having a viscosity of from 0.01 to 1,000 Pa.s at 25° C., wherein the aryl groups comprise from 1 to 40 mole % of the total silicon-bonded organic groups in the organopolysiloxane; (B) an organopolysiloxane having a viscosity of from 0.001 to 10 Pa.s at 25° C. and containing at least 2 silicon-bonded hydrogen atoms per molecule, in a quantity sufficient to cure the composition; (C) a platinum catalyst in a quantity sufficient to cure the composition; and (D) 0.00001 to 100 parts by weight of an organopolysiloxane having a viscosity of from 0.01 to 10,000 Pa.s at 25° C.

Abstract: A protective containment apparatus for preventing damage to expensive components of an assembly due to the failure of an electronic component in a nearby potted circuit which is known to fail catastrophically. The containment apparatus can employ a resilient material 38 placed around the at-risk electronic component 34 prior to potting the circuit. The resilient material 38 absorbs the expanding gases and fragmented parts of the at-risk component 34 which are expelled during the catastrophic failure. The cushioning effect of the resilient material 38 prevents the fragments and parts of the potting material from becoming projectiles that can damage any nearby components of the assembly. The containment apparatus can also employ a restrictive material 42 placed around the at-risk component 34 prior to potting the circuit.

Abstract: A semiconductor device includes a semiconductor element having a plurality of electrodes on an upper surface thereof. A first substrate has a plurality of conductors on an upper surface thereof. The first substrate is mounted on the upper surface of the semiconductor element and is smaller in area than the semiconductor element. A second substrate has a plurality of solderballs on an upper surface thereof. The second substrate is mounted on the upper surface of the first substrate and is smaller in area than the first substrate. An adhesive layer is disposed between the first substrate and the semiconductor element, and causes the first substrate to be affixed to the semiconductor element. A plurality of metal wires electrically couple the electrodes on the semiconductor element to the conductors on the first substrate. A sealing frame is attached to the semiconductor element. A cap is bonded to both the second substrate and the sealing frame.

Abstract: Disclosed is a thin plate member for forming a semiconductor package, having a recess for receiving a semiconductor chip. The thin plate is composed of sintered metal, e.g. sintered copper or sintered alluminum alloy. A sintered metal body being porous and having a shape which is close to the shape of the thin plate member is prepared, and it is sized into the shape of the thin plate member. The sintered alluminum alloy comprises 0.4 to 0.8% by weight of magnesium, 0.2 to 0.6% by weight of silicon and the balance aluminum and has a structure comprising an aluminum phase being formed of aluminum particles and an alloy phase being composed of magnesium, silicon and aluminum and interposing between the aluminum particles, and the sintered copper has a metallographic structure comprising a phase of copper particles.

Abstract: A semiconductor device in which defective resin filling can be prevented. One embodiment has a metal heat-releasing plate (103) with good thermal conductivity, which is sealed within a resin portion (107). An inner lead (101) is attached to the heat-releasing plate (103) and is at the same time provided with a bent portion. The heat-releasing plate (103) is located at the center of the resin portion (107) in its thickness-wise direction. The above arrangement roughly equalizes the spaces above and under the heat-releasing plate (103), thereby improving the resin filling performance to enable fabrication of a semiconductor device without causing defective resin filling such as an unfilled portion.

Abstract: A hermetic thin pack semiconductor device. The semiconductor device has a semiconductor substrate and at least one electrode on the upper surface of the semiconductor substrate. A lid of a ceramic material for the semiconductor device has at least one opening extending through the lid. A first electrically conductive material is located on the interior surface of the at least one opening, a second electrically conductive material is located on at least a portion of the upper surface of the lid, and a third electrically conductive material is located on at least a portion of the lower surface of the lid. A solder material is positioned between the electrode and the third electrically conductive material and positioned on a corresponding portion of the electrode opposite a corresponding opening in the lid.

Abstract: The present invention is characterized, in a semiconductor device with a semiconductor element sealed by resin, in that a metallic foil is bonded through adhesive to the bottom of a lead frame with the semiconductor element mounted thereon, and another metallic foil is fixed to the outer surface of the sealing resin on the side of the semiconductor element. Such a configuration provides a semiconductor device free from warp. In addition, the effect of no warp and metallic foils on the upper and lower surfaces of the semiconductor device provides a reliable semiconductor device with excellent heat dissipation, less influence from moisture absorption and high thermal stress resistance.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature T.sub.g greater than 200.degree. C. and a volumetric coefficient of thermal expansion of .ltoreq.75 ppm/.degree.C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: A semiconductor optical sensing device includes an insulating casing containing a semiconductor optical sensor chip fixed in the bottom thereof. Transparent silicone gel fills the interior of the casing and covers the sensor chip. A transparent plate covers both the sensor chip and the silicone gel. Holes in the casing allow expansion and contraction of the silicone gel without disturbing the optical properties of the sensor chip, and without permitting the formation of bubbles in the silicone gel.

Abstract: A method of manufacturing a semiconductor and a lamination therefor, in which fixing materials are temporarily fixed to the molding faces of a mold through release films. The semiconductor element is then placed in the mold and molding resin is injected into the mold. The resin is heated to produce the semiconductor device. During this process, the fixing materials become embedded in each of the opposite surfaces of the resin.

Abstract: An integrated circuit heat transfer element (6,30) is made by selecting thermally conductive fibers having aspect ratios of length to diameter of more than 1, selecting a resin and combining the fibers and the resin to create a formable resin/fiber compound. The resin/fiber compound is formed into a composite material in part by applying pressure to the formable resin/fiber compound, which aligns the fibers, and when cured creates a thermally anisotropic composite material to maximize heat conduction along the aligned fibers. The thermally anisotropic composite material has a coefficient of thermal expansion (CTE) of less than about 10.times.10.sup.-6 cm/cm/.degree. C. The composite material has a thermal conductivity in the direction of the carbon fibers of at least 50 W/m.degree. K. The IC device is preferably secured to the heat transfer element using a thermally conductive adhesive.

Abstract: A semiconductor element such as a CCD chip is contained in a recess portion of an opaque package made of plastic, and the upper surface thereof is covered with a transparent cap made of plastic. The cap has a different thermal expansion coefficient from that of the package and is formed in a thickness of 0.5 mm which is thinner than that of the prior art. The semiconductor element is connected with leads and these leads project outside the package. This semiconductor device is mounted to a printed circuit board.

Abstract: A composite bump structure and methods of forming the composite bump structure. The composite bump structure comprises a polymer body of relatively low Young's Modulus compared to metals covered by a conductive metal coating formed at the input/output pads of an integrated circuit element or substrate. The composite bump is formed using material deposition, lithography, and etching techniques. A layer of soldering metal can be formed on the composite bumps if this is desired for subsequent processing. A base metal pad covering the integrated circuit element input/output pad can be used to provide added flexibility in location of the composite bump. The composite bump can be formed directly on the input/output pad or on the base metal pad.

Abstract: A copper sheet having an aperture provided therein at a bonding area for clearing the semiconductor chip and its bonding wires is bonded by an adhesive to a sealing side of an organic substrate which has been loaded on the sealing side with a pattern of copper foil wiring. The copper sheet is higher in adhesiveness to a sealing resin than to any conventional resist. A resultant semiconductor device according to the present invention will prevent detachment of the sealing resin at an interface, which may result from a thermal history in the sealing or reflow process and eliminate entrance of water, hence minimizing a decline in resistance to moisture.

Abstract: A method for preparing a circuitized organic substrate for the subsequent deposition of an adhesive thereon is provided. The method comprises exposing the circuitized substrate to a plasma formed from a gas mixture comprising a fluorine-containing entity. Preferably, the gas mixture used to form the plasma also comprises oxygen. It has been determined that treatment of the circuitized substrate with a plasma formed from a gas mixture comprising at least 20% by volume of the fluorine-containing entity and, preferably, up to about 80% by volume of oxygen reduces the spread of an adhesive deposited on the surface of the organic substrate. It has also been determined that such treatment does not adversely affect the subsequent bonding of wires to the wire bond sites that are present on the surface of the substrate.

Abstract: A method and apparatus for controlling the thickness of a thermal interface between a processor die and a thermal plate in a microprocessor assembly are provided. The apparatus includes a generally rectangular shaped thermal top cover having a recessed portion of predetermined depth and aperture therein. The thermal top cover fits over the processor die. A thermal interface layer fills the recessed portion of the thermal top cover covering the processor die. The depth of the recessed portion is greater than the thickness of the processor die so that the thickness of the thermal interface layer is controlled. A thermal plate is placed over the thermal top cover in contact with the thermal grease so as to form a thermal path from the processor die to the thermal plate.

Abstract: There is provided a plastic-packaged semiconductor integrated circuit including (a) an inner lead having a lead-on-chip (LOC) type structure, (b) a ball grid array (BGA) type terminals for electrically connecting the inner lead to an external circuit, and (c) an outer package made of thermosetting resin for shielding the inner lead therein.

Abstract: A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

Abstract: A shielding apparatus for an electronic component includes a first insulative encapsulant surrounding at least a portion of the component and a second encapsulant surrounding said first encapsulant and having conductive particles dispersed therein for absorbing ionizing radiation.

Abstract: Polyimide layers having special properties are formed on the bottom surface of a metallic body for a metal-based semiconductor circuit substrate with a polyimide layer as an insulator. There are four lamination methods: (a) a method in which a layer of thermoplastic polyimide resin (1) and a layer of non-thermoplastic polyimide resin are laminated on the bottom surface of the metallic body one over another in this order, (b) a method in which a layer of thermoplastic polyimide resin (1), a layer of non-thermoplastic polyimide resin and a layer of thermoplastic polyimide resin (2) are laminated on the bottom surface of a metallic body one over another in this order, (c) a method in which a layer of non-thermoplastic polyimide resin is laminated on the bottom surface of a metallic body and (d) a method in which a layer of thermoplastic polyimide resin (2) is laminated on the bottom surface of a metallic body.

Abstract: A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.

Abstract: The present invention discloses a power semiconductor component 1 having a special pressure contact system which is suitable, for example, for circuit-breakers, rectifiers, or the like in industrial drives. A pressure-equalizing element 9 in the form of a box 10, 15 with a flowable or plastically deformable medium 12 is inserted between a pressure plunger 7a and a power semiconductor 2. Because of the hydrostatic pressure in the box 10, an inhomogeneous pressure delivered at one side is passed on to the other side as a homogeneous pressure. A homogeneous pressure delivery can be achieved, even in the edge region of the pressure surfaces 11a, 11b, by means of an inlet camber of the lateral surface 13. The box 10, 15 preferably consists of copper or AlSiC, and the medium 12 of a liquid metal (Ga, Hg), a plastic metal (Pb, Al) or of metal balls (Cu) in silicone oil.

Abstract: A semiconductor device includes a plastic substrate with a multilayer structure having electrically conductive lines and an embedded planar metal layer, a semiconductor chip having electrodes connected to respective lines by solder, and a sealing member of a synthetic resin adhering the semiconductor chip tightly to the plastic substrate.

Abstract: A power semiconductor module in which a plurality of power semiconductor elements forming a bridge circuit are provided together with control circuits. The module includes a common casing which accommodates a metal base, a main circuit section, and a control circuit section. The main circuit section has a plurality of semiconductor elements of the bridge circuit mounted on a ceramic insulating board which is thermally coupled to the metal base. The main circuit section also supports connecting conductors to which the semiconductor elements are connected. In the control circuit section are mounted control circuits for the semiconductor elements. The control circuits are mounted on a wiring substrate which is formed by wiring conductors on an insulating board. The main circuit section is connected through a bond to the control circuit section. Input and output terminals of the bridge circuit are extended from the connecting conductors of the main circuit section.

Abstract: A package for shielding a circuit containing magnetically sensitive materials from external magnetic fields. A shield attached to a base of the package is connected by vias to a first conductive plane. A shield attached to a lid of the package is connected by vias to a second conductive plane. The first shield and the second shield are electrically interconnected. Conductive leads extend from the package and are connected internally to the circuit.

Abstract: An electronic device (10) such as that of the micromechanical type having a time-released source of a passivant (20). This source (20) is preferably comprised of an impregnated molecular sieve/binder combination, preferably being a polymer. The passivant may be PFDA. The time-released passivant source continuously over the life of the device reduces any tendency of engaged or contacting elements to stick, adhere, or otherwise resist separation. The present invention finds particular use in spatial light modulators of the DMD type. The molecular sieve/binder can also include getter/desiccant source, such as a non-evaporable getter to remove moisture from the hermetically sealed electronic device.

Abstract: A semiconductor optical device is provided with a photo-electric conversion unit having plural photo-electric conversion elements and is entirely sealed by a sealing member. The photo-electric conversion elements are connected to external leads with electrical connectors. The distance D between a planar outer surface and a photoelectric conversion area satisfies the equation, D.gtoreq./2.multidot.l/tan .theta., where .theta. is a critical angle of total reflection of the sealing member with respect to air and l is the maximum length of said photoelectric conversion area.

Abstract: The semiconductor package contains the substrate with a stacked structure; the semiconductor device mounted on the top of the substrate and provided with the electrode pads; the input/output terminals on the bottom of the substrate, which connects the semiconductor package to the printed circuit board; and the conductive tubes going through the substrate, which connects the input/output terminals and the electrode pads. The surface-mounted semiconductor package has the protecting device on its sides. The protect device prevents water and the like from infiltrating the edges of the substrate, and additionally avoid a crack of the substrate due to expansion of the water. Furthermore, the protecting device has the pairs of lands on both sides of the substrate, which fasten the edges of the substrate.

Abstract: A carrier substrate comprises a flexible insulating substrate containing aramid fiber as a reinforcer, first bonding pads formed on one side of the flexible insulating substrate, and second bonding pads formed on the other side of the flexible insulating substrate, where the first bonding pads and the second bonding pads are electrically bonded by via-holes punched in the flexible insulating substrate. The carrier substrate and a peripheral stiffener made of a material whose thermal expansion coefficient is higher than that of the carrier substrate compose a chip carrier, and an LSI chip is mounted on the recess of the chip carrier.

Abstract: The semiconductor package and manufacturing method thereof whereby the inexpensive package of high thermal conductivity is obtained by applying a Cu/Mo/Cu clad material for a base plate which matches the thermal expansion of a semiconductor chip, and the inexpensive package with high heat transfer suitable for a high frequency device is obtained by controlling a thickness of glass, and a size of a lead (width, thickness), thereby to match impedance of a wiring portion with that of the semiconductor chip, by plating only necessary areas with Au, and by plating the exterior with Sn.

Abstract: A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.

Abstract: An electronic control module (10) includes a package substrate (12) having an interior cavity (28) through which a package lead (22) traverses. The interior cavity (28) is filled with an expandable polymer material (34). The expandable polymer material (34) is constrained within the cavity by a pressure resistive layer (32, 35) that overlies expandable polymer material (34) In one embodiment, an epoxy layer (32) forms an upper surface of the interior cavity (28). The expandable polymer material (34) is responsive to a fluid, such that upon contact with a fluid diffusing along the package lead (22), the expandable polymer material (34) will swell and form a fluid-tight pressure seal around the package lead (22). The fluid-tight pressure seal prevents the fluid from diffusing to interior portions of the electronic control module (10) and causing the failure of electronic components (18) mounted within the electronic module (10).

Abstract: An integrated circuit device includes a substrate; circuit elements including an active element and a bias line for applying a DC bias voltage to the active element, disposed on the substrate; a thermoplastic material layer disposed on a region of the substrate; and a magnetic substance layer disposed on a region of the substrate including a region of the bias line, and adhered to and supported by the thermoplastic material layer. In this structure, the magnetic substance layer can be formed in an appropriate shape and at an appropriate position on the bias line according to the oscillation characteristics of the active element, such as a transistor, and the magnetic substance layer absorbs the frequency components of the oscillation of the active element, whereby oscillation of the active element is easily prevented.

Abstract: An improved semiconductor module comprising a molded frame and a composite semiconductor substrate subassembly received in a cavity in said frame. The composite semiconductor substrate subassembly comprises a plurality of semiconductor devices which are connected to electrical contacts on an edge of the molded frame by a variety of configurations described herein. In one embodiment of the invention, the composite semiconductor substrate sub-assembly includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The composite substrate provides a mounting surface for the placement of semiconductor devices and their associated passive components.

Abstract: A wirebondless module package and method of fabrication including a molded preform of porous SiC with a cavity having therein an AlN substrate defining a plurality of pockets. The preform being infiltrated with Al and the Al being deposited in each of the pockets. A semiconductor die mounted on the Al in one of the pockets. A dielectric layer covering the Al and defining openings therethrough positioned to expose the aluminum and a connection to the die. A conductive material positioned on the dielectric layer in contact with the die and the Al so as to define terminals and interconnections between the die and the terminals.

Abstract: The present invention relates to micro-mechanical devices including actuators, motors and sensors with improved operating characteristics. A micro-mechanical device (10) comprising a DMD-type spatial light modulator with a getter (100) located within the package (52). The getter (100) is preferably specific to water, larger organic molecules, various gases, or other high surface energy substances. The getter is a non-evaporable getter (NEG) to permit the use of active metal getter systems without their evaporation on package surfaces.

Abstract: This invention is for an integrated circuit package which includes two integrated circuit die connected to a common substantially planar lead frame, wherein bond pads on each die face the common lead frame.

Abstract: A flip-chip IC package (10) provides a thermally-conductive lid (20) attached to a backside of the chip (12) by a die attach layer (18) of a predetermined thickness range. A rim (22), preferably KOVAR iron-nickel alloy, is formed on the lid (20) with a depth (44) less than a sum (42) of a thickness of the chip, the interconnects (16), and a minimum final thickness (40) of the die attach layer (18) by a predetermined margin (46). An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy (24) is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer (18) with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness (40).

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.