Abstract: A focal plane plate for a high-resolution camera with light-sensitive semiconductor sensors, includes an electrically nonconductive material for accommodating housed light-sensitive semiconductor sensors. Adjustment elements are arranged on the focal plane plate at arrangement locations of the housings of the light-sensitive semiconductor sensors, or the focal plane plate is designed with the adjustment elements. The adjustment elements are capable of being adapted in a complementary fashion to the form of the housings in the top sides of the light-sensitive semiconductor sensors lying in a common plane.

Abstract: A thin film hydrogen getter and EMI shielding are provided for protecting GaAs circuitry sealed in an hermetic package. The thin film getter comprises a multilayer metal film that is deposited by vacuum evaporation techniques onto a conductive metal, such as aluminum or copper, that serves as the EMI shielding. The conductive layer is first formed on an interior surface. The multilayer hydrogen getter film comprises (1) a titanium film and (2) a palladium film that is deposited on the titanium film. Both the titanium and the palladium are deposited during the same coating process run, thereby preventing the titanium from being oxidized. The palladium continues to prevent the titanium from being oxidized once the getter is exposed to the atmosphere. However, hydrogen is easily able to diffuse through the palladium into the titanium where it is chemically bound up, since palladium is highly permeable to hydrogen.

Abstract: A semiconductor package for three-dimensional mounting is provided. The package includes a wiring substrate having a first surface on which a first wiring pattern is formed and a second surface on which a second wiring pattern is formed, the first wiring pattern and second wiring pattern being electrically connected to each other; a semiconductor chip placed on the first surface of the wiring substrate and electrically connected to the first wiring pattern; a sealing resin layer sealing the semiconductor chip and the first wiring pattern; a thickness direction wire passing through the sealing resin layer in a thickness direction and having one end electrically connected to the first wiring pattern and the other end exposed at the surface of the sealing resin layer; and a lower surface connecting electrode formed on the second surface of the wiring substrate and electrically connected to the second wiring pattern.

Abstract: A package for an integrated circuit chip adapted to operate at microwave frequencies. The package includes an electrically conductive lead frame having electrical leads extending outwardly from an inner region. A base section is adhesively affixed to a bottom portion of the lead frame. The base section and a plastic cover are configured to provide a cavity when the cover and the base section are affixed with the integrated circuit chip being disposed with such provided cavity. With another integrated circuit chip package, an electrically conductive lead frame has electrical leads adapted for electrical connection to the integrated circuit chip. The base section includes a conductive member nd a dielectric member. The dielectric member has an aperture disposed in registration with an inner region of the lead frame. The conductive member is electrically to a bottom surface portion of the integrated circuit. The integrated circuit chip being disposed in registration with the aperture.

Abstract: A package for encasing one or more semiconductor devices includes a composite base component with opposing first and second surfaces formed from a mixture of metallic powders. A first metallic powder is copper or a copper-base alloy and a second metallic powders is a metal or metal alloy with a coefficient of thermal expansion less than that of copper. There is sufficient copper or copper-base alloy present for the composite base to preferably have a coefficient of thermal expansion of at least 9×10−6/° C. A ring frame formed from a nickel/iron-based alloy having a plurality of interconnections extending through sidewalls thereof is bonded to the composite base by a braze with a melting temperature in excess of 700° C. In an alternative embodiment, the composite base brazed to a frame formed from a ceramic having a coefficient of thermal expansion in excess of 8×10−6/° C.

Abstract: IC CHIP MOUNTING STRUCTURE has IC chips having protruding electrodes, a flexible printed circuit board having conductors connected to the protruding electrodes of the IC chips, and a protective plate attached to the flexible printed circuit board. The protective plate has openings to accommodate the driver IC chips. A resin member having a high heat conductivity is arranged in the opening in contact with the surface of the IC chip. The IC chip mounting structure can be attached to a chassis of a plasma display device so that heat generated by the driver IC chip is transferred to the chassis via the heat conductive resin member.

Abstract: A packaged microchip has an isolator that minimizes stress transmission from its package to its microchip. To that end, the packaged microchip includes a stress sensitive microchip having a bottom surface with a bottom surface area, and a package having an integral isolator. The isolator has a top surface with a top surface area that is smaller than the bottom surface area of the microchip. The microchip bottom surface is coupled to the top surface of the isolator.

Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.

Abstract: Disclosed is a semiconductor package characterized by having at least one cavity defined in a substrate and at least one buffer pad disposed in the at least one cavity. The semiconductor package includes a semiconductor chip disposed on the substrate, at least one conductive trace connecting with the buffer pad and at least one bonding wire electrically connecting the semiconductor chip to the buffer pad. The buffer pad has a thickness larger than the thickness of the conductive trace.

Abstract: A semiconductor device including a semiconductor substrate having a thickness of not more than 300 &mgr;m and a resin layer formed on a face thereof. A plurality of conductor sections formed in and through the resin layer, and a plurality of electrodes located on the resin layer and connected by the conductor sections to electrodes of semiconductor elements located on the substrate. The resin layer includes at least one of silica, alumina, zirconia, quartz fiber, glass fiber resin fiber and inorganic particles capable of absorbing ionic impurities.

Abstract: A groove having a V-shaped section is provided on a bonding surface of an IC chip being as a first small part, while an elongate projection having a V-shaped section to engage with the groove of the first IC chip is provided on a corresponding portion of a bonding surface of an IC chip being as a second small part. Then, the IC chips are bonded together by the action of a holding force resulting from fitting the elongate protection of the second IC chip to the groove of the first IC chip, together with a bonding force produced between the bonding surfaces by interatomic force and metallic bond.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one semiconductor chip, external contacts and a conductor configuration. The intermediate layer is provided with at least one opening, into which the at least one semiconductor chip is inserted. The carrier layer, the intermediate layer and the coverlayer are connected one above another and form a submodule. If a plurality of submodules are installed above one another, a semiconductor component is provided in which the semiconductor chips are located in several mutually overlying planes. The semiconductor chips can be interconnected. A method for producing a semiconductor component is also provided.

Abstract: A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected through the substrate to input/output terminals of the substrate. The substrate has a metal film on the top surface thereof around the opening of the respective the cavities. A metal lid panel, covering the cavity openings, is soldered to the metal film by reflowing a layer of solder disposed over a lid panel bottom surface, thereby sealing the die in each cavity. Subsequently, individual packages are singulated from the ceramic substrate.

Abstract: A coin-shaped IC tag which can be endowed with a predetermined weight is described. The coin-shaped IC tag ensures a normal operation and affords a satisfactory feeling of weightiness as a value medium. The coin-shaped IC tag comprises an IC tag core. The IC tag core comprises an IC packaging base member including a base and an electronic circuit for communicating data and for recording data, the electronic circuit mounted on the base. The IC tag core also comprises a high specific gravity resin layer joined to the IC packaging base member.

Abstract: The specification describes a packaging arrangement for micro-electromechanical systems (MEMS). The MEMS devices are mounted on a ceramic platform and are then packaged in a hybrid package. The hybrid package may be hermetically sealed. The hybrid package uses a ceramic insert as the primary MEMS device enclosure. The ceramic insert is mounted on a polymer printed wiring board, which provides both support and electrical interconnection for the ceramic insert. Optical access to the MEMS device is through a transparent window that may be hermetically sealed to the ceramic insert. The use of a ceramic primary enclosure for the MEMS device array substantially eliminates thermomechanical instabilities and provides thermomechanical and hermetic performance for the elements that require it. The main interconnection and routing function, implemented using standard epoxy printed circuit technology, yields high interconnection versatility and performance at low cost.

Abstract: A hermetically sealing enclosure for housing photo-semiconductor devices that reduces the heat generated in the wiring strips at the ceramic terminal member, increases the allowable current of the wiring strips in comparison with the conventional enclosures while maintaining the low power consumption, and stabilizes the output of the device in the enclosure. A photo-semiconductor module incorporating the enclosure is also offered. The ceramic terminal member is provided with a first wiring layer that comprises a plurality of wiring strips and that penetrates through the ceramic terminal member; two second wiring layers each of which comprises at least one wiring strip, one of which is connected to the first wiring layer at the outside of the enclosure, and the other of which is connected to the first wiring layer at the inside; and at least one third wiring layer that comprises at least one wiring strip and that connects the two second wiring layers.

Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.

Abstract: A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the semiconductor chip opposite from the solid device.

Abstract: A semiconductor package and its production method in which the semiconductor package is produced by having via holes for electrically connecting top and bottom surface of a double-sided copper clad substrate and cutting the substrate at a line separating the via holes into half. The semiconductor package includes a plurality of wiring patterns on the double-sided copper clad substrate, via holes for interconnecting the top and bottom sides of the substrate and having a long hole shape so that the via hole is shared by adjacent semiconductor packages when the substrate is cut and separated, semiconductor chips mounted on predetermined positions on the substrate, and resin for sealing an entire body of the substrate.

Abstract: An acceleration sensor is disclosed which includes a capacitance-type acceleration detection element mounted on a ceramic base plate. The element comprises a movable electrode mounted between a pair of fixed electrodes. Acceleration of the sensor in a measurement direction causes the movable electrode to move relative to the fixed electrodes and the element has opposite ends in a direction perpendicular to the measurement direction. The acceleration detection element is mounted on the base at a first one of the opposite ends. Accordingly, the mounting surface of the acceleration sensor is parallel to the direction of acceleration to be detected. Thus the acceleration sensor can be surface-mounted on a printed board, and more be easily mounted in an automobile air bag control system or the like.

Abstract: A plastic encapsulated VCSEL and power monitoring system wherein the VCSEL and photodetector are encapsulated in an optoelectronic plastic molding material. A tilted window, with a partially reflective coating on one side, is attached to the top of the plastic molding material using an epoxy with a refractive index that substantially matches the molding material. The plastic encapsulated VCSEL and photodetector may be manufactured at low cost using standard molding techniques. The high optical quality of the tilted window and partially reflective coating provide an excellent surface to reflect a portion of the optical beam back to the photodetector. Also, the tilted window substantially reduces inconsistent power monitoring due to beam divergence and walk-off.

Abstract: The present invention relates to a carrier module for micro-BGA(&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.

Abstract: The present invention provides an improved heat sink retention assembly, such that the heat sink is physically supported by a base rather than by an integrated circuit. Traditional heat sinks have an alignment feature that physically aligns and supports the heat sink by contact of the feature with an integrated circuit, and that transfers force applied to the heat sink to the integrated circuit. This transferred force may be seen as shear stress at the pins of integrated circuits such as pin-grid arrays, and may damage the integrity of the integrated circuit or its connection to an external circuit. The present invention provides alignment and support features remote from contact with the integrated circuit, and therefore provides support for the heat sink in a manner that does not place substantial stress on the integrated circuit.

Abstract: A novel array of optically and electrically interacting optical MEMS dies physically and electrically integrally attached upon an optically transmissive preferably (transparent) printed circuit substrate that is monolithically formed with one or more optical components, such as lenses, for providing fixed optical path alignment and interaction therebetween, and with provision for the integration also of active optical components such as lasers and photodiodes and the like.

Abstract: Disclosed are a packaging component for packaging a microelectronic (e.g., III-V semiconductor) device, the packaged microelectronic device, and methods for manufacture thereof. The component has sequentially deposited layers of metal (37, 50), to be located within the package, to act as a hydrogen getter. The sequentially deposited layers of metal include at least a first layer (3) of Ni adjacent the housing member surface, to improve adherence of the sequentially deposited layers and interstitially trap hydrogen; an outermost layer (11) of palladium to convert molecular hydrogen to hydrogen atoms and to absorb hydrogen; and a layer (9) of Ti or Zr adjacent this outermost layer. Additional layers (5, 7) of nickel and of titanium or zirconium can be provided between the first layer and the layer adjacent the outermost layer. Desirably, the surface of the housing member is roughened prior to depositing the first layer thereon.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature Tg greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.

Abstract: A chip carrier has a cavity portion for receiving a semiconductor chip and a flange portion along at least a portion of a top perimeter of the cavity portion. The module preferably includes a substrate (e.g., a PCB or chip carrier substrate) having a slot for receiving the cavity portion of the chip carrier, with the flange portion of the chip carrier being supported by the substrate. The flange portion is preferably electrically conductive and grounded, so that appropriate conductive pads on the chip can be wire bonded to the flange, while other on-chip pads can be wire bonded to designated pads on the substrate surface.. The cavity portion is also preferably thermally conductive to provide a thermal path for the semiconductor chip. In another embodiment, a relatively thick flanged chip mounting pad is also received within a substrate slot to provide improved heat dissipation.

Abstract: A hermetically sealing enclosure for housing photo-semiconductor devices that reduces the heat generated in the wiring strips at the ceramic terminal member, increases the allowable current of the wiring strips in comparison with the conventional enclosures while maintaining the low power consumption, and stabilizes the output of the device in the enclosure. A photo-semiconductor module incorporating the enclosure is also offered. The ceramic terminal member is provided with a first wiring layer that comprises a plurality of wiring strips and that penetrates through the ceramic terminal member; two second wiring layers each of which comprises at least one wiring strip, one of which is connected to the first wiring layer at the outside of the enclosure, and the other of which is connected to the first wiring layer at the inside; and at least one third wiring layer that comprises at least one wiring strip and that connects the two second wiring layers.

Abstract: An inductor and a manufacturing method for the inductor includes disposing a spacer pin defining a core, and which includes a magnetic sinter, in a mold, and placing a coil so as to surround the spacer pin. A composite material which has a permeability that is different from that of the magnetic sinter and which includes a mixture of a powdered magnetic material and a resin, is then injected into the mold to obtain a molded body having embedded therein the coil and the spacer pin. Next, external electrodes are formed on outside surfaces of the molded body such that both ends of the coil are connected to the external electrodes.

Abstract: A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

Abstract: A semiconductor module in which a lead electrode is integrally formed with or pressed into resin separated from a resin case, and a connector securing a pad for bonding a metal wire to the lead electrode is bonded to a substrate with a power semiconductor element mounted thereon by an adhesive, and the like in a similar manner as the module case. According to the present invention, an electrode can be disposed in an appropriate position in the semiconductor module, and the scope of the free layout is enhanced.

Abstract: A fastening mechanism for installing a processor heatsink on a planar board space takes up a minimal amount of the planar board space. The heatsink is held down securely against the top of the processor with a substantial amount of force. This is accomplished through a screw and leaf spring mechanism at each side edge of the processor. The screw and leaf spring arrangement are rotated out of the way while the heatsink is installed and then returned to their original positions to retain the heatsink. The mechanism is partially assembled prior to the installation of the heatsink.

Abstract: A method of encapsulating microelectromechanical (MEMS) structures is provided wherein the MEMS structures are formed on a substrate and encapsulated prior to packaging thereof. A sacrificial material is first deposited over the substrate to cover at least a portion of the MEMS structure. An encapsulation material is then deposited over the sacrificial material such that the encapsulation material covers at least a portion of the sacrificial material over the MEMS structure. The sacrificial material is subsequently removed such that the encapsulation material forms a shell spaced apart from and covering the MEMS structure and permits the intended operation of the MEMS structure. Associated MEMS devices fabricated using a method of encapsulating MEMS structures according to embodiments of the present invention are also provided.

Abstract: A semiconductor device substrate and a method of manufacturing the same by removing variations in resin thickness due to resin flows, warps in the substrate, cracking in the substrate, and foams contained in the resin.

Abstract: A semiconductor chip is mounted on a bottom plate, on which a side wall surrounding the semiconductor chip is formed. At a position where a lead passes through the side wall, an inner surface of the side wall and that of a ceramic piece lie on the same plane vertical to the bottom plate. Clearances with triangular cross-sections are provided for each boundary surface between the side wall and the ceramic piece so that the ceramic piece is prevented from being cracked by thermal stress. An airtight property of the ceramic package is not deteriorated by the aforementioned clearance.

Abstract: An integrated circuit package having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body are proposed. It is a characteristic feature of the proposed encapsulating mold that the encapsulating-body cavity formed in the upper mold further includes a constricted cutaway portion in the rim thereof. The constricted cutaway portion can be either uniform in thickness or formed in a multi-step staircase-like shape. During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would less likely to flash onto those surface parts of the substrate beyond the encapsulating body.

Abstract: A microchip (3) is mounted to a chip carrier (1) in such a way as to avoid an earth fault between the chip (3) and the carrier (1). When mounting chips, the chip (3) is placed on a chip carrier (1) that includes an electrically and thermally conductive element (13). The element includes a surface (17) and a recess (15) arranged relative to the surface. The microwave chip (3) is arranged at the surface (17) of the electrically and thermally conductive element (13) by means of a fixing or bonding substance (19), which is disposed at least partially in the recess (15). When mounting the chip, the chip (3) is positioned so that an earth plane (3d) of the microwave chip (3) will lie level with the surface (17) of the electrically and thermally conductive element (13). The chip carrier (1) is suitable for a chip mounting process and can be produced both readily and inexpensively.

Abstract: A packaging structure of an image sensor includes a plurality of metal sheets, an image sensing chip, and transparent glue. Each of the metal sheets has a first surface and a second surface. The image sensing chip is electrically connecting to the plurality of first surfaces of the metal sheets. The transparent glue is for covering the metal sheets and the image sensing chip is capable of receiving optical signals. The second surfaces of the metal sheets bonded by the transparent glue are exposed to the outside so as to form signal output terminals for the image sensor. A method for packaging the structure is also disclosed.

Abstract: The method of manufacturing a semiconductor device of the present invention includes steps of; a resin layer forming process in which a face with electrodes of a semiconductor wafer having a plurality of semiconductor elements formed thereon is coated with a resin layer which has a function of sealing it; and a wafer thinning process in which the back face of the semiconductor wafer is ground. The method of manufacturing the semiconductor device of the present invention further includes a process of forming a conductive section on the electrodes of the semiconductor wafer with a plurality of semiconductor elements in such a manner the conductive section reaches to the electrodes. The manufacturing method of the semiconductor device of the present invention still further includes a process of cutting the semiconductor wafer having a plurality of semiconductor elements along boundaries of each semiconductor element.

Abstract: A packaged integrated circuit device includes a substrate including a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component. The second circuit component may comprises an impedance matching circuit. The circuit device may also include fastening means for securing the lid to the substrate. The fastening means may comprise an adhesive, solder, or a spring biased member.

Abstract: Disclosed are a packaging component for packaging a microelectronic (e.g., III-V semiconductor) device, the packaged microelectronic device, and methods for manufacture thereof. The component has sequentially deposited layers of metal (37, 50), to be located within the package, to act as a hydrogen getter. The sequentially deposited layers of metal include at least a first layer (3) of Ni adjacent the housing member surface, to improve adherence of the sequentially deposited layers and interstitially trap hydrogen; an outermost layer (11) of palladium to convert molecular hydrogen to hydrogen atoms and to absorb hydrogen; and a layer (9) of Ti or Zr adjacent this outermost layer. Additional layers (5, 7) of nickel and of titanium or zirconium can be provided between the first layer and the layer adjacent the outermost layer. Desirably, the surface of the housing member is roughened prior to depositing the first layer thereon.

Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.

Abstract: A semiconductor die is enveloped by an ambient gas that will react to the presence of a particular wave length of light. A laser beam is focused on the edge of the die to deposit a dielectric coating. The laser beam or the die is rotated until the dielectric coating covers the entire die edge. The dielectric coating acts as a seal that is impervious to water and other contamination that can reduce the die reliability. The dielectric coating also electrically insulates the die from its surroundings.

Abstract: A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

Abstract: The present invention relates to a method of fabricating a microstructure having an inside cavity comprising the steps of:

Abstract: A millimeter wave semiconductor device is comprised of a millimeter wave device, a wiring substrate with the millimeter wave device mounted thereto, and a sealing cap with a conductor on a surface thereof for sealing the millimeter wave device. The sealing cap has a ground potential at the conductor provided on the surface thereof and the sealing cap has an internal surface spaced from an upper surface of the wiring substrate by less than one fourth of a spatial wavelength of a frequency applied. This can prevent creation of a waveguide mode in a sealed space and as a result provide a miniature millimeter wave semiconductor device which can have good RF characteristics in a space sealed by a conductive cap for electromagnetic shielding and can also readily be applied to a variety of packages associated with various product types.