Abstract: The present invention provides a small-sized and inexpensive semiconductor device wherein a synchronous dynamic random access memory and a flash memory are built in a single encapsulater. A flash memory chip and a synchronous dynamic random access memory chip (SDRAM chip) are fixed to a main surface of a wiring board in a parallel state, and another SDRAM chip is fixed onto the flash memory chip. Electrodes for the respective semiconductor chips are respectively exposed and these electrodes are connected to their corresponding electrodes of the wiring board. An encapsulater formed of an insulating resin is formed on the main surface side of the wiring board so as to cover wires. Since the encapsulater is formed by cutting a block encapsulater formed by block molding by dicing, the side faces of the encapsulater result in cut surfaces. Bump electrodes are provided on the back surface of the wiring board in an array fashion.

Abstract: A carrier for handling integrated circuit components during storage and shipping includes a plurality of pocket portions each for supporting an individual component. The pocket portions include a base surface and a plurality of sidewalls defining the pocket generally. The sidewalls include support surfaces arranged at a first, oblique angle relative to the base surface. A plurality of retainer surfaces are associated with at least some of the support surfaces. The retainer surfaces extend at a second angle relative to the base surface. The retainer surfaces cooperate with the support surfaces to maintain the integrated circuit components within the pockets in a desired alignment throughout handling. One example includes guide surfaces that facilitate inserting the components into the pockets.

Abstract: An electronic apparatus of the present invention comprises an electronic circuit board; an electrically conductive casing for encasing the electronic circuit board; a semiconductor element module electrically connected to the electronic circuit board; and a resin fixture intervening between the electrically conductive casing and the semiconductor element module, the resin fixture mounted with the semiconductor element module and fitted to the electrically conductive casing. As a result, the resin fixture can suppress a transfer of heat generated in the electronic circuit board to the semiconductor element module.

Abstract: A chip mounting substrate comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands.

Abstract: A polygonal nut 5 for receiving a clamping bolt 7 is securely inserted in a nut insertion hole 6 which is formed in the thin portion 1a of the resin case 1, and the polygonal nut is engaged with an inner surface 6a of the nut insertion hole 6. The inner surface 6a of the nut insertion hole 6 has a round-shaped notch concave portion 6b formed at a position confronting to a corresponding corner portion 5b of the polygonal nut 5 so that the corner portion 5b of the polygonal nut 5 is not in contact with a resin case member to thereby prevent the resin case from being cracked.

Abstract: A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one side of the member to close one end of each aperture. After devices are inserted into the apertures with their first ends “up” and their second ends “down,” a second removable cover is attached to the other side of the member to close the other end of each aperture. After inverting the assembly, removal of the first cover presents the devices in the apertures with their second ends “up” and their first ends “down.

Abstract: The present invention is to provide a power semiconductor device including a heat radiator having a principal surface and an insulating substrate bonded on the principal surface of the heat radiator via a first solder layer. The power semiconductor device also includes at least one semiconductor chip mounted on the insulating substrate via a second solder layer. The insulating substrate has a thin-layer and thick-layer edges, and is bonded on the principal surface of the heat radiator so that the first solder layer has a thickness thinner towards a direction from the thin-layer edge to the thick-layer edge (T1>T2). Also, the semiconductor chip is mounted on the insulating substrate so that a first distance between the thick-layer edge and the semiconductor chip is less than a second distance between the thin-layer edge and the semiconductor chip (L1<L2).

Abstract: A method for forming a semiconductor device including a die attach surface having a first pedestal and a first semiconductor die having a first surface formed with a first cavity for mounting the first semiconductor die on the first pedestal. Further provision is made for the formation of a dielectric cavity in the semiconductor die, the first pedestal or both. The cavity allows for fields produced by electronic components disposed on the upper surface of the semiconductor die to penetrate into the dielectric cavity. Inclusion of a second pedestal on a common die attach surface and a second semiconductor die having second cavity for mounting provides for substantially coplanar precision alignment or the first and second semiconductor die.

Abstract: A surface mount package is composed of a package body and first and second terminals. The package body has first and second surfaces intersecting with each other. Also, the package body has an installing portion for an element to be installed. The first terminal is connected to the first surface, and the second terminal is connected to the second surface.

Abstract: A surface mount-type microelectronic component assembly which does not physically attach the microelectronic component to its carrier substrate. Electrical contact is achieved between the microelectronic component and the carrier with solder balls attached to either the microelectronic component or the carrier substrate. A force is exerted on the assembly to achieve sufficient electrical contact between the microelectronic component and the carrier substrate.

Abstract: A plurality of semiconductor chips bent along the outer circumferential surface of a cylindrical substrate are mounted to the outer circumferential surface of the substrate. The bumps of these semiconductor chips are connected to connection pads formed on the outer circumferential surface of the substrate. By diminishing the curvature radius of the bent semiconductor chips, the size of the semiconductor module can be made smaller than the size of the chip.

Abstract: A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.

Abstract: Stress balanced semiconductor device packages, a method of forming, and a method of modifying a mold segment for use in the method. A semiconductor die is attached to one side of a substrate having discrete conductive elements such as a ball grid array (BGA) on the opposing side thereof. An envelope of encapsulant material is disposed over the semiconductor die on one side of the substrate while a stress balancing structure comprising at least one stem member and at least one transversely extending branch member formed of encapsulant material is disposed over the opposing side of the substrate in an arrangement which does not interfere with the discrete conductive elements. The envelope and the stress balancing structure may be simultaneously formed.

Abstract: A convergence device 10 for assembly an LCD imaging device 14 to a fixed housing 12. The convergence device 10 has a frame 25 with a plurality of retention arms 26 protruding therefrom. Each of the retention arms 26 has a retention barb 27 for hooking behind a retention land 28 on the imaging device 14. The imaging device 14 has a retainer 18 with a plurality of preload flexures 24 for providing some outward pressure on the frame 15 of the convergence device 10. After the imaging device 14 is positioned on the fixed housing 12, an adhesive 30 is applied to a housing adhesive gap 32 and to a plurality of imager fixing adhesive gaps 34 to hold the convergence device 10 in place relative to the fixed housing 12 and further to hold the imaging device 14 in place relative to the convergence device 10.

Abstract: A support assembly for supporting an integrated circuit package with an array of solder columns extending from a bottom surface of the integrated circuit package to a circuit board preferably includes: a pair of shims for supporting the integrated circuit package, the shims being positioned along opposite edges of the integrated circuit package and placed between and abutting the integrated circuit package and the circuit board; and a retention clip for aligning and securing in place the pair of shims.

Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.

Abstract: A packaged electronic device includes connection contacts that are formed on the contact pads on the second surface of the substrate. In contrast to the prior art, the connection contacts are not solder contacts but are formed of nickel/aluminum plated copper and are therefore harder and less malleable and subject to deformation than prior art solder balls. The connection contacts are formed to align with, and contact, attachment pads formed on the motherboard or other system component. A tension device is then used to mechanically attach the packaged electronic device of the invention to the motherboard.

Abstract: A lead frame for a high power semiconductor device die has three external lead conductors, the outer two of which are reentrantly bent outwardly from the center of the lead frame. When the lead frame is overmolded, the outer conductors are spaced from a central conductor by an increased creepage distance along the plastic surface of the housing. Further, the lead sequence of the exterior leads is gate, source, drain for a power MOSFET. The post area for wire bonding to the source post is enlarged to permit wire bonding with at least three bond wires. The external conductors can be downwardly bent to form a surface mount device. The cross-sectional area of the external conductors is substantially enlarged, although only a small enlargement of the circuit board hole is needed. The package outline has a long flat area centered over the main die area, with a tapered end surface which allows the package to pry open a mounting spring for surface mounting of the package.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: A micro-electromechanical system assembly is designed to integrate a laser. More particularly, laser is a vertical cavity surface-emitting laser. The MEMS assembly includes a micro-electromechanical substrate having an upper surface and a lower surface, the upper surface defined as having a first area and a second area. A first substrate bonding pad is positioned on the upper surface at a location within the first area, and a second substrate bonding pad is positioned on the upper surface at a location within the second area. Deposited upon the first and second substrate bonding areas are respective first and second solder material. A laser to be integrated in the MEMS assembly has a first laser bonding pad located on a first side, and a second laser bonding pad located on a second side. The laser is placed between the first substrate bonding pad and second substrate bonding pad such that they align with the respective first and second laser bonding pads.

Abstract: A substrate with at least one conductive post formed prior to the formation of an inter-layer dielectric (ILD) coating on the substrate. The conductive post may be formed from a metal layer of the substrate. Additionally, the conductive post may be built up on the substrate.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: The invention relates to a microstructure in a preferably electrically conductive substrate (1), more specifically made of doped single crystal silicon, with at least one functional unit (2.1, 2.2) and to a method of fabricating the same. In accordance with the invention, the functional unit (2.1, 2.2) is mechanically and electrically separated from the substrate (1) on all sides by means of isolation gaps (5, 5a) and is connected, on at least one site, to a first structure (4a) of an electrically conductive layer (S) that is electrically isolated from the substrate (1) by way of an isolation layer (3) and that secures the unit into position relative to the substrate (1). For this purpose, the functional unit (2.1, 2.2) is released from the substrate (1) in such a manner that the isolation gaps (5, 5a) are provided on all sides relative to the substrate (1).

Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: A semiconductor device having a plated heat sink (PHS) layer on the back surface, preventing a short circuit between a bonding wire, and a first metal layer. A method of making a semiconductor device including forming a catalyst layer on a bottom of a first separation groove in the front surface of a semiconductor substrate, and forming the first metal layer selectively in the first separation groove by electroless plating, using the catalyst layer as a catalyst.

Abstract: An image sensor package includes a substrate and an image sensor mounted to the substrate. Bond pads of the image sensor are wirebonded to interior traces on the substrate by bond wires. An encapsulant encloses the bond wires, the encapsulant being formed of a first optically curable material that has been cured. A lid adhesive mounts a lid to the substrate, the lid adhesive being formed of a second optically curable material that has been cured. During fabrication, the first and second optically curable materials are cured rapidly without heating to form the encapsulant and the lid adhesive, respectively, thus minimizing the fabrication cost of the image sensor package.

Abstract: An electronic interconnection assembly having a thin film bonded to either a glass ceramic or to an organic laminate substrate, and a method for attaching a thin film wiring package to the substrate. Provided is the utilization of adhesives which may be processed at significantly lower temperatures so as to avoid damaging components, the wiring package and interconnection joints. Moreover, pursuant to specific aspects, the joining of the thin film to the substrate may be implemented with the utilization of dendrites.

Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.

Abstract: A panel assembly of packaged integrated circuit devices including conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The locking passageways extend from a topside of the panel toward a bottom side of the panel. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.

Abstract: Utilization of the “dead space” previously occupied by a metal stiffener in an integrated circuit package as a location for power conditioning and converting mechanisms such as de-coupling capacitors and planar transformers.

Abstract: The present invention relates to a carrier module for micro-BGA(&mgr;-BGA) type device which is capable of testing a produced device without damaging to a solder ball thereunder after being rapidly connected to a test socket. A carrier module for a &mgr;-BGA type device according to the present invention comprises: an upper and lower carrier module body formed with protrusions at the upper and lower portions thereof; a device receiving unit inserted to the upper carrier module body for receiving a &mgr;-BGA type device; and a spring secured elastically to the upper and lower protrusions by being inserted thereto.

Abstract: The present invention provides an improved heat sink retention assembly, such that the heat sink is physically supported by a base rather than by an integrated circuit. Traditional heat sinks have an alignment feature that physically aligns and supports the heat sink by contact of the feature with an integrated circuit, and that transfers force applied to the heat sink to the integrated circuit. This transferred force may be seen as shear stress at the pins of integrated circuits such as pin-grid arrays, and may damage the integrity of the integrated circuit or its connection to an external circuit. The present invention provides alignment and support features remote from contact with the integrated circuit, and therefore provides support for the heat sink in a manner that does not place substantial stress on the integrated circuit.

Abstract: An integrated circuit chip and method of manufacturing the same which includes the use of a wafer cap having depressions therein for aligning with micro-electro-mechanical systems included in said integrated circuit when said cap is placed over a wafer containing numerous integrated circuits, the wafer is then cut, after the wafer cap is bound to the wafer. The wafer cap may also include a piezo-resistive element thereon for measuring pressure around the hermetically sealed MEMS.

Abstract: A method and apparatus for making sealed or closed microchannel structures in semiconductor wafers is disclosed. Two substrates, preferably a transparent cover substrate and an opaque base substrate, are used. The transparent cover substrate is placed over the opaque base substrate. By using the characteristics of the transparent material, electromagnetic waves are directed through the transparent cover substrate to the opaque base substrate. The laser beam heats the base substrate to its phase change temperature, melting the surface of the base substrate that is in contact with a surface of the cover substrate, coalescing the surfaces together and forming a sealed microchannel structure.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: A high-frequency module includes a substrate including a thin film resin sheet. A high-frequency circuit wiring line forming a first wiring layer is formed and a high-frequency circuit component is provided on an upper surface of the substrate. A resin sealing package seals the first wiring layer and the high-frequency circuit component.

Abstract: A MEMS device with a flap having one or more conductive landing areas electrically isolated from the flap and electrically coupled to a landing surface to reduce stiction. The device may be formed from a device layer of a silicon-on-insulator (SOI) substrate with conductive landing pads fabricated by forming one or more vias through the device layer, an underlying sacrificial layer etched to form one or more depressions at locations corresponding the vias and filled with a conductive landing pad material to form a structure having one or more electrically isolated landing pad areas on an underside of the device layer. A method for operating a MEMs device in an equipotential stiction reduction mode is also provided.

Abstract: An electronic device is described that has a sheet strip for packaging bonding wire connections of the electronic device and a method for producing it. To that end, the sheet strip, has at least two preformed, opposite edge regions which cover the edge regions of the bonding channel in an overlapping manner. Furthermore, the sheet strip has a preformed central region situated between the edge regions, which central region has a bulge and thickened portion and has two convexly curved contour lines in cross section.

Abstract: A control substrate is covered by an electromagnetic shielding member connected to a conductive base plate on which a power insulating substrate is placed. A conductive connecting member through which the electromagnetic shielding member and the conductive base plate are electrically connected to each other is inserted into a case. The control substrate and the electromagnetic shielding member are supported by the conductive connecting member.

Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.

Abstract: A semiconductor device having a semiconductor element and a plurality of segments formed by dividing a conductive plate. Some of the segments are electrically coupled with electrodes of said semiconductor element and constitute lead pad portions as mounting electrodes of the semiconductor device. Other segments among the plurality of divided segments constitute die pad portions on which the semiconductor element is mounted. The plurality of divided segments and the semiconductor element are sealed and supported together by a resin material portion. The resin material portion fills the space between the divided segments as the lead pad portions. Semiconductor devices having various package sizes can be fabricated by using standardized common parts.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: A chip carrier made of a non-metallic material has conductor tracks applied thereon for producing an external, two-dimensional connection configuration for electronic circuit chips. The chip carrier has a multiplicity of chip mounting locations and first cutouts disposed in such a way that at least one first cutout is adjacent each of the chip mounting locations. A second, channel-like cutout in the chip carrier leads from each chip mounting location to a first cutout adjacent the chip mounting location.

Abstract: The present invention relates to a capsule (1) for at least one high power transistor chip (17) for high frequencies, comprising an electrically and thermally conductive flange (10), at least two electrically insulating substrates (15), and at least two electrical connections (16), and a cover member, where the high power transistor chip (17) is arranged on the flange (10). The high power transistor chip (17) and the electrically insulating substrates (15) are arranged on the flange (10). The electrical connections (16) are arranged on electrically insulating substrates (15) and the electrically insulating substrates (15) are connected to the flange (10) and open and separate from the high power transistor chip (17).

Abstract: A heat-resisting high-power diode includes a casing defining a receiving chamber, a chip unit mounted in the receiving chamber and soldered to the casing by tin solder, a conductor unit soldered to the chip unit by tin solder, a cover shell riveted to the casing to close the receiving chamber, and a jelly-like electrically insulative glue of specific gravity lower than tin solder filled in the receiving chamber and covered over the chip unit and the lower part of the conductor unit to prohibit tin solder from flowing out of the casing when melted due to an excessively high working temperature.

Abstract: An apparatus (10, 310) is provided including a first chip having at least one recess (18, 418) formed on the first chip, in the form of an optoelectronic/photonic device (12, 314), at a pre-selected location. A second chip, in the form of an optical component supporting substrate (14, 312), includes at least one projection (24, 424) extending therefrom at a pre-selected location, wherein at least one of the recess and the projection includes angled walls (28, 428) having an angle relative to the top of the wall less than 54.74° for capturing and directing the other of the at least one recess (18, 418) and the at least one projection (24, 424) for aligning the first chip to the second chip.

Abstract: A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 using face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions and for relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.

Abstract: A semiconductor chip is mounted in face-up disposition, with a contact-bearing front surface facing away from a substrate such as a circuit panel, and with a rear face facing toward the substrate. A backing element having terminals is disposed between the rear face of the chip and the substrate, and the terminals of the backing element are connected to contact pads on the substrate. The terminals of the backing element are movable with respect to the chip to compensate for differential thermal expansion of the chip and substrate.

Abstract: An electronic package and method of making the electronic package is provided. An opening in the substrate of the electronic package is formed to substantially prevent adhesive which can bleed from under an electronic device from contacting conductive pads on the substrate. An electrical coupling is formed between the package's electronic device and conductive pads.

Abstract: A semiconductor device includes a semiconductor chip having a mounting surface with connecting pads mounted thereon, and a film having a gluing surface facing the mounting surface of the chip and a mounting surface for mounting a circuit board on a surface opposite the gluing surface. The circuit board has connecting pads mounted thereon. On the mounting surface of the film, a wiring pattern is formed with connecting terminals connected to the connecting pads of the circuit board. The film is an anisotropically conductive film and exhibits conductivity at local areas when subjected to pressure between the wiring pattern and the connecting pads of the semiconductor chip. The gluing surface of the film is attached solidly to the semiconductor chip, wherein the film maintains conductivity in view of a cooling process after heating.