Abstract: A method of fabricating a package for a micro-electromechanical systems (MEMS) device. A flex circuit interconnect subassembly for the package is made by placing a flex circuit on a pad insert, attaching a carrier insert to the pad insert to deflect the lead portions of the flex circuit, and applying a cover insert to the pad insert, after the attachment of the carrier insert, to re-deflect the lead portions of the flex circuit toward the device bond sites. The flex circuit interconnect subassembly may be combined with an electronic device die/carrier subassembly to form a completed electronic device package. The flex circuit interconnect subassembly and the die/carrier subassembly are joined using mechanical interlocking layers. The invention is particularly suited for making such an electronic device die/carrier subassembly which has a MEMS die permanently affixed to a carrier.

Abstract: A plurality of multi-chip modules are incorporated in a semiconductor device. Each of the multi-chip modules has a plurality of functional parts mounted on a circuit board. A flexible wiring board connects the multi-chip modules to each other. An interface part is mounted on the flexible wiring board so as to control input and output signals of the multi-chip modules.

Abstract: A high-frequency input/output feedthrough comprises a lower dielectric substrate in which are formed a bottom face ground layer, side ground layers, a line conductor and cofacial ground layers (formed on both sides of the line conductor on one and the same face of the lower dielectric substrate); and an upper dielectric substrate joined to the lower dielectric substrate so that portions of the line conductor and cofacial ground layers are sandwiched between the lower and upper dielectric substrate. In order to suppress return and insertion losses of signal in millimeter wave range due to a difference in transmission mode to improve transmission characteristics, the upper dielectric substrate is made thicker than the lower dielectric substrate. The width of the portion of the line conductor which is sandwiched between the lower dielectric substrate and the upper dielectric substrate is smaller than that of another portion. The cofacial ground layers are projected toward the line conductor.

Abstract: An improved package for a semiconductor device. The semiconductor device includes an apparatus having at least two access leads to facilitate electrical connection of the apparatus within an electrical circuit. The package has generally a closed polyhedral shape presenting a plurality of faces and substantially insulatingly surrounding the apparatus in a manner leaving the access leads exposed for effecting electrical connection. The access leads extend a distance from exit loci from the package. The exit loci are situated on an exit face of the package, adjacent pairs of exit loci being generally in a common plane. An intraplanar distance within the common plane is established intermediate each adjacent pair of the exit loci. The improvement comprises configuring the exit face to establish an on-surface path greater than the intraplanar distance intermediate selected adjacent pairs of the exit loci.

Abstract: An optical semiconductor device for surface mounting includes a semiconductor chip having a light emitting function or a light receiving function and two electrodes of the semiconductor chip sealed into a light-permeable resin package. The electrodes have tip surfaces externally exposed from the sides at the four corners of the resin package. The tip surfaces 4 of the electrodes are located on only the sides 4a of the resin package, but not located on the bottom thereof. In this configuration, when the optical semiconductor device for surface mounting is arranged on the solder paste on a board, its stand-up due to the contraction of the solder paste after the reflow can be avoided.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: A surface mount semiconductor diode device (50) having first (51) and second (53) coplanar contacts comprises a semiconductor element (52) having a first surface electrically mounted on a first member (54) formed of conductive material, which first member (54) has an arm (58) extending in a direction away from the semiconductor element (52) to an end (60) which forms the first contact (51). A cup member (62) formed of conductive material comprises a wall (64) extending from a bottom portion (66) so as to form an opening (68) surrounded by the wall (64). The semiconductor element (52) and first member (54) are mounted within the opening (68) such that a second surface of the semiconductor element (52) is electrically coupled to the bottom portion (66) of the cup member (62) and the end of the arm (58) extends above a top surface (72) of the wall (64).

Abstract: In the present invention, an insulating film adhesive material is attached onto the wirings in the form of a tent so that an empty space communicating with a vent hole is provided. Use of this chip-supporting substrate makes it possible to produce small-sized semiconductor packages preventive of package cracking and having a high reliability, because the function of the vent hole is not damaged and also gases and water vapor which are generated from the insulating film adhesive material at the time of reflowing can be driven off surely outside the package.

Abstract: A socket for semiconductor devices has a contact pin for a semiconductor device that is located on a top surface thereof and a contact pin for a board that is located on a bottom surface thereof, and which is placed between the semiconductor device and the board.

Abstract: A low-cost header for connecting an electronic components board to a circuit board is disclosed, consisting of side walls made of an unwarpable plastic material and joined together to form a frame around an area substantially the same as the area of the components board. A plurality of metal pins are located in the frame, each having one end extending from said frame such that these ends can be soldered to the components board concurrently with the solder attachment of the components to the board. The other ends of the pins can be formed so that they are adjusted for either through-hole attachment to circuit boards, or for surface mounting.

Abstract: In a stacked-type semiconductor unit having a plurality of semiconductor devices stacked on a base board including a base electrode, each semiconductor device has a wiring board including an external electrode provided in an end portion thereof. The semiconductor devices are stacked on the base board such that the external electrodes are aligned with one another. Then, the external electrodes are electrically connected to the base board by solder.

Abstract: An apparatus package for high temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: A substrate for mounting a semiconductor chip to be bonded to a surface of the substrate via a resin adhesive, such as an anisotropic conductive film. The substrate includes a substrate body having a semiconductor chip mounting surface and a plurality of conductive lines arranged on the surface extending in a lengthwise direction and spaced substantially in parallel to one another by a predetermined pitch. Each of the conductive lines defines, by a part thereof, a pad portion, a width of which is larger than that of the conductive line, to which a respective electrode of the semiconductor chip is to be electrically connected. Each pad portion has a first end and a second opposite end, with respect to a lengthwise direction thereof. The plurality of pad portions is arranged with a first end of one pad portion and a second end of an adjacent pad portion arranged in the vicinity of each other in a widthwise direction.

Abstract: An insert-molded leadframe having wire bonding posts formed on an inner portion, device pins formed on an outer portion, and a central portion connecting between the inner portion and the outer portion. Plastic encases the central portion of the conductive leadframe, such that the bonding posts and the device pins are exposed at inner and outer edges, respectively, of the plastic casing. The bonding posts and the device pins are disposed substantially perpendicular to one another. The conductive leadframe is formed with the bonding posts in a first plane and the device pins in a second plane, the first and second planes being substantially mutually parallel. The conductive leadframe then is encased in plastic by injection molding to form the insert-molded leadframe of the invention.

Abstract: Provided is a mount for an integrated circuit that features a routing carrier having first and second power planes and first and second signal layers. The first and second signal layers are disposed between the first and second power planes so that the return path for current propagating along the signal layers is in one of the adjacent power planes. To that end, another embodiment of the present invention provides that the distances between the signal layers and power planes are substantially constant over the volume of the routing carrier to ensure, which provides a constant impedance between one of the first and second signal layers and the power plane adjacent thereto.

Abstract: A mounting substrate and related mounting method for a semiconductor device. The mounting substrate includes a mounting area to which the semiconductor device is to be mounted and fixed by an adhesive, a peripheral channel formed in the mounting substrate so as to surround the mounting area, and radial channels extending radially from the center towards the periphery of the mounting area. An adhesive is applied at least to either the center of the mounting surface of the semiconductor device or the center of the mounting area of the mounting substrate. The semiconductor device is placed on the mounting area and the adhesive flows outwardly along the radial channels, with the adhesive then being cured. The peripheral channel provides control of the amount of adhesive which flows to the outside of the semiconductor device and the mounting area. The adhesive overflow can be adjusted such that adhesive climbs up the sides of the semiconductor device but not reach the upper surface of the device.

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Abstract: An integrated low cost thick film RF module and method for making same. An improved thick film dielectric is employed to build three-dimensional, high frequency structures. This new dielectric can be utilized to create novel RF and microwave modules that inexpensively integrate the I/O and electrical isolation functions of traditional microcircuits without using the usual set of expensive components. In particular, the module comprises a substrate; a conductive ground plane disposed above the substrate; a first dielectric layer printed on top of the ground plane; a microstrip disposed on top of the first dielectric; a second dielectric layer printed on top of the microstrip; a top ground plane disposed on top of the second dielectric; and a shield, electrically coupled to the top ground plane.

Abstract: Solder ball bond pads and wire bond pads may be selectively coated so that the wire bond bond pads have a thicker gold coating than the solder ball bond pads. This may reduce the embrittlement of solder ball joints while providing a sufficient thickness of gold for the wire bonding process. In general, gold coatings are desirable on electrical contact surfaces to prevent oxidation. However, the thickness of gold which is necessary on solder ball bond pads may be less and excessive gold may be disadvantageous. Thus, by masking the solder ball bond pads during the gold coating of the wire bond bond pads, a differential gold thickness may be achieved which is more advantageous for each application.

Abstract: A semiconductor device includes a lead terminal that has an island at one end, a semiconductor element whose bottom surface is connected to the island, one or more wires that connect a top surface of the semiconductor element to the island, and a resin seal that seals in the semiconductor device and the wires. In the island, a cut is formed between a section on which one semiconductor element is mounted and a section on which the wires are bonded.

Abstract: The semiconductor device includes a substrate, a semiconductor component, and a cap covering the semiconductor component and attached to the substrate. The cap has a top wall, a plurality of side walls 14 extending downward from the top wall and a bottom wall. Opening are provided in the side walls of the cap at corners thereof. Due to the provision of openings, the cap can be manufactured without deformation thereof. Air or liquid can flow into, or out of, the interior of the cap, after the semiconductor deviced is completed.

Abstract: Large size multi-chip module packages are fitted with a new lid (1) formed of a Kovar™ (5) framed sheet of Alumina (3) no less than 0.04 inches thick to form a new “postless” MCM package 2 (FIG. 4 and FIG. 6) that is tolerant of differential pressures of at least one atmosphere and is reworkable. The rigidity of the Alumina sheet avoids the problem of excess deflection found in the prior lids for the package. It also permits elimination of internal lid support posts, freeing internal area within the MCM package that may be used to seat additional electronic circuitry and/or components.

Abstract: A wire bonding method includes aligning the face of a capillary along a first direction to make a first wire bond at a first bond point. The capillary face is realigned to a second direction to make a second wire bond at a second bond point. The realignment may be achieved by a system including an wire bonding capillary having an indicator located thereon. A detector detects a signal from the indicator. The signal corresponds to a rotational alignment of the capillary and, therefore, to a direction of alignment of the capillary face. A first signal indicates a first alignment of the capillary face and a second signal indicates a second alignment of the capillary face. The signals may each have a relative signal strength which indicates rotational an offset of the capillary face from a given direction.

Abstract: An electrical assembly includes an IC package having a thermally conductive mounting flange in contact with a heat sink. A thermally conductive casing is secured to the heat sink, the casing at least partially enclosing the IC package. A resilient retaining member is disposed between the casing and IC package, the retaining member applying sufficient force on the IC package so as to maintain good thermal contact between the mounting flange and heat sink.

Abstract: A semiconductor component (31) and a method for coupling a semiconductor device (36) to a substrate (81). The semiconductor component (31) includes a saddle (34) and the semiconductor device (36). The saddle (34) has a plurality of sides (51, 52, 53, 54, 55) that form a semiconductor device receiving area (58). The semiconductor device (36) is inserted into the semiconductor device receiving area (58) and secured in the semiconductor device receiving area (58) using tabs (66, 67). The saddle (34) is coupled to the substrate (81) by fasteners (82,83).

Abstract: A press-fit package, such as a press-fit rectifier, includes an improved cup design which incorporates a mold lock formed within the inner wall of the cavity. a well is provided between the inner cavity wall and the die bond area to assist in mechanical decoupling of the press-fit force and the semiconductor die. An insert profile is formed along the outer surface of the cup to assist in proper alignment of the press-fit package during assembly, and a small lip is formed around the perimeter of the die bond area.

Abstract: A semiconductor device includes a semiconductor substrate having front and back surfaces and a heat dissipating metal layer on the back surface. The semiconductor substrate includes side surfaces covering a metal layer. The side surfaces are outwardly tapered and include a pair of upper side surfaces and lower side surfaces. A protrusion bearing semiconductor elements extends from the front surface of the substrate in a direction opposite the back surface of the substrate. The side surfaces of the protrusion are not metal covered. Thus, short-circuiting between wires connected to the semiconductor elements and the metal layer covering the side surfaces is avoided.

Abstract: In order to simplify handling and mounting of chips or chip-like structures/micro-blocks, a method and a device have been developed, by which, depending on the area of use, one or more chips can be assembled to act together and/or act together with other chip-like structures such as micromechanical building elements or microoptical elements. The actual retention of a micro-building-block (1) is achieved by micromechanical tongues (4) acting across holes or cavities (2) in a carrier material (3). Silicon tongues can, for example, be both flexible and sufficiently strong to retain a chip. In this manner, there is assured both precise vertical and horizontal positioning and mechanical retention. Electrical connection to the chip can be effected either by thin film technology or by more conventional wire-bonding.

Abstract: A semiconductor device includes a semiconductor pellet (1), and a package having a pellet mount portion (21) on which a semiconductor pellet (1) is mounted. The semiconductor pellet (1) is mounted on the pellet mount portion (21) of the package through a joint material (6). The area of the surface of the pellet mount portion (21) on which the semiconductor pellet (1) is mounted is set to be smaller than the area of the surface of the semiconductor pellet (1) which is mounted on the pellet mount portion (21), thereby preventing the climb-up of the joint material (6) along the side surface of the semiconductor pellet (1).

Abstract: A connector type semiconductor package having a package mounting surface on a package main body, the connection direction of a signal connection connector being parallel to the package mounting surface, the package comprising a connector insertion portion provided in the package main body, the signal connection connector detachably inserted into the connector insertion portion, surface mount type electrical connection terminals provided at the package main body, and a step provided at a side where the connector insertion portion of the package main body is provided, for determining the height of the surface mount type electrical connection terminals.

Abstract: A reworkable multi-chip module contains a large multi-chip module package (2) with an opening at the top to permit access to an internal region for semiconductor devices, the opening being at least four square inches area with the length or width dimension being at least two inches. The opening is sealed with a stiff closure (1) of sufficient rigidity to withstand at least one atmosphere of differential pressure without significant deflection, is removable in a single piece and may be reinstalled. The closure includes a panel of electrically non-conductive material (3) and a metal flange (5) borders the periphery of the panel to support the panel on the top of the module package.

Abstract: A method for providing pre-placed, pre-brazed feed throughs in the substrate of a hermetic package corresponding to the terminal leads of the encased circuit COTS components. The substrate may include directly bonded copper (DBC) regions forming circular shapes where the holes for the special connectors of the present invention will be located. These holes will correspond to the leads of the COTS component that will be mounted to it. Holes are laser or mechanically drilled into the substrate inside the circular shapes formed in the DBC. To form the feed through, a bushing, such as a blind copper rivet, is brazed in the hole, with the open end thereof oriented toward the component-side of the substrate. These open ends can accept the leads of the COTS component, like the holes of a conventional PC circuit board.

Abstract: A thermally enhanced semiconductor package includes a sheet metal cap having flexible flanges provided with solder contacts for reliable attachment to a circuit board. The package assembly further includes a semiconductor chip with a contact-bearing front surface facing forwardly, and chip bonding contacts overlying the front face of the chip. The flange bonding contacts are coplanar with the chip bonding contacts, or can be brought into coplanar alignment by flexure of the cap. The package can be surface-mounted to a circuit board by placing the package onto pads of solder paste, and then heating the assembly to melt the solder paste in order to join the bonding contacts on the chip and on the flange to corresponding contacts on the circuit board.

Abstract: In a gate unit (47) for a hard-driven GTO (10), at least some of the electronic components (37, . . , 42) needed for driving are arranged on a printed circuit board (34). The printed circuit board (34) encloses the GTO (10), in order to achieve low-inductance contact, in a plane lying between the anode side and the cathode side of the GTO (10) parallel to the semiconductor substrate (17) of the GTO (10) and is directly connected to the cathode contact (14) and the gate connection (22) of the GTO (10). A compact structure with, at the same time, improved mechanical stability is achieved in such a gate unit in that the components (37, . . , 42) are arranged on the printed circuit board (34) around the GTO (10), in the immediate vicinity of the GTO (10).

Abstract: A surface mount type semiconductor package is mounted on a printed board by bonding, by means of solder bumps signal electrodes, electrically connected to respective terminals of a semiconductor chip incorporated in the package, with lands provided on the printed board. On a mount surface of the package, there are provided auxiliary electrodes formed as electrodes which are not electrically connected to the respective terminals of the semiconductor chip and have a thickness greater than that of the signal electrodes. As a result, solder thickness is secured for the solder bumps between each signal electrode and corresponding land by the difference in thickness between the auxiliary electrode and the signal electrode.

Abstract: In the manufacturing process of electronic modules a problem could arise when the modules have non-flat top surface. This is due to the fact that most of the automatic picking tools uses a vacuum nozzle to pick and place the module. According to the present invention a flat feature (a cap or a stud) is added to the module. This flat feature can be either fixed on the module or removable after the manufacture in order to reduce the dimensions.

Abstract: A method and apparatus for controlling the thickness of a thermal interface between a processor die and a thermal plate in a microprocessor assembly are provided. The apparatus includes a generally rectangular shaped thermal top cover having a recessed portion of predetermined depth and aperture therein. The thermal top cover fits over the processor die. A thermal interface layer fills the recessed portion of the thermal top cover covering the processor die. The depth of the recessed portion is greater than the thickness of the processor die so that the thickness of the thermal interface layer is controlled. A thermal plate is placed over the thermal top cover in contact with the thermal grease so as to form a thermal path from the processor die to the thermal plate.

Abstract: The bond between a flip chip integrated circuit and a substrate is subject to mechanical stress from thermal cycles. This problem is exaggerated when the substrate has a rate of thermal expansion which is appreciably different from that of silicon. This problem is further exaggerated when the IC has a large footprint because it will experience a larger absolute expansion. A solution is proposed to this problem which involves creating an anchoring point. The anchoring point can be in either the IC or the substrate and can be a through-hole or a surface indentation such as a groove or a cutout. The anchoring point is filled with the underfill material during the underfill process. The anchoring point thus provides additional mechanical strength to the bond between the IC and the substrate.

Abstract: High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate, such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes. The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., a nickel plating).

Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.

Abstract: An electronic cartridge. The cartridge may include a first cover and a second cover that are adjacent to a substrate. One or more integrated circuit packages may be mounted to the substrate. The cartridge may include a pin that extends from the first cover and which has a barb that is embedded into the second cover. The embedded barb will damage the second cover if the cover is removed from the cartridge. The present invention thus prevents the removal and re-installation of the cover from the cartridge.

Abstract: A heat dissipating device which can provide multiple levels of pressure to a semiconductor package, having an outer peripheral ceramic region and an inner silicon region, is provided. A top cover member is provided with a central female-threaded bore. The top member is secured, without the use of tools, to the ceramic portion of the semiconductor package by a pair of upwardly standing legs with inwardly turned flanges where the flanges engage the marginal opposing portions of the top member. A heat dissipating member, having male-threaded base, is threadably inserted into the female-threaded bore to engage the upper surface of the silicon portion of the semiconductor package. The pressure of the heat dissipating member is independently adjustable, by hand, relative to the preset pressure of the top member onto the ceramic portion of the semiconductor package.

Abstract: A mount 2 is secured on a circuit board 1 to support a diode chip 3 thereon. A plurality of legs 7, 12 formed in the mount 2 are in contact with an electrode 4 on the circuit board 1 to form at least a dent 14. The mount 2 also has an inclined surface 8 formed at the periphery which faces the electrode 4. Solder 9 is filled in the dent 14 between the legs 7, 12 and in the flaring area 13 between the circuit board 1 and the inclined surface 8 of the mount 2 to prevent exfoliation or detachment of the mount from the electrode 4.

Abstract: A substrate for connecting one element having a first coefficient of thermal expansion to another element having a differing coefficient of thermal expansion that will alleviate interconnection problems due to thermal mismatch.

Abstract: A semiconductor device package and method includes a thick, integrated circuit chip stack having a substantially planar bottom surface with a plurality of terminals. A carrier substrate is provided, also having a substantially planar surface, and being adapted to mount the chip stack. The substrate has a plurality of terminals and may preferably be made of a metallized ceramic. The terminals of the chip stack are adapted to be connected to the terminals of the substrate. Means are provided for mounting the chip stack on the substrate, as well as means for making electrical connections between the terminals of the chip stack and the terminals of the substrate. Finally, encapsulating means are used for supporting and maintaining the chip stack mounted on the carrier substrate. J leads connect the substrate to a circuit card.

Abstract: An integral semiconductor package and mounting structure in which a lid for sealing a semiconductor chip on a platform includes flanges extending beyond the platform with the flanges having holes for receiving screws for mounting the package to a heat sink. The flanges are flexed into engagement with a heat sink thereby maintaining the package in yieldable pressure engagement with the heat sink.

Abstract: Heat sinks and methods particularly suited for use on packaged integrated circuits which are not amenable to the use of snap-on heat sinks and on which cemented-on heat sinks prevent conventional probing or reworking of the integrated circuit in the event trouble-shooting of the circuit is required after mounting of the heat sink. In accordance with the invention, a scalable post, based on heat sink size, mass and integrated circuit size, is cemented to the integrated circuit package in a configuration and location not interfering with the later probing or reworking of the integrated circuit, and without interfering with the printed circuit board layout. The post is then used to removably and independently hold a heat sink onto the integrated circuit so that good heat transfer between the integrated circuit and the heat sink is achieved, but still allowing the removal of the heat sink at any time if probing of the integrated circuit is later required. Alternate embodiments are disclosed.

Abstract: An improved transistor package with superior stability to wave soldering, having a nickel oxide barrier strip formed on the surface of the leads.