Abstract: A module houses electronic circuitry that comprises a first electrically conductive surface area and a second electrically conductive surface. The first and second electrically conductive surfaces combine to form a substantially token-shaped body. The body has a groove positioned around its perimeter. A probe that has a first end and a second end. A conductive, approximately pointed tip that extends from the first end of the probe and a conductive sleeve extends outward from pointed tip from a location proximate to said first end to a second distance. A first electrical connection contacts the tip and extends from the first end through the probe out the second end. A second electrical connection contacts the sleeve and extends from the first end through the probe out from the second end. A housing that holds an electronic module. The electronic module has a first surface and a second surface.

Abstract: A diode mount for an LED (2) with a plug connector (3) and compensating resistor (4) is manufactured by injection molding a one piece housing and mounting an LED and plug connector therein. An electrical connection between the LED and the plug connector, as well as a mechanical fixing, is accomplished by an electrically-conductive paste (5). At the same time, the electrically-conductive paste forms the compensating resistor.

Abstract: A method for packaging a semiconductor die includes forming an additional protective layer and conductive traces on the die. The die is then placed in a multi-die holder having electrical connectors for establishing an electrical connection to the conductive traces. The protective layer is formed as a thin or thick film of an electrically insulating material such as a polymer, glass, nitride or oxide. In addition, the protective layer can be formed with a tapered peripheral edge to facilitate insertion of the die into the die holder.

Abstract: A surface-mount semiconductor package comprises a semiconductor which is embedded within a plastics material body (10). Electrical control connections to the semiconductor comprise first and second upstanding legs (12,14) which are offset from each other, making it easier to couple the devices in parallel. Power output is provided by metal pads (16,18). The pads may be partially sheared, to step them, thereby allowing a single thickness leadframe to be used in the manufacture of the device. On the lower face of the body (10) there are channels (22,24) which increase the electrical tracking distance and allow improved washing of residues after the device has been secured to a substrate.

Abstract: A semiconductor device of the present invention enables mounting with a reduced thickness and a high density. IC packages (17) are mounted in each opening (12) on both surfaces of a substrate (11) in such a way that package bodies (18) are half accommodated in the opening (12) formed in the substrate (11).

Abstract: A package for relatively high power transistors including heat conducting mounting flange having a relatively large "footprint" relative to the area covered by at least one active chip supported thereby and comprised of a plurality of bipolar silicon-carbide transistors. The transistors are located on a dielectric substrate brazed to the flange. A plurality of screw mounting holes, preferably eight in number, are included in the mounting flange adjacent the outer edge of the dielectric substrate so as to surround the chip. Mounting screws in the eight mounting holes together with a relatively large flange/ground plane interface significantly improves heat dissipation for the heat generated by the silicon carbide transistors by promoting radial heat spreading through the heat conductive metal flange.

Abstract: An electronic miniaturized memory device according to the invention has at least one integrated memory circuit (2,20) and an interconnection interface (3), said memory device comprises a case (1) being a housing for an electronic subsystem (17), said interconnection interface (3) comprises at least one central contact (7,70) for electrically contacting at least one integrated memory circuit (2,20) and said case (1) comprises projecting portion (14) facilitating the attaching of the memory device to a support (8), allowing the memory device to document information relative to the curriculum vitae of the support (8) or to elements in its environment.

Abstract: A semiconductor device in which a control element is buffered from the effect caused by a power element whose heating value is greater than that of the control element, so as to provide the semiconductor device of multiple-chip configuration and having stable operating characteristics within a guaranteed range.

Abstract: The invention is to an array of stacked devices utilizing vertical surface mounted semiconductor devices stacked side by side and inserting the stack of devices into a casing. The packaged stack of devices creates a cube package which is capable of replacing SIMM boards, and saves considerable space. The casing dissipates heat generated in the devices, and may be of metal or thermally conductive plastic.

Abstract: Lead inductance of a power MOSFET circuit layouts is effectively reduced a `vertically` parallel terminal lead configuration that serves to cancel magnetic flux linkage between adjacent leads, thereby reducing the effective inductance in terminal leads to the gate, source and drain regions of the circuit. Rather than lay out source, drain and gate terminal leads in long, meandering shapes without regard to their direction or mutual coupling effects, as in conventional structures, source and drain leads are arranged as vertically parallel pair of generally flat conductors, that overlie one another on opposite sides of a thin strip of insulating material.

Abstract: A semiconductor device includes vertical placement part for mounting the semiconductor device on a surface of a circuit board in a vertical position, and a connection part for making electrical connections between the circuit board and a semiconductor element. A stage is provided on which the semiconductor element is placed. The stage has supporting members causing the semiconductor device to vertically stand on the circuit board. Wiring boards, stacked on a side of the stage on which the semiconductor element is placed, have windows in which the semiconductor element is located. The vertical placement part includes wiring lines extending between edges of the wiring boards facing the circuit board and peripheries of the windows. The wiring lines have ends located in the vicinity of the edges of the wiring boards and have a shape enabling the semiconductor device to be mounted on the circuit board.

Abstract: In a chip-carrier provided with a chip-carrier substrate, a chip-carrier cover and an IC chip, said IC chip being arranged at a distance from a circuit surface of the IC chip being directed toward the chip-carrier substrate, an .alpha.-ray shielding film made of film material containing few radioactive elements, and adhered to a surface of the chip-carrier substrate facing the IC chip or to the circuit surface of the IC chip is provided for protecting the IC chip from the IC chip.

Abstract: A solid state imaging apparatus which can be made small in the contour is formed of a solid state imaging device chip provided with pad electrodes formed near a photoelectrically converting part, an interal connecting substrate bent so that a plurality of surfaces not on the same plane as this solid state imaging device chip may be formed and face-bonded and connected with the pad electrodes of this solid state imaging device chip through bumping members and electronic parts fitted on this connecting substrate and functionally connected to the solid state imaging device chip.

Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

Abstract: A packaging and cooling assembly for integrated circuit chips includes a base for reception of one or more circuit chips, and a combination heat sink and cover for attachment to the base. The circuit chips are mounted circuit side down on the base, and include flexible lead frames for attachment to bonding pads on the base. Compliant cushions that generally conform to the shape and size of the chips are held loosely between the circuit sides of the chips, and the base. The heat sink enages the back sides of the circuit chips when it is attached to the base. This causes the chips to compress the compliant cushions, thereby holding the chips firmly in position, and forming a high thermal conductivity interface between the chips and the heat sink. To further enhance the heat transfer characteristics of the interface, a thin film of fluid is coated on the back sides of each chip to fill in the microvoids which result from asperity contact of the heat sink and chip mating surfaces.

Abstract: A semiconductor package is described for supporting and interconnecting semiconductor chips, each chip having contact lands on a contact surface, the package also including a substrate with a contact surface. An interposer module is disposed between at least one chip's contact surface and the substrate's contact surface. The interposer module has first and second opposed surfaces and a first plurality of contact locations positioned on its first surface which mate with a chip's contact land. A second plurality of contact locations on the interposer modules second surface are positioned to mate with contact lands on the substrate. A set of conductive vias are positioned within the interposer module and connect the first plurality of contact locations with a first subset of the second plurality of contact locations. A distributed capacitance layer is positioned within the interposer and is adjacent to its first surface.