Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.

Abstract: A separable and reconnectable connector for semiconductor devices is provided that is scalable for devices having very small contact pitch. Connectors of the present disclosure include signal pins shielded by pins electrically-coupled to ground. One or more signal pins in a contact array are electrically-shielded by at least one ground pin coupled to a ground plane. Embodiments thereby provide signal pins, either single-ended or a differential pair, usable to transmit signals with reduced noise or cross-talk and thus improved signal integrity. Embodiments further provide inner ground planes coupled to connector ground pins to shield pairs of differential signal pins without increasing the size of the connector. Inner grounding layers can be formed within isolation substrates incorporated into connector embodiments between adjacent pairs of signal pins.

Abstract: A chip electronic component includes a stack, a first external electrode disposed at least on a first end surface and a first main surface of the stack, a second external electrode disposed at least on a second end surface and a first main surface of the stack, a first bump disposed at least on a portion of the first external electrode on the first main surface, and a second bump disposed at least on a portion of the second external electrode on the first main surface. The first bump and the second bump each have a porosity greater than or equal to about 5% and less than or equal to about 40%.

Abstract: A micro heater chip, a wafer-level electronic chip assembly and a chip assembly stacking system are provided. The chip assembly stacking system includes a plurality of wafer-level electronic chip assemblies stacked on top of one another and electrically connected with each other. Each wafer-level electronic chip assembly includes a wafer-level electronic chip and a micro heater chip disposed on the wafer-level electronic chip. The micro heater chip includes a heating structure and an insulative structure disposed between the heating structure and the wafer-level electronic chip. The heating structure includes a carrier body, at least one micro heater disposed on or inside the carrier body, and a plurality of conductive connection layers passing through the carrier body. The insulative structure includes an insulative body disposed between the heating structure and the wafer-level electronic chip, and a plurality of conductive material layers passing through the insulative body.

Abstract: A flexible display device is provided that includes a display panel having an active area including a plurality of pixels displaying an image and a non-active area surrounding the active area, first data pads disposed in the non-active area adjacent to the active area of the display panel and electrically connected with the plurality of pixels, pads disposed in a direction away from the first data pads and the active area, second data pads disposed between the first data pads and the pads, and a protrusion pattern located between the second data pads and the third data pads and disposed on an upper part of the insulating layer.

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

Abstract: A semiconductor module includes a metal plate; a solder applied on the metal plate; a component-to-be-bonded mounted on the solder; and a linear guide portion delineated along a circumference of the component-to-be-bonded on a top surface of the metal plate, and including a metal surface having greater surface roughness than a peripheral region.

Abstract: A method for forming a connection structure is disclosed. A semiconductor structure having a first pad and a bump respectively on a bottom surface thereof is provided. A carrier having a second pad on a top surface thereof is provided. The second pad corresponds to the bump. An epoxy portion is disposed onto the second pad of the carrier. A diameter of the epoxy portion is less than or equal to a diameter of the bump. After depositing the epoxy portion, the bump is attached to the second pad via the epoxy portion.

Abstract: The present invention relates to an optical interconnection for interconnecting a first contact and a second contact, which need to be optically interconnected, the optical interconnection comprising: a nanorod formed on at least one of the first contact and the second contact; and a nanowire extending from the first contact or the nanorod formed on the first contact so as to transmit an optical signal toward the second contact or the nanorod formed on the second contact. The optical interconnection according to the present invention shows improved optical signal characteristics due to a reduction in coupling loss.

Abstract: A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.

Abstract: A semiconductor device includes a substrate; a die attached to the substrate; an encapsulation covering the substrate and the die, wherein the die is embedded within the encapsulation; and a heating element embedded within the encapsulation, wherein the heating element is configured to provide thermal energy to the die.

Abstract: Provided is a power semiconductor device which is able to have improved connection reliability between a wiring line and an electrode of a power semiconductor element in comparison to conventional power semiconductor devices. This power semiconductor device is provided with: a semiconductor element; an insulating substrate having an electrode layer to which the semiconductor element is bonded; an external wiring line which is solder bonded to an upper surface electrode of the semiconductor element and has an end portion for external connection, said end portion being bent toward the upper surface; and a frame member which is affixed to the electrode layer of the insulating substrate. The frame member has a fitting portion that is fitted with the end portion for external connection; and the external wiring line has at least two projected portions that protrude toward the semiconductor element.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

Abstract: A multilayer capacitor includes a capacitor body including a plurality of first and second internal electrodes alternately stacked with dielectric layers interposed therebetween. A first via electrode penetrates through the plurality of first internal electrodes and is exposed at the first surface of the capacitor body. A second via electrode penetrates through the plurality of second internal electrodes, is exposed at the first surface of the capacitor body, and is spaced apart from the first via electrode. First and second external electrodes are on a first surface of the capacitor body, spaced apart from each other, and respectively connected to end portions of the first and second via electrodes. The first and second external electrodes each include a nickel (Ni) layer on the first surface of the capacitor body and a gold (Au) plating layer on the nickel layer.

Abstract: A cooling module has a heat generating body, a heat exchanger made of metal, and an insulating plate. The heat generating body has a heat dissipating surface. The heat exchanger has cooling surface facing the heat dissipating surface. The insulating plate has a first surface and a second surface. The insulating plate is interposed between the heat dissipating surface and the cooling surface on a condition that the insulating plate faces the heat dissipating surface and that the second surface faces the cooling surface. The insulating plate and the cooling surface are joined to be one body by a joining material. The heat dissipating surface and the insulating plate are in close contact with each other through an elastic member. The heat dissipating surface and the cooling surface are thermally connected to each other through the joining material, the insulating plate, and the elastic member.

Abstract: An ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package has the insulating layer between the carrier board and the substrate in the prior art replaced by an anisotropic conductive film or materials with similar structure. The anisotropic conductive film has conductive particles therein to replace the conductive openings on the insulating layer in the prior art. When compressing the substrate onto the carrier board, the bottom surface of the second electrode pads are compressing the corresponding conductive particles on the second electrical contact pads, causing which to burst, therefore forming high-density compressed areas that conduct the second electrode pads and the second electrical contact pads; the conductive particles outside the high-density compressed area are not burst, forming an insulating film between the substrate and the carrier board; in other words, the anisotropic conductive film provides conduction in a Z direction.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

Abstract: In some embodiments, a contact via and a fabricating method thereof are provided. The method can comprise: providing a substrate; forming a buffer layer in the substrate; forming a dielectric layer covering the substrate and the buffer layer; forming a through hole in the dielectric layer, wherein a bottom of the through hole exposes a surface of the buffer layer; performing a roughening treatment to the exposed surface of the buffer layer to increase a roughness of the exposed surface of the buffer layer; forming a barrier layer in the through hole, and reducing a thickness of a portion of the barrier layer at the bottom of the through hole; and filling a conductive material into the through hole to form a contact via.

Abstract: A method and apparatus comprising a first composite layer and a second composite layer in which the second composite layer is associated with the first composite layer. The first composite layer and the second composite layer form a structure. The second composite layer has a conductivity configured to dissipate an electric charge on a surface of the structure and limit a flow of an electrical current in the second composite layer in which the electrical current is caused by an electromagnetic event.

Abstract: A metal/ceramic bonding substrate includes: a ceramic substrate; a metal plate bonded directly to one side of the ceramic substrate; a metal base plate bonded directly to the other side of the ceramic substrate; and a reinforcing member having a higher strength than that of the metal base plate, the reinforcing member being arranged so as to extend from one of both end faces of the metal base plate to the other end face thereof without interrupting that the metal base plate extends between a bonded surface of the metal base plate to the ceramic substrate and the opposite surface thereof.

Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance.

Abstract: A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer.

Abstract: A device, system, and method for solar cell construction and bonding/layer transfer are disclosed herein. An exemplary structure of solar cell construction involves providing a monocrystalline donor layer. A solder bonding layer bonds the donor layer to a carrier substrate. A porous layer may be used to separate the donor layer.

Abstract: A semiconductor device bonded by an anisotropic conductive adhesive composition, the anisotropic conductive adhesive composition having a solid content ratio between a polymer binder system and a curing system of about 40:60 to about 60:40, and a coefficient of thermal expansion of about 150 ppm/° C. or less at about 100° C. or less.

Abstract: A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a binder resin; a first radical polymerization material having one or two (meth)acrylate reactive groups in a structure thereof and a second radical polymerization material having at least three (meth)acrylate reactive groups in a structure thereof; and conductive particles, the anisotropic conductive film having a moisture permeability of 170 g/m2/24 hr or less and a moisture absorbency of 2% or less.

Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.

Abstract: Provided are multimaterial devices, such as coaxial nanowires, that effect hot photoexcited electron transfer across the interface of the materials. Modulation of the transfer rates, manifested as a large tunability of the voltage onset of negative differential resistance and of voltage-current phase, may be effected by modulating electrostatic gating, incident photon energy, and the incident photon intensity. Dynamic manipulation of this transfer rate permits the introduction and control of an adjustable phase delay within a device element.

Abstract: A semiconductor device is provided with: a semiconductor element; and a connecting conductor that electrically connects at least one of an input terminal and an output terminal of the semiconductor element to a connection terminal of an electronic device. In this semiconductor device, the connecting conductor is a block structure.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube potion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.

Abstract: The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanotubes.

Abstract: A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ?5 ?m, (D) conductive micro-particles having an average particle size <5 ?m, (E) a thixotropic agent, and (F) a hydrosilylation catalyst.

Abstract: There is provided a wiring board for mounting a light emitting element thereon. The wiring board includes: an insulating layer; a wiring pattern on the insulating layer; a reflecting layer on the insulating layer to cover the wiring pattern, wherein the light emitting element is to be mounted on a surface of the reflecting layer; and a silica film on the surface of the reflecting layer.

Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.

Abstract: A method is provided for transferring a graphene sheet to metal contact bumps of a substrate that is to be used in a semiconductor device package, i.e. a stack of substrates connected by said contact bumps, e.g., copper contact bumps for which graphene forms a protective layer. An imprinter device can be used comprising an imprinter substrate, said substrate being provided with cavities, whereof each cavity is provided with a rim portion. The imprinter substrate is aligned with the substrate comprising the bumps and lowered onto said substrate so that each bump becomes enclosed by a cavity, until the rim portion of the cavities cuts through the graphene sheet, leaving graphene layer portions on top of each of bumps when the imprinter is removed. The graphene sheet is preferably attached to the substrate by imprinting it into a passivation layer surrounding the bumps.

Abstract: According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film.

Abstract: A functional material includes at least two kinds of particles selected from the group consisting of first metal composite particles, second metal composite particles and third metal composite particles. The first metal composite particles, the second metal composite particles and the third metal composite particles each contain two or more kinds of metal components. The melting point T1(° C.) of the first metal composite particles, the melting point T2(° C.) of the second metal composite particles and the melting point T3(° C.) of the third metal composite particles satisfy a relationship of T1>T2>T3.

Abstract: Various methods and apparatuses involve the provision of graphitic material. As consistent with one or more aspects herein, an organic material template is used to restrict growth, in a width dimension, of graphitic material grown from the organic material template. Graphitic material is therein provided, having a set of characteristics including electrical behavior and shape, with a representative width defined by the width dimension, based on the organic material template.

Abstract: A method of forming an edge-doped graphene channel is described. The method involves selectively removing graphene from a graphene layer on a substrate in the presence of a dopant to form graphene channels. The dopant forms bonds with carbon atoms on the edge of the graphene such that the graphene channels are edge doped. An article of manufacture is also provided which includes a substrate layer, one or more edge-doped graphene channels on the substrate layer and a layer of an etch mask material on and coextensive with the one or more graphene channels. An article of manufacture is also provided which includes a substrate layer and one or more edge-doped graphene channels on the substrate layer, wherein each of the one or more the graphene channels has a width less than 100 nm and a carrier density greater than 5×1012 cm?3.

Abstract: A three-dimension circuit structure includes a substrate, a first conductive layer, a filled material and a second conductive layer. The substrate has an upper surface and a cavity located at the upper surface. The first conductive layer covers the inside walls of the cavity and protrudes out the upper surface. The filled material fills the cavity and covers the first conductive layer. The second conductive layer covers the filled material and a portion of the first conductive layer, and the first conductive layer and the second conductive layer encapsulate the filled material. The material of the filled material is different from that of the first conductive layer and the second conductive layer.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.

Abstract: A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such a way that the second material mechanically and electrically bonds the plurality of first material particles to one another.

Abstract: A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ?5 ?m, (D) conductive micro-particles having an average particle size <5 ?m, (E) a thixotropic agent, and (F) a hydrosilylation catalyst.

Abstract: Methods for depositing nanomaterial onto a substrate are disclosed. Also disclosed are compositions useful for depositing nanomaterial, methods of making devices including nanomaterials, and a system and devices useful for depositing nanomaterials.

Abstract: A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.

Abstract: The present disclosure relates to an optoelectronic device, in particular to an arrangement for contacting an optoelectronic device. The optoelectronic device (200) includes an elastic electrode (208). A method for forming the elastic electrode (208) is described.

Abstract: A semiconductor device is provided which has internal bonds which do not melt at the time of mounting on a substrate. A bonding material is used for internal bonding of the semiconductor device. The bonding material is obtained by filling the pores of a porous metal body having a mesh-like structure and covering the surface thereof with Sn or an Sn-based solder alloy.

Abstract: It is an object of the present invention to provide a wireless chip of which mechanical strength can be increased. Moreover, it is an object of the present invention to provide a wireless chip which can prevent an electric wave from being blocked. The invention is a wireless chip in which a layer having a thin film transistor is fixed to an antenna by an anisotropic conductive adhesive or a conductive layer, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer is sandwiched between the first conductive layer and the second conductive layer. The first conductive layer serves as a radiating electrode and the second conductive layer serves as a ground contact body.

Abstract: The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nanotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nanotubes are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.

Abstract: The printed circuit board (100) includes the interposer (2) where the semiconductor element (1) is mounted and the electrode pad (8) is formed on one surface, the printed wiring board (3) where the electrode pad (9) is formed on one surface facing the interposer (2), and the joint material (70) for bonding the electrode pads (8) and (9). The joint material (70) includes the solder layer (60) formed by the solder material (11) and the metal layers (50), (50) provided to the electrode pads (8) and (9). Each metal layer (50) includes the metal particle aggregate (10) in which metal particles are integrated with voids and is formed by filling the voids in the metal particle aggregate (10) with melted solder material (11). It is possible to ensure the height of the solder, improve reliability of the bonding, and downsize the semiconductor device by using such joint material.