Composite Material (e.g., Fibers Or Strands Embedded In Solid Matrix) Patents (Class 257/746)
  • Patent number: 10325725
    Abstract: A multilayer capacitor includes a capacitor body including a plurality of first and second internal electrodes alternately stacked with dielectric layers interposed therebetween. A first via electrode penetrates through the plurality of first internal electrodes and is exposed at the first surface of the capacitor body. A second via electrode penetrates through the plurality of second internal electrodes, is exposed at the first surface of the capacitor body, and is spaced apart from the first via electrode. First and second external electrodes are on a first surface of the capacitor body, spaced apart from each other, and respectively connected to end portions of the first and second via electrodes. The first and second external electrodes each include a nickel (Ni) layer on the first surface of the capacitor body and a gold (Au) plating layer on the nickel layer.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Won Seo, Jin Kyung Joo, Ik Hwan Chang, Jin Woo Chun, Jin Man Jung
  • Patent number: 10253729
    Abstract: A cooling module has a heat generating body, a heat exchanger made of metal, and an insulating plate. The heat generating body has a heat dissipating surface. The heat exchanger has cooling surface facing the heat dissipating surface. The insulating plate has a first surface and a second surface. The insulating plate is interposed between the heat dissipating surface and the cooling surface on a condition that the insulating plate faces the heat dissipating surface and that the second surface faces the cooling surface. The insulating plate and the cooling surface are joined to be one body by a joining material. The heat dissipating surface and the insulating plate are in close contact with each other through an elastic member. The heat dissipating surface and the cooling surface are thermally connected to each other through the joining material, the insulating plate, and the elastic member.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: April 9, 2019
    Assignee: DENSO CORPORATION
    Inventors: Shingo Oono, Tomohiro Shimazu, Yasuhiro Mizuno, Ryohei Tomita
  • Patent number: 10170403
    Abstract: An ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package has the insulating layer between the carrier board and the substrate in the prior art replaced by an anisotropic conductive film or materials with similar structure. The anisotropic conductive film has conductive particles therein to replace the conductive openings on the insulating layer in the prior art. When compressing the substrate onto the carrier board, the bottom surface of the second electrode pads are compressing the corresponding conductive particles on the second electrical contact pads, causing which to burst, therefore forming high-density compressed areas that conduct the second electrode pads and the second electrical contact pads; the conductive particles outside the high-density compressed area are not burst, forming an insulating film between the substrate and the carrier board; in other words, the anisotropic conductive film provides conduction in a Z direction.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: January 1, 2019
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nung Lin
  • Patent number: 10003028
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: June 19, 2018
    Assignee: INTEL CORPORATION
    Inventor: Hans-Joachim Barth
  • Patent number: 9978677
    Abstract: In some embodiments, a contact via and a fabricating method thereof are provided. The method can comprise: providing a substrate; forming a buffer layer in the substrate; forming a dielectric layer covering the substrate and the buffer layer; forming a through hole in the dielectric layer, wherein a bottom of the through hole exposes a surface of the buffer layer; performing a roughening treatment to the exposed surface of the buffer layer to increase a roughness of the exposed surface of the buffer layer; forming a barrier layer in the through hole, and reducing a thickness of a portion of the barrier layer at the bottom of the through hole; and filling a conductive material into the through hole to form a contact via.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: May 22, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Ji Quan Liu
  • Patent number: 9840338
    Abstract: A method and apparatus comprising a first composite layer and a second composite layer in which the second composite layer is associated with the first composite layer. The first composite layer and the second composite layer form a structure. The second composite layer has a conductivity configured to dissipate an electric charge on a surface of the structure and limit a flow of an electrical current in the second composite layer in which the electrical current is caused by an electromagnetic event.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: December 12, 2017
    Assignee: THE BOEING COMPANY
    Inventors: Noel Timothy Gerken, Quynhgiao Nguyen Le
  • Patent number: 9713253
    Abstract: A metal/ceramic bonding substrate includes: a ceramic substrate; a metal plate bonded directly to one side of the ceramic substrate; a metal base plate bonded directly to the other side of the ceramic substrate; and a reinforcing member having a higher strength than that of the metal base plate, the reinforcing member being arranged so as to extend from one of both end faces of the metal base plate to the other end face thereof without interrupting that the metal base plate extends between a bonded surface of the metal base plate to the ceramic substrate and the opposite surface thereof.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: July 18, 2017
    Assignee: DOWA METALTECH CO., LTD.
    Inventors: Hideyo Osanai, Takayuki Takahashi, Satoru Ideguchi, Hirotaka Kotani
  • Patent number: 9704802
    Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 11, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao T. Liu
  • Patent number: 9601413
    Abstract: A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: March 21, 2017
    Assignee: UBOTIC COMPANY LIMITED
    Inventor: Chun Ho Fan
  • Patent number: 9589696
    Abstract: A semiconductor device bonded by an anisotropic conductive adhesive composition, the anisotropic conductive adhesive composition having a solid content ratio between a polymer binder system and a curing system of about 40:60 to about 60:40, and a coefficient of thermal expansion of about 150 ppm/° C. or less at about 100° C. or less.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: March 7, 2017
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Hyun Hee Namkung, Jae Sun Han, Hyun Wook Kim, Jin Young Seo, Kwang Jin Jung, Dong Seon Uh
  • Patent number: 9590130
    Abstract: A device, system, and method for solar cell construction and bonding/layer transfer are disclosed herein. An exemplary structure of solar cell construction involves providing a monocrystalline donor layer. A solder bonding layer bonds the donor layer to a carrier substrate. A porous layer may be used to separate the donor layer.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 7, 2017
    Assignee: AMBERWAVE INC.
    Inventors: Anthony Lochtefeld, Chris Leitz, Mark Carroll
  • Patent number: 9177935
    Abstract: A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a binder resin; a first radical polymerization material having one or two (meth)acrylate reactive groups in a structure thereof and a second radical polymerization material having at least three (meth)acrylate reactive groups in a structure thereof; and conductive particles, the anisotropic conductive film having a moisture permeability of 170 g/m2/24 hr or less and a moisture absorbency of 2% or less.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: November 3, 2015
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Youn Jo Ko, Hye Su Ki, Ie Ju Kim
  • Patent number: 9107312
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 11, 2015
    Assignees: VORBECK MATERIALS CORPORATION, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'Homme
  • Patent number: 9059264
    Abstract: Provided are multimaterial devices, such as coaxial nanowires, that effect hot photoexcited electron transfer across the interface of the materials. Modulation of the transfer rates, manifested as a large tunability of the voltage onset of negative differential resistance and of voltage-current phase, may be effected by modulating electrostatic gating, incident photon energy, and the incident photon intensity. Dynamic manipulation of this transfer rate permits the introduction and control of an adjustable phase delay within a device element.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: June 16, 2015
    Assignee: Drexel University
    Inventors: Jonathan E Spanier, Guannan Chen, Eric M Gallo, Baris Taskin
  • Patent number: 9048721
    Abstract: A semiconductor device is provided with: a semiconductor element; and a connecting conductor that electrically connects at least one of an input terminal and an output terminal of the semiconductor element to a connection terminal of an electronic device. In this semiconductor device, the connecting conductor is a block structure.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: June 2, 2015
    Assignee: KEIHIN CORPORATION
    Inventors: Hidefumi Abe, Seiichiro Abe, Toru Shiba, Takuya Yagi, Toshiro Mayumi
  • Publication number: 20150137370
    Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube potion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.
    Type: Application
    Filed: December 4, 2014
    Publication date: May 21, 2015
    Inventors: Xinpeng WANG, Haiyang ZHANG
  • Publication number: 20150137371
    Abstract: The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanotubes.
    Type: Application
    Filed: December 15, 2014
    Publication date: May 21, 2015
    Inventors: Ahmed Busnaina, Cihan Yilmaz, TaeHoon Kim, Sivasubramanian Somu
  • Patent number: 9018095
    Abstract: A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ?5 ?m, (D) conductive micro-particles having an average particle size <5 ?m, (E) a thixotropic agent, and (F) a hydrosilylation catalyst.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 28, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Yoshitaka Hamada
  • Patent number: 9006894
    Abstract: There is provided a wiring board for mounting a light emitting element thereon. The wiring board includes: an insulating layer; a wiring pattern on the insulating layer; a reflecting layer on the insulating layer to cover the wiring pattern, wherein the light emitting element is to be mounted on a surface of the reflecting layer; and a silica film on the surface of the reflecting layer.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 14, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazutaka Kobayashi, Yasuyoshi Horikawa, Mitsuhiro Aizawa, Koji Hara
  • Patent number: 8975747
    Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: March 10, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Ando, Ryoichi Kajiwara, Hiroshi Hozoji
  • Patent number: 8974617
    Abstract: A method is provided for transferring a graphene sheet to metal contact bumps of a substrate that is to be used in a semiconductor device package, i.e. a stack of substrates connected by said contact bumps, e.g., copper contact bumps for which graphene forms a protective layer. An imprinter device can be used comprising an imprinter substrate, said substrate being provided with cavities, whereof each cavity is provided with a rim portion. The imprinter substrate is aligned with the substrate comprising the bumps and lowered onto said substrate so that each bump becomes enclosed by a cavity, until the rim portion of the cavities cuts through the graphene sheet, leaving graphene layer portions on top of each of bumps when the imprinter is removed. The graphene sheet is preferably attached to the substrate by imprinting it into a passivation layer surrounding the bumps.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 10, 2015
    Assignees: IMEC, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu
  • Publication number: 20150061133
    Abstract: According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film.
    Type: Application
    Filed: February 10, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsunobu ISOBAYASHI, Akihiro KAJITA, Tadashi SAKAI
  • Publication number: 20150054158
    Abstract: A functional material includes at least two kinds of particles selected from the group consisting of first metal composite particles, second metal composite particles and third metal composite particles. The first metal composite particles, the second metal composite particles and the third metal composite particles each contain two or more kinds of metal components. The melting point T1(° C.) of the first metal composite particles, the melting point T2(° C.) of the second metal composite particles and the melting point T3(° C.) of the third metal composite particles satisfy a relationship of T1>T2>T3.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 26, 2015
    Applicant: NAPRA CO., LTD.
    Inventors: Shigenobu Sekine, Yurina Sekine
  • Patent number: 8957406
    Abstract: Various methods and apparatuses involve the provision of graphitic material. As consistent with one or more aspects herein, an organic material template is used to restrict growth, in a width dimension, of graphitic material grown from the organic material template. Graphitic material is therein provided, having a set of characteristics including electrical behavior and shape, with a representative width defined by the width dimension, based on the organic material template.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: February 17, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Anatoliy N. Sokolov, Fung Ling Yap, Zhenan Bao, Nan Liu
  • Publication number: 20150014853
    Abstract: A method of forming an edge-doped graphene channel is described. The method involves selectively removing graphene from a graphene layer on a substrate in the presence of a dopant to form graphene channels. The dopant forms bonds with carbon atoms on the edge of the graphene such that the graphene channels are edge doped. An article of manufacture is also provided which includes a substrate layer, one or more edge-doped graphene channels on the substrate layer and a layer of an etch mask material on and coextensive with the one or more graphene channels. An article of manufacture is also provided which includes a substrate layer and one or more edge-doped graphene channels on the substrate layer, wherein each of the one or more the graphene channels has a width less than 100 nm and a carrier density greater than 5×1012 cm?3.
    Type: Application
    Filed: December 20, 2013
    Publication date: January 15, 2015
    Applicant: Harper Laboratories, LLC
    Inventors: Kevin BRENNER, Romeil SANDHU
  • Patent number: 8932950
    Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: January 13, 2015
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xinpeng Wang, Haiyang Zhang
  • Patent number: 8933563
    Abstract: A three-dimension circuit structure includes a substrate, a first conductive layer, a filled material and a second conductive layer. The substrate has an upper surface and a cavity located at the upper surface. The first conductive layer covers the inside walls of the cavity and protrudes out the upper surface. The filled material fills the cavity and covers the first conductive layer. The second conductive layer covers the filled material and a portion of the first conductive layer, and the first conductive layer and the second conductive layer encapsulate the filled material. The material of the filled material is different from that of the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: January 13, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh
  • Patent number: 8922016
    Abstract: A method for producing a composite material, associated composite material and associated semiconductor circuit arrangements is disclosed. A plurality of first electrically conducting material particles are applied to a carrier substrate and a second electrically conducting material is galvanically deposited on a surface of the first material particles in such a way that the second material mechanically and electrically bonds the plurality of first material particles to one another.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Daniel Kraft, Friedrich Kroener, Francisco Javier Santos Rodriguez, Carsten Von Koblinski
  • Publication number: 20140374905
    Abstract: A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ?5 ?m, (D) conductive micro-particles having an average particle size <5 ?m, (E) a thixotropic agent, and (F) a hydrosilylation catalyst.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 25, 2014
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Yoshitaka Hamada
  • Patent number: 8907482
    Abstract: A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 9, 2014
    Assignee: Honeywell International Inc.
    Inventor: David Scheid
  • Patent number: 8906804
    Abstract: Methods for depositing nanomaterial onto a substrate are disclosed. Also disclosed are compositions useful for depositing nanomaterial, methods of making devices including nanomaterials, and a system and devices useful for depositing nanomaterials.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: December 9, 2014
    Assignee: QD Vision, Inc.
    Inventors: Seth Coe-Sullivan, Maria J. Anc, LeeAnn Kim, John E. Ritter, Marshall Cox, Craig Breen, Vladimir Bulovic, Ioannis Kymissis, Robert F. Praino, Jr.
  • Patent number: 8907354
    Abstract: The present disclosure relates to an optoelectronic device, in particular to an arrangement for contacting an optoelectronic device. The optoelectronic device (200) includes an elastic electrode (208). A method for forming the elastic electrode (208) is described.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andrew Ingle
  • Patent number: 8896119
    Abstract: A semiconductor device is provided which has internal bonds which do not melt at the time of mounting on a substrate. A bonding material is used for internal bonding of the semiconductor device. The bonding material is obtained by filling the pores of a porous metal body having a mesh-like structure and covering the surface thereof with Sn or an Sn-based solder alloy.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: November 25, 2014
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Yoshitsugu Sakamoto, Hiroyuki Yamada, Yoshie Yamanaka, Tsukasa Ohnishi, Shunsaku Yoshikawa, Kenzo Tadokoro
  • Publication number: 20140319684
    Abstract: It is an object of the present invention to provide a wireless chip of which mechanical strength can be increased. Moreover, it is an object of the present invention to provide a wireless chip which can prevent an electric wave from being blocked. The invention is a wireless chip in which a layer having a thin film transistor is fixed to an antenna by an anisotropic conductive adhesive or a conductive layer, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer is sandwiched between the first conductive layer and the second conductive layer. The first conductive layer serves as a radiating electrode and the second conductive layer serves as a ground contact body.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Yukie SUZUKI, Yasuyuki ARAI, Shunpei YAMAZAKI
  • Patent number: 8853856
    Abstract: The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nanotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nanotubes are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Maxime Darnon, Gerald W. Gibson, Pratik P. Joshi, Qinghuang Lin
  • Publication number: 20140231996
    Abstract: The printed circuit board (100) includes the interposer (2) where the semiconductor element (1) is mounted and the electrode pad (8) is formed on one surface, the printed wiring board (3) where the electrode pad (9) is formed on one surface facing the interposer (2), and the joint material (70) for bonding the electrode pads (8) and (9). The joint material (70) includes the solder layer (60) formed by the solder material (11) and the metal layers (50), (50) provided to the electrode pads (8) and (9). Each metal layer (50) includes the metal particle aggregate (10) in which metal particles are integrated with voids and is formed by filling the voids in the metal particle aggregate (10) with melted solder material (11). It is possible to ensure the height of the solder, improve reliability of the bonding, and downsize the semiconductor device by using such joint material.
    Type: Application
    Filed: October 3, 2012
    Publication date: August 21, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshitomo Fujisawa
  • Publication number: 20140225260
    Abstract: A method of producing an electro-optic device includes providing a substructure, depositing a network of nanowires on the substructure, depositing a sol-gel solution on the network of nanowires and the substructure, and removing solvent from the sol-gel solution to provide fusing material that causes junctions of nanowires within the network of nanowires to fuse together to reduce electrical sheet resistance of the network of nanowires. An electro-optic device includes a sub-structure, a network of nanowires deposited on the substructure, and a plurality of nanoparticles attached to the network of nanowires. The plurality of nanoparticles fuse junctions of overlapping nanowires together to reduce electrical sheet resistance of the network of nanowires.
    Type: Application
    Filed: September 13, 2012
    Publication date: August 14, 2014
    Applicant: The Regents of the University of California
    Inventors: Yang Yang, Rui Zhu
  • Publication number: 20140210084
    Abstract: A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a binder resin; a first radical polymerization material having one or two (meth)acrylate reactive groups in a structure thereof and a second radical polymerization material having at least three (meth)acrylate reactive groups in a structure thereof; and conductive particles, the anisotropic conductive film having a moisture permeability of 170 g/m2/24 hr or less and a moisture absorbency of 2% or less.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 31, 2014
    Inventors: Youn Jo KO, Hye Su KI, Ie Ju KIM
  • Publication number: 20140191399
    Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.
    Type: Application
    Filed: August 13, 2012
    Publication date: July 10, 2014
    Inventors: Takashi Ando, Ryoichi Kajiwara, Hiroshi Hozoji
  • Patent number: 8766443
    Abstract: An anisotropic conductive film composition for bonding an electronic device may include a hydrogenated bisphenol A epoxy monomer represented by Formula 1 or a hydrogenated bisphenol A epoxy oligomer represented by Formula 2: where n may be an integer from 1 to about 50.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 1, 2014
    Assignee: Cheil Industries, Inc.
    Inventors: Arum Yu, Nam Ju Kim, Kyoung Soo Park, Young Woo Park, Joon Mo Seo, Kyung Il Sul, Dong Seon Uh, Hyun Min Choi
  • Publication number: 20140138828
    Abstract: A semiconductor device including a first connecting member including a first electrode; a second connecting member including a second electrode; and an anisotropic conductive film between the first connecting member and the second connecting member, the anisotropic conductive film bonding the first electrode to the second electrode, wherein the anisotropic conductive film exhibits linear indentations in an inter-terminal space of the second connecting member after pre-compression and primary compression of the anisotropic conductive film onto the first and second connecting members.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 22, 2014
    Inventors: Do Hyun PARK, Kyu Bong KIM, Woo Jun LIM
  • Publication number: 20140138829
    Abstract: The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome.
    Type: Application
    Filed: December 31, 2011
    Publication date: May 22, 2014
    Applicant: SHANGHAI IC R&D CENTER CO., LTD.
    Inventors: Yuhang Zhao, Xiaoxu Kang
  • Publication number: 20140124931
    Abstract: A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a polyurethane resin; at least one other resin selected from the group of an ethylene-vinyl acetate copolymer resin, an acrylonitrile resin, and a styrene resin; isobornyl acrylate; and conductive particles.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 8, 2014
    Inventors: Young Ju SHIN, Kyu Bong KIM, Hyun Joo SEO, Kyoung Hun SHIN, Woo Jun LIM
  • Patent number: 8716863
    Abstract: The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsingjen Wann, Ting-Chu Ko
  • Publication number: 20140103297
    Abstract: Various methods and apparatuses involve the provision of graphitic material. As consistent with one or more aspects herein, an organic material template is used to restrict growth, in a width dimension, of graphitic material grown from the organic material template. Graphitic material is therein provided, having a set of characteristics including electrical behavior and shape, with a representative width defined by the width dimension, based on the organic material template.
    Type: Application
    Filed: August 30, 2013
    Publication date: April 17, 2014
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Anatoliy N. Sokolov, Fung Ling Yap, Zhenan Bao, Nan Liu
  • Patent number: 8698322
    Abstract: A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 15, 2014
    Assignee: Oracle International Corporation
    Inventors: Robert J. Drost, Ashok V. Krishnamoorthy, John E. Cunningham
  • Publication number: 20140084468
    Abstract: A semiconductor device includes a first connecting member having a first electrode, a second connecting member having a second electrode, and an anisotropic conductive film between the first connecting member and the second connecting member, the anisotropic conductive film electrically connecting the first and second electrodes to each other. The anisotropic conductive film includes a polymer binder resin, an epoxy resin, conductive particles, and a curing agent. The epoxy resin includes a naphthalene ring-containing epoxy resin and a dicyclopentadiene ring-containing epoxy resin. The naphthalene ring-containing epoxy resin is included in an amount of 100 parts by weight to 500 parts by weight based on 100 parts by weight of the dicyclopentadiene ring-containing epoxy resin.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 27, 2014
    Inventors: Young Woo PARK, Joon Mo SEO, Hyun Min CHOI, Ji Yeon KIM, Kyoung Soo PARK, Arum YU, Jong Hyuk EUN
  • Patent number: 8680678
    Abstract: A conductive electrode paste or ink formulation including a getter removes or reduces the concentration of the unwanted impurities in an electronic device. These reductions may happen during or immediately after the fabrication or sealing of the device, or they may occur after some activation time or event. Water, oxygen, carbon dioxide, hydrogen, and residual solvents are gettered.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: March 25, 2014
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventors: John Devin MacKenzie, Jian Ping Chen
  • Patent number: 8674520
    Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Nobuhiro Imaizumi, Keishiro Okamoto, Keiji Watanabe
  • Publication number: 20140057428
    Abstract: A layer of material having a low thermal conductivity is coated over a substrate. A film of conductive ink is then coated over the layer of material having the low thermal conductivity, and then sintered. The film of conductive ink does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity maybe a polymer, such as polyimide.
    Type: Application
    Filed: November 7, 2013
    Publication date: February 27, 2014
    Applicant: APPLIED NANOTECH HOLDINGS, INC.
    Inventors: Zvi Yaniv, Mohshi Yang, Peter B. Laxton