Abstract: A microelectronic network is fabricated on a fibrous skeleton by binding or complexing electronically functional substances to the nucleic acid skeleton. The skeleton comprises fibers with nucleotide chains.

Abstract: A semiconductor device has a dielectric film made of a fluorine-added carbon film formed on a substrate, a metallic layer formed on the fluorine-added carbon film and an adhesive layer formed between the dielectric film and the metallic layer. The adhesive layer is made of a compound layer having carbon and the metal (or metal the same as the metal included in the metallic layer), to protect the metallic layer from being peeled-off from the fluorine-added carbon film.

Abstract: The present invention relates generally to a new apparatus and method for introducing thermal paste into semiconductor packages. More particularly, the invention encompasses an apparatus and a method that uses at least one preform of thermal paste for the cooling of at least one chip in a sealed semiconductor package. The thermal paste preform is subcooled, and is transferred onto a module component from a separable transfer sheet, or is placed onto the module component using an attached and/or imbedded mesh. The preform of thermal paste may be of simple or complex shape, and enables cooling of one or more chips in a module.

Abstract: A semiconductor device, comprising an electrode on a base surface, a bump formed on the electrode, a pad, and a means of connection. The means of connection comprises a plurality of conductive particles, conducting the bump and the pad with conductive particles bonded between. The base surface is further formed with a barrier rib that separates the conductive particles.

Abstract: An electronic device includes a first conductive polymer layer sandwiched between a first external metal foil electrode and a first internal metal foil electrode, a second conductive polymer layer sandwiched between a second internal metal foil electrode and a second external metal foil electrode, a layer of fiber-reinforced epoxy resin bonding the first and second internal electrodes together, a first terminal providing electrical contact between the first internal electrode and the second external electrode, and a second terminal providing electrical contact between the second internal electrode and the first external electrode. In a preferred embodiment, the polymer layers exhibit PTC behavior, and the terminals are formed by a solder layer applied over a plated layer of conductive metal. Insulative layers are preferably provided on the external electrodes, and located so as to insulate the first and second terminals from each other.

Abstract: The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

Abstract: An article of manufacture and method of forming nanoparticle sized material components. A semiconductor oxide substrate includes nanoparticles of semiconductor oxide. A modifier is deposited onto the nanoparticles, and a source of metal ions are deposited in association with the semiconductor and the modifier, the modifier enabling electronic hole scavenging and chelation of the metal ions. The metal ions and modifier are illuminated to cause reduction of the metal ions to metal onto the semiconductor nanoparticles.

Abstract: Process for producing electrical connections on the surface of a semiconductor package containing an integrated-circuit chip and having metal electrical-connection regions on the surface of the package, consisting of: covering these connection regions with a first metal layer forming an anti-diffusion barrier; covering this first layer with an anti-oxidation second metal layer; and depositing a metal solder drop or solder ball on the second metal layer. The solder drop comprises an addition of metal particles in suspension which contain at least one of the metals of the first metal layer so as to produce a precipitate comprising these additional metal particles and at least partly the metal of the second metal layer, the precipitate remaining in suspension in the solder drop.

Abstract: According to various disclosed embodiments, a conductor is patterned in a dielectric. The conductor can be patterned, for example, in the shape of a square spiral. The conductor can comprise, for example, copper, aluminum, or copper-aluminum alloy. The dielectric can be, for example, silicon oxide or a low-k dielectric. A spin-on matrix containing high permeability particles is then deposited adjacent to the patterned conductor. The high permeability particles comprise material having a permeability substantially higher than the permeability of the dielectric. The high permeability particles can comprise, for example, nickel, iron, nickel-iron alloy, or magnetic oxide. As a result, an inductor having a high inductance value is achieved without lowering the quality factor of the inductor.

Abstract: A conductive adhesive agent of the invention contains an elution preventing film-forming agent 4, which becomes reactive after electric continuity through a conductive particle 3 appeared in the conductive adhesive agent when a binder resin 2 is being hardened, to thereby form an elution preventing film 5 on a surface of the conductive particle 3. By using this conductive adhesive agent, the packaging structure is made migration resistant and sulfurization resistant.

Abstract: An improved wear resistant bump contact is produced by the inclusion of small particles of hard materials in the conductive material of the contact bump, preferably by co-deposition at the time of electroplating of the bump bulk material. Desirable attributes of the small particles of hard material include small particle size, hardness greater than the hardness of the bulk material of the contact bump, compatibility with the plating conditions, and electrical conductivity. Nitride, borides, silicides, carbides are typical interstitial compounds suitable for use in satisfying these desirable attributes. In one preferred example, a nickel bulk material and silicon carbide particles are utilized. In one variation, the bump of metal-particle co-deposited material is coated by a thin cap layer of noble, non-oxidizing metal to prevent electrical erosion by arcing as contact is made and broken from the pad. Rhodium and ruthenium are suitable metals and can be electrodeposition over the composite bump structure.

Abstract: Refractory metal articles having hither than normal impurity levels of concentrations of additive species near the surface that promote chemically enhanced sintering without any adverse effect on function properties, including, among others, tantalum or niobium lead wires that form assemblies useful as electrolytic capacitor anodes and the like, as made by surface oxidation of the wire, embedding a wire end in a loose mass of the powder and sintering to producing assemblies of enhanced structural integrity and affording stable electrical characteristics of electrical devices including such assemblies.

Abstract: A thermal joint for facilitating heat transfer between two components is described. The thermal joint is formed from an alloy of at least two constituents. The alloy has a liquid temperature and a solid temperature. When the operating temperature falls between the liquid temperature and the solid temperature, the alloy has at least one liquid phase which is in substantial equilibrium with at least one solid phase. The thermal joint is used between a heat-generating component, such as a semiconducting device, and a heat-dissipating component, such as a heat sink. Such thermal joint substantially reduces the thermal resistance between the two components.

Abstract: Described is an electronic device having a compliant fibrous interface. The interface comprises a free fiber tip structure having flocked thermally conductive fibers embedded in an adhesive in substantially vertical orientation with portions of the fibers extending out of the adhesive and an encapsulant between the portions of the fibers that extend out of the adhesive and the fiber's free tips.

Abstract: Methods of forming a graded layer is disclosed. The graded layer transitions from one material to another material. The properties of these materials are chosen to optimize the interfaces on each side of the graded layer. Specifically, an improved transistor gate stack barrier layer may be formed by disposing an appropriate graded layer between a gate layer and an interconnect layer. In fact, the graded layer may obviate the use of the interconnect layer, as the top of the graded layer may include a highly conductive material. An improved integrated circuit interconnect structure may also be formed by grading the material composition of an interconnect layer.

Abstract: Ceramics for wiring boards having an SiO2 crystal phase, a spinel type oxide crystal phase containing Mg or Zn and Al and a composite oxide type crystal phase containing at least Sr, Al and Si, and having a coefficient of thermal expansion of not smaller than 5.5 ppm/° C. at room temperature through up to 400° C., a dielectric constant of not larger than 7, and a dielectric loss of not larger than 50×10−4 at 20 to 30 GHz. The ceramics can be obtained by the co-firing with a low-resistance metal such as copper or silver, and can be advantageously applied for the production of a wiring board for treating, particularly, signals of high frequencies. Furthermore, the ceramics has a coefficient of thermal expansion which is so large as can be brought close to the coefficient of thermal expansion of the semiconductor element such as GaAs or of the printed board.

Abstract: An object of the invention is to provide a light emitting diode which enables relatively easy fabrication of large-area displays and is applicable to thin, long life, low cost, full color displays too. The object is attained by a light emitting diode comprising a positive electrode, a negative electrode, an inorganic light emitting layer between the electrodes exhibiting at least electroluminescence, a high resistance inorganic electron transporting layer between the inorganic light emitting layer and the negative electrode, capable of blocking holes and having conduction paths for carrying electrons, and an inorganic hole transporting layer between the inorganic light emitting layer and the positive electrode, the inorganic hole transporting layer being a high resistance inorganic hole transporting layer capable of blocking electrons and having conduction paths for carrying holes.

Abstract: A composite conductor for contacting a semiconductor device chip. A durable substrate subassembly for a high power transistor switching modules. The substrate subassembly is durable because wire bonds to the semiconductor device electrodes are replaced with a soldered metal/ceramic composite conductor. The part of the composite conductor contacting the semiconductor device has a coefficient of thermal expansion close to that of the semiconductor device. The substrate in the substrate subassembly has automatic alignment features. The composite conductor also has automatic alignment features, along with stress relief features. Automatic alignment permits concurrent soldering of the chip to the substrate, and the composite conductor to the chip and to a terminal contact.

Abstract: An embodiment of the invention includes an integrated circuit package having a substrate, an integrated circuit mounted to the substrate, a thermal element, and a heat pipe disposed between the integrated circuit and the thermal element. The heat pipe includes a retaining structure impregnated with a thermal grease. The heat pipe is a result of a process that includes the step of impregnating the retaining structure with a thermal grease prior to disposing the heat pipe between the integrated circuit and the thermal element.

Abstract: In a substrate, a device hole is punched, and a metal wiring pattern is formed on the substrate. Then, an insulating film is formed from the side of the metal wiring pattern so as to cover at least the device hole. In this state, the insulating film is formed for fixing the inner leads of the metal wiring pattern, which are projected on the device hole. Then, the semiconductor chip is provided so as to face the device hole from the side of the substrate, and the electrode is connected to the inner leads via the ACF by thermocompression. The described arrangement is provided so as to realize an extremely narrow frame in a liquid crystal module. According to the described method, a quality TCP semiconductor device can be manufactured in a simple manner at high yield.

Abstract: Conductive interconnections are formed by depositing an adhesive material, made up of ferromagnetic particles dispersed within a matrix material, on a semiconductor substrate, such as an electronic component, and applying a magnetic field between an exposed surface of the adhesive material and an attached surface of the adhesive material (abutting the semiconductor substrate), such that a plurality of the ferromagnetic particles move and align within the matrix material under the influence of the magnetic field. One method of the present invention comprises depositing the adhesive material on a contact site of a first electronic component. A second electronic component having a contact site is aligned over the adhesive material and a magnetic field is applied between the first electronic component and the second electronic component.

Abstract: Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement.

Abstract: Metal heated to a molten state is injected under a high hydrostatic penetration pressure into extremely small and closely spaced channels of an insulating matrix to form an array of electrically conductive pins or wires. The materials for the pins and matrix are selected for compatibility with respect to melting, matrix sintering and surface tension penetration conditions associated with the fabrication of a high density charge transfer device.

Abstract: A ball grid array (BGA) semiconductor package includes a package case having a recess in an upper surface thereof, a semiconductor chip received in the recess, and a connection means provided on an active region of the chip. A molding compound molds the chip and fills a gap between the package case and the connection member. The package enables a thinner package fabrication and reduces an access time of a package device, thereby realizing a high speed device.

Abstract: An improved wear resistant bump contact is produced by the inclusion of small particles of hard materials in the conductive material of the contact bump, preferably by co-deposition at the time of electroplating of the bump bulk material. Desirable attributes of the small particles of hard material include small particle size, hardness greater than the hardness of the bulk material of the contact bump, compatibility with the plating conditions, and electrical conductivity. Nitride, borides, suicides, carbides are typical interstitial compounds suitable for use in satisfying these desirable attributes. In one preferred example, a nickel bulk material and silicon carbide particles are utilized. In one variation, the bump of metal-particle co-deposited material is coated by a thin cap layer of noble, non-oxidizing metal to prevent electrical erosion by arcing as contact is made and broken from the pad. Rhodium and ruthenium are suitable metals and can be electrodeposited over the composite bump structure.

Abstract: The specification describes a thermocompression bonding process using anisotropic conductive film (ACF) bonding material in which the bonding pads are shaped to prevent depletion of conductive particles in the bonding region during compression. The process is useful in bump technology for interconnecting component assemblies on substrates such as glass, printed wiring boards, etc. The shaped structure can be made using photodefinable polymer strips around the bonding pads where the strips are thicker than the bonding pad. Alternative approaches to shaping one or both of the mating conductive surfaces are disclosed.

Abstract: An electronic device that is equipped with a plurality of bonding pads positioned on the device for making electrical interconnections and electrically conductive composite bumps adhered to the bonding pads wherein the bumps are formed of a composite material consisting of a thermoplastic polymer and at least about 30 volume percent of conductive metal particles based on the total volume of the metal particles and the thermoplastic polymer. The present invention is also directed to a method of making electrical interconnections to an electronic device by pressing a plurality of composite bumps of a polymeric based material against a substrate having an electrically conductive surface by mechanical means under a sufficient temperature and/or a sufficient pressure.

Abstract: A heat spreader for a semiconductor device is constituted by an integral laminate of alternatingly stacked and diffusion-bonded Fe-Ni alloy sheets and copper-group metal sheets, the laminate having a one-directional stripe pattern of the Fe-Ni alloy sheets and the copper-group metal sheets, which appears on a planar surface on which a silicon chip is disposed. It is produced by (a) alternatingly stacking Fe-Ni alloy sheets and copper-group metal sheets, (b) hot isostatic-pressing the resulting stack of the metal sheets to form a slab, (c) rolling the slab vertically to the laminating direction of the metal sheets to form an integrated stripe-pattern laminate, and (d) cutting the integrated stripe-pattern laminate to a predetermined shape.

Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: A thermal interface 26 between a heat source (e.g., an IC die) 24 and a heat sink 28 comprises a metallic mesh (26a) filled with a thermally conductive semi-liquid substance (26b). The thermally conductive semi-liquid substance may comprise, e.g., silicone grease or paraffin. The wire mesh may comprise silver, copper and/or gold cloth.

Abstract: Enhanced flux pinning in superconductors is achieved by embedding carbon nanotubes into a superconducting matrix. The carbon nanotubes simulate the structure, size and shape of heavy ion induced columnar defects in a superconductor such as Bi.sub.2 Sr.sub.2 CaCu.sub.2 O.sub.8+x. The nanotubes survive at treatment temperatures of up to approximately 800.degree. C. both in oxygen containing and in inert atmospheres. The superconducting matrix with nanotubes is heat treated at a lower temperature than the temperature used to treat the best case pure superconductor material.

Abstract: An integrated circuit package, and integrated circuit assembly having such a package, includes a base portion and a cover portion which cooperatively enclose an integrated circuit chip. The base and cover portions are formed of composite material and have matching coefficients of thermal expansion. Because the base and cover portions each match the other's thermal expansions and contractions, no stresses are generated in the package from heating and cooling during and following operation of the integrated circuit chip, and no such thermally produced physical stresses are transferred to the circuit chip to shorten its life. A version of the package includes plural lamina, and may include facial metallic coating layers on the lamina for shielding, electromagnetic shielding, and electrical interconnection of the integrated circuit chip. Another version of the package utilizes the facial metallic coating layers to join portions of the package by soldering.

Abstract: A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21), and the second porous die mount (22) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20), the first porous die mount (21), and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.

Abstract: An ASIC type microcircuit package assembly has a die of at least about 20 millimeters square in size and utilizes as a die attach a polymeric adhesive incorporating a conductive filler. Such microcircuit package assemblies are produced by bonding the die to a substrate with the die attach, curing the die attach, and hermetically sealing the die bonded to the substrate. The microcircuit package assemblies thereby produced are characterized by stability at temperatures of up to about 360.degree. C. and under conditions of stress corresponding to a 12 pound pull following 1,000 temperature cycles between -65.degree. and 150.degree. C., and having a moisture level of less than about 5000 ppm.

Abstract: The invention provides a nanometer sized carbon tubule enclosing a foreign material except for carbon. The carbon tubule comprises a plurality of tubular graphite monoatomic sheets coaxially arranged. The foreign material is introduced through a top portion of the carbon tubule. The introduction of the foreign material is accomplished after forming an opening at the top portion of the carbon tubule either by contacting the foreign material with the top portion of the carbon tubule together with a heat treatment or by an evaporation of the foreign material on the top portion of the carbon tubule together with the heat treatment. The foreign material is introduced only in a center hollow space defined by an internal surface of the most inner tubular graphite monoatomic sheet.

Abstract: A wire bonding method comprising the steps of (a) disconnecting a first wire which is bonded on a first pad which is provided on a substrate, (b) forming a second pad on the first pad, and (c) bonding a second wire on the second pad, so that the second wire is electrically connected to the first pad. The step (a) may completely remove the first wire from the first pad, and the step (b) may form the second pad at least on a top surface of the first pad including a part which is damaged by the removal of the first wire. On the other hand, the step (a) may cut the first wire so that a tip end of the first wire remains bonded on the first pad, and the step (b) may form the second pad at least on a top surface of the first pad so as to completely cover the remaining tip end of the first wire.

Abstract: A photovoltaic device of this invention has a semiconductor layer for generating a photovoltaic power and a collector electrode formed on the semiconductor layer to collect the power generated by the semiconductor layer. A conductive layer containing a conductive powder is formed on at least one side of the collector electrode closer to the semiconductor layer, and a metal layer is formed on the side away from the semiconductor layer. The metal layer covers the surface of the conductive layer away from the semiconductor layer.

Abstract: An active matrix substrate in which signals are inputted by a drive IC to a plurality of gate wirings made of aluminum or the like so as to drive a plurality of pixel electrodes such that an image is formed, said active matrix substrate comprising: a drive IC mounting portion which is formed together with the pixel electrodes on a principal face of a substrate by an indium-tin-oxide (ITO) film identical with that forming the pixel electrodes; wherein the gate wirings are disposed on the ITO film of the drive IC mounting portion so as to be directly connected to the ITO film.

Abstract: A photovoltaic element has a photoelectric conversion layer and a collecting electrode formed thereon by curing a paste having at least an electroconductive base substance and a curable resin formed on the photoelectric conversion layer. The number average molecular weight of the curable resin is 3000 or less.

Abstract: A method for producing a linear pattern having a width less than 100 microns and a resistivity of the order of 10.sup.-6 .OMEGA..multidot.cm on a substrate includes maintaining a low melting point metal in its fused state, applying the fused metal to a tip of a drawing head disposed close to or contacting a substrate by capillary action, applying the fused metal to the substrate in a line with a width less than 100 microns while moving the tip of the drawing head relative to the substrate, and cooling and solidifying the linear pattern of fused metal. Therefore, a linear pattern having a width less than 100 microns and a resistivity of the order of 10.sup.-6 .OMEGA..multidot.cm is directly formed on the substrate in a simple process with high efficiency and the production yield is significantly improved.

Abstract: A method for forming a solder bump on an integrated circuit die utilizes a terminal (12) formed of an electrically conductive, solder-wettable composite material composed of copper particles and a polymeric binder. The terminal comprises a bond pad (24) overlying a passivation layer (20) on the die and a runner section (26) connecting the bond pad to a metal contact (16). The terminal is applied to the die, for example, as an ink by screen printing, after which a body of solder alloy is reflowed in contact with the bond pad to form the bump. A preferred material for the terminal is composed of silver-plated copper particles and a resol type phenolic binder.

Abstract: A solar cell has a photoelectric conversion semiconductor layer and an electrode made of a material containing a conductive base material and a resin binder electrically connected to the photoelectric conversion semiconductor layer, wherein the volume of voids in the electrode having a diameter of 0.1 .mu.m or greater is 0.04 ml/g or less.

Abstract: A semiconductor device includes a semiconductor element attached to a support member by a junction material that includes a parent phase of a low-melting-point junction material and fine particles of a high-melting-point junction material which are uniformly dispersed in the low-melting-point material. By heating the junction material to a temperature higher than the melting point of the low-melting-point junction material and lower than the melting point of the high-melting-point junction material, the low-melting-point junction material is brought to a molten state, making the entire junction material fluid. Thus, the size of the junction material need not be adjusted to that of the semiconductor element. Further, with this semiconductor device, the contact area between the low-melting-point junction material and the high-melting-point junction material is extremely large so that the requisite time for making the composition of the junction material uniform is shortened.

Abstract: A method for ball-bonding thin film structures. The bonding characteristics of a thin-film electrode structure are measured, before the actual bonding step, by pressing a ball (of a material similar to that of the bonding wire) against an electrode by a bonding capillary, and then measuring the resultant indentation of the electrode. The depth of this test indentation of the electrode has a good correlation with the bondability.

Abstract: The disclosure is directed to an improved circuit and method which utilizes a plurality of generally planar diamond substrate layers. Electronic circuit elements are mounted on each of the substrate layers, and the substrate layers are disposed in a stack. Heat exchange means can be coupled generally at the edges of the substrate layers. In a disclosed embodiment, a multiplicity of generally planar diamond substrate layers and a multiplicity of generally planar spacer boards are provided. Each of the substrate layers has mounted thereon a multiplicity of electronic elements and conductive means for coupling between electronic elements. In general, at least some of the electronic elements on the substrate layers comprise integrated circuit chips. The substrate layers and spacer boards are stacked in alternating fashion so that spacer boards are interleaved between adjacent substrate layers.

Abstract: A semiconductor structure with a p-type ZnSe layer has an improved ohmic contact consisting of a layer of Hg.sub.x Zn.sub.1-x Te.sub.a Se.sub.b Sc where x=0-1 with x being 0 at the surface of the ZnSe layer and increasing thereafter, a, b and c each =0-1 and a+b+c=1.

Abstract: High concentration polysilicon is grown on the silicon carbide so as to effect the connection through the polysilicon, thereby to obtain a better wiring construction in the connection between silicon carbide conductor basic plate and wiring.

Abstract: An electric circuit is provided on a semiconductor substrate with a supercoducting film. The surfaces being in contact with the superconducting film are made of heat-resistant non-oxide insulating materials so that the performance of the superconducting film is not degraded.

Abstract: Lead frames, in which at least one part of the surface of a metal member which is a part of the lead frame is provided with an anodic oxide film of copper or a copper alloy, and in which a member composed substantially of a resin film or a resin plate is connected to the lead frame through this anodic oxide film by gluing or pressing under heat exhibit good adhesion between the metal member and the resin film or plate. Similarly, lead frames constructed with at least two metal members, having a portion of the surface provided with an anodic oxide film of copper or a copper alloy, and in which these metal members are joined together through this anodic oxide film exhibit good adhesion between the metal members.