Abstract: A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals.

Abstract: A semiconductor device where an outside connection terminal of a semiconductor element and an electrode of a wiring board are connected to each other via a conductive adhesive, the conductive adhesive includes a first conductive adhesive; and a second conductive adhesive covering the first conductive adhesive; wherein the first conductive adhesive contains a conductive filler including silver (Ag); and the second conductive adhesive contains a conductive filler including a metal selected from a group consisting of tin (Sn), zinc (Zn), cobalt (Co), iron (Fe), palladium (Pd), and platinum (Pt).

Abstract: The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent to such transfers.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract: A conductive composition for coating a semiconductor wafer comprises conductive filler that has an average particle size of less than 2 microns and a maximum particle size of less than 10 microns, a first resin that has a softening point between 80-260° C., solvent, curing agent, and a second resin, wherein at room temperature the first resin is substantially soluble in the solvent.

Abstract: Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.

Abstract: Cylinders having Al as a major constituent are orderly arrayed in an (Si, Ge) matrix. In a nanostructure in the form of a mixture film having a plurality of cylinders having Al as a major constituent, and a matrix region surrounding the plurality of cylinders and having Si and/or Ge as a major constituent, the total amount of Si and Ge is in the range from 20 to 70 atomic % in the mixture film, the cylinders are orderly arrayed, the diameter of the cylinders is in the range from 1 to 30 nm, and the interval between the cylinders is 30 nm or less.

Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.

Abstract: An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

Abstract: Methods are provided to form wirings for tile-shaped elements, structures of wirings for tile-shaped elements, and electronic equipment, with which highly reliable electrical wirings having minute wiring patterns can be formed. In wiring forming method for a tile-shaped element, which is used, when a circuit device is formed by connecting a tile-shaped element having at least an electrode and a tile configuration to a final substrate having at least an electrode, to form an electrical wiring that electrically connects the electrode of the tile-shaped element to the electrode of the final substrate, liquid material including electro conductive material is applied to at least a part of a wiring region that is a region where the electrical wiring is formed on at least one of surfaces of the final substrate and the tile-shaped element.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

Abstract: In a pressure-welded semiconductor device where at least one semiconductor element is disposed inside a casing, a buffer conductive layer including conductive carbons is disposed at pressure-welded portions between first casing-side electrodes and element-side electrodes disposed on a first main surface and at pressure-welded portions between second casing-side electrodes and element-side electrodes disposed on a second main surface.

Abstract: Method for manufacturing an elastic connector, integrated with an electrode of at least either a chip-type LED or a printed circuit board on which a LED element is directly mounted and to which the LED is electrically connected. The LED-integrated connector can subsequently be mounted on another circuit board by being sandwiched and compressed between a lower surface of the chip-type LED or lower surface of the LED-mounted printed circuit board and the other circuit board to which the LED-integrated connector is being mounted, so as to provide an electric connection. The method providing a LED-integrated connector which is thin and cost-effective while able to provide a simple and secure conductivity between electrodes of the chip-type LED and other circuit board, to which the LED-integrated connector is subsequently mounted.

Abstract: A microelectronic network is fabricated on a fibrous skeleton by binding or complexing electronically functional substances to the nucleic acid skeleton. The skeleton comprises fibers with nucleotide chains. The assembly of the fibers into a network is based on interactions of nucleotide chain portions of different fibers.

Abstract: An active matrix substrate comprises a substrate, a plurality of adhesion parts provided on the substrate so as to have substantially the same height, and a plurality of active elements provided on the plurality of adhesion parts, respectively, each of the plurality of adhesion parts including a height control member and an adhesive.

Abstract: A composite material is provided, which has a low thermal expansivity, a high thermal conductivity, and a good plastic workability, which composite material may be applied to semiconductor devices and many other uses. The composite material is composed of metal and inorganic particles having a smaller coefficient of thermal expansion than the metal. It is characterized in that the inorganic particles are dispersed in such a way that 95% or more of them (in terms of their area in cross-section) form aggregates of complex configuration joined together. The composite material contains 20-80 vol % of copper oxide, with the remainder being copper. It has a coefficient of thermal expansion of 5×10?6 to 14×10?6/° C. and thermal conductivity of 30-325 W/m·K in the range of room temperature to 300° C. It is suitable for the radiator plate of semiconductor devices and the dielectric plate of electrostatic attractors.

Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.

Abstract: The present invention relates to electrically attaching a surface mount device to mounting structure via their respective contact pads using an attach material, such as solder or conductive epoxy, which includes a filler material. In general, the filler material is relatively solid and granular shaped, wherein the diameter of the filler material controls a mounting distance between the surface mount device and the mounting structure. The filler allows a desired distance to be maintained during initial placement of the surface mount device and any subsequent reheating.

Abstract: The present invention relates to electrically attaching a surface mount device to a mounting structure via their respective contact pads using an attach material, such as solder or conductive epoxy, which includes a filler material. In general, the filler material is relatively solid and granular shaped, wherein the diameter of the filler material controls a mounting distance between the surface mount device and the mounting structure. The filler allows a desired distance to be maintained during initial placement of the surface mount device and any subsequent reheating.

Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.

Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.

Abstract: A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract: A localised reduced lifetime region (1,25,41) is provided in a semiconductor device formed substantially of silicon. A predetermined concentration of carbon is provided in the region, and then the body is heated to incorporate a lifetime controlling impurity substantially within the carbon region. It is believed that the association between the impurity ions (M+) and the carbon atoms (C) on silicon lattice sites produces C-M+ complexes with significant capture cross-sections. The carbon may be provided by addition during epitaxial growth of silicon material, during bulk growth of the silicon, or by implantation and/or diffusion.

Abstract: Described is an electronic device having a compliant fibrous interface. The interface comprises a free fiber tip structure having flocked thermally conductive fibers embedded in an adhesive in substantially vertical orientation with portions of the fibers extending out of the adhesive and an encapsulant between the portions of the fibers that extend out of the adhesive and the fiber's free tips.

Abstract: A semiconductor package for power transistors of the LDMOS type has a metallic substrate with a die mounted directly thereon, lead frame insulators mounted thereon adjacent the die and a plurality of leads mounted on the insulators and electrically coupled to the die by bond wires. The substrate includes a body having opposite surfaces comprising pure copper layers, and with the body interior being at least partially comprised of a copper/diamond composite so as to act as a heat spreader and provide improved heat removal and low thermal expansion, as well as an electrical connection for the die. The body may be entirely comprised of a copper/diamond composite, or it may be comprised of a copper/tungsten composite having a copper/diamond composite insert therein. The copper/diamond composite is comprised of diamond particles within a copper matrix.

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

Abstract: A package to be mounted with semiconductor chips has a heat-radiating substrate having a thickness of smaller than 0.4 mm of a Cu—Mo composite as prepared by impregnating from 30 to 40% by mass of copper (Cu) melt into a green compact of molybdenum. The heat-radiating substrate is produced by preparing an Mo green compact through isostatic molding, mounting Cu on the Mo green compact, heating it to thereby impregnate copper into the Mo green compact to give a Cu—Mo composite, and rolling the Cu—Mo composite into a sheet substrate.

Abstract: A package to be mounted with semiconductor chips has a heat-radiating substrate having a thickness of smaller than 0.4 mm of a Cu—Mo composite as prepared by impregnating from 30 to 40% by mass of copper (Cu) melt into a green compact of molybdenum. The heat-radiating substrate is produced by preparing an Mo green compact through isostatic molding, mounting Cu on the Mo green compact, heating it to thereby impregnate copper into the Mo green compact to give a Cu—Mo composite, and rolling the Cu—Mo composite into a sheet substrate. In the isostatic molding process, at least two or more plates.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

Abstract: A thermal conducting material with higher thermal conductivity for a given low viscosity is shown. Carbon fibers are added to the thermal grease to promote thermal conductivity. The carbon fibers are also not highly electrically conductive, reducing the danger of short circuiting due to misapplication of the thermal grease. Due to the high thermal conductivity of the carbon fibers, a lower loading percentage is needed to obtain significant gains in thermal conductivity. The low loading percentages in turn permit lower thermal grease viscosity, which allows the thermal grease to be spread very thin during application.

Abstract: Provided are a composite material excellent in plastic workability, a method of producing the composite material, a heat-radiating board of a semiconductor equipment, and a semiconductor equipment to which this heat-radiating board is applied. This composite material comprises a metal and an inorganic compound formed to have a dendritic shape or a bar shape. In particular, this composite material is a copper composite material, which comprises 10 to 55 vol. % cuprous oxide (Cu2O) and the balance of copper (Cu) and incidental impurities and has a coefficient of thermal expansion in a temperature range from a room temperature to 300° C. of from 5×10−6 to 17×10−6/° C. and a thermal conductivity of 100 to 380 W/m·k. This composite material can be produced by a process comprising the steps of melting, casting and working and is applied to a heat-radiating board of a semiconductor article.

Abstract: There is provided a structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract: A method for selectively doping an organic semiconductor 1material in the region of a contact area 0.1formed between a contact and the organic semiconductor material disposed thereon includes introducing the dopant with the aid of nanoparticles, the nanoparticles being disposed in a manner adjoining the contact area and, as a result, only a very narrow region of the organic semiconductor material being doped. The field increase effected by the nanoparticles results in a further reduction of the contact resistance.

Abstract: A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract: A net-shape molded heat transfer component is provided which includes a thermally conductive core and a metallic coating for reflection of electromagnetic interference and radio frequency waves. The heat transfer component is formed by net-shape molding a core body from a thermally conductive composition, such as a polymer composition, and applying a metallic coating. The molded heat transfer part is freely convecting through the part, which makes it more efficient and has an optimal thermal configuration. Additionally, the part is shielded from electromagnetic interference and radio frequency waves, thus preventing the transfer of same into the circuitry housed by the part. In addition, the coating also seals the conductive polymer core against moisture infiltration, making the part well suited for telecommunications applications in potentially harsh environments.

Abstract: Methods of forming a graded layer is disclosed. The graded layer transitions from one material to another material. The properties of these materials are chosen to optimize the interfaces on each side of the graded layer. Specifically, an improved transistor gate stack barrier layer may be formed by disposing an appropriate graded layer between a gate layer and an interconnect layer. In fact, the graded layer may obviate the use of the interconnect layer, as the top of the graded layer may include a highly conductive material. An improved integrated circuit interconnect structure may also be formed by grading the material composition of an interconnect layer.

Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.

Abstract: In an electrode structure for a nitride III-V compound semiconductor device, a metallic nitride is used as an electrode material. A metallic material of the metallic nitride has a negative nitride formation free energy, and comprises at least one metal selected from a group consisting of IVa-group metals such as titanium and zirconium, Va-group metals such as vanadium, niobium, and tantalum, and VIa-group metals such as chromium, molybdenum, and tungsten.

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.