Abstract: A method of manufacturing a semiconductor structure includes loading the substrate from a first load lock chamber into a first processing chamber; disposing a conductive layer over the substrate in the first processing chamber; loading the substrate from the first processing chamber into the first load lock chamber; loading the substrate from the first load lock chamber into an enclosure filled with an inert gas and disposed between the first load lock chamber and a second load lock chamber; loading the substrate from the enclosure into the second load lock chamber; loading the substrate from the second load lock chamber into a second processing chamber; disposing a conductive member over the conductive layer in the second processing chamber; loading the substrate from the second processing chamber into the second load lock chamber; and loading the substrate from the second load lock chamber into a second load port.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.

Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.

Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

Abstract: Embodiments of the invention provide a semiconductor memory device. In some embodiments, the device includes a bottom electrode extending in a y-direction relative to top surface of a substrate and a top electrode extending in an x-direction relative to the top surface of the substrate. An active area is located at the cross-section between the bottom electrode and the top electrode and is located on vertical side walls extending in a z-direction of the semiconductor memory device with respect to the top surface of the substrate. An insulating layer is located in the active area in between the top electrode and the bottom electrode.

Abstract: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.

Abstract: A microelectronic device comprises a first conductive material comprising copper, a conductive plug comprising tungsten in electrical communication with the first conductive material, and manganese particles dispersed along an interface between the first conductive material and the conductive plug. Related electronic systems and related methods are also disclosed.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Abstract: In an embodiment, a device includes: a first and second integrated circuit die; and a hybrid redistribution structure including: a first photonic die; a second photonic die; a first dielectric layer laterally surrounding the first photonic die and the second photonic die, the first integrated circuit die and the second integrated circuit die being disposed adjacent a first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a major surface of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; a second dielectric layer disposed adjacent a second side of the first dielectric layer; and a waveguide disposed between the first dielectric layer and the second dielectric layer, the waveguide optically coupling the first and second photonic dies.

Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

Abstract: A TiN-based film includes TiON films having an oxygen content of 50% or above and TiN films which are laminated alternately on a substrate. In a TiN-based film forming method, a TiON film having an oxygen content of 50 at % or above and a TiN film are alternately formed on a substrate.

Abstract: A multi-wafer bonding structure and bonding method are disclosed. The multi-wafer bonding structure includes a first unit and a second unit, a metal layer of each wafer in the first unit electrically connected to an interconnection layer of the first unit, a first bonding layer in the first unit electrically connected to the interconnection layer of the first unit, a second bonding layer in the second unit electrically connected to a metal layer of the second unit, and the first bonding layer being in contact with the second bonding layer to achieve an electrical connection, thereby achieving the electrical connection among the interconnection layer of the first unit, the first bonding layer, the second bonding layer and the metal layer of each wafer.

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.

Abstract: A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally patterning a dielectric layer formed of SiC, SiN or SiC (N, H) and filled the openings in the patterned dielectric layer with a metal conductor. Optionally, the surfaces defining the openings of the dielectric layer are subjected to a nitridation process to form a nitride layer at the surface. Still further, the metallization structures can include a pure metal liner on the surfaces defining the openings of the dielectric layer.

Abstract: A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.

Abstract: Patterning methods for forming patterned device substrates are provided. Also provided are devices made using the methods. The methods utilize photoresist features have re-entrant profiles to form a secondary metal hard mask that can be used to pattern an underlying device substrate.

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include selectively modifying a top surface of an ultra-low k dielectric intermediate trench openings. The modified top surface of the ultra-low k dielectric includes an element such as nitrogen, carbon, silicon, or mixture thereof and has greater hydrophobicity than the ultra-low k dielectric underlying the top surface.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a gate electrode provided via a gate insulating film, an interlayer insulating film, and a barrier metal. At a temperature T (K) and where a guaranteed time of no negative bias temperature instability is L (h), a surface density tTi1 of Ti contained in the barrier metal satisfies: t Ti ? ? 1 > 1 1.58 × 10 5 ? { ln ? ( L 1.74 × 10 - 8 ) + Ea 473 × k - Ea kT } where, k is Boltzmann's constant, and Ea is activation energy satisfying 1.0 (eV)<Ea<1.5 (eV).

Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.

Abstract: A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.

Abstract: A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.

Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function including a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors. The through-vias include a first top level via and at least a second top level via lateral to the first top level via. A composite layer includes copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level. A plurality of Cu traces includes a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu metal trace on the composite layer contacting the second top level via.

Abstract: A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized.

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

Abstract: In fabricating a radio frequency (RF) switch, a phase-change material (PCM) and a heating element, underlying an active segment of the PCM and extending outward and transverse to the PCM, are provided. Lower portions of PCM contacts for connection to passive segments of the PCM are formed, wherein the passive segments extend outward and are transverse to the heating element. Upper portions of the PCM contacts are formed from a lower interconnect metal. Heating element contacts are formed cross-wise to the PCM contacts. The heating element contacts can comprise a top interconnect metal directly connecting with terminal segments of the heating element. The heating element contacts can comprise a top interconnect metal and intermediate metal segments for connecting with the terminal segments of the heating element.

Abstract: A method of forming a memory structure includes forming an opening on opposing sides of a plurality of memory pillars disposed on a substrate, the opening extends through a capping layer located above a first dielectric layer and a top portion of an oxide layer, the oxide layer is located between the first dielectric layer and an encapsulation layer on the substrate, the encapsulation layer surrounds the plurality of pillars, removing the oxide layer from areas of the memory structure located between the memory pillars, above the encapsulation layer and below the first dielectric layer, after removing the oxide layer a gap remains within the areas of the memory structure, and forming a second dielectric directly above the capping layer, wherein the second dielectric layer pinches off the opening to form airgaps.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a semiconductor substrate, an air gap region, a capping layer, and an isolating layer. The air gap region is disposed in the semiconductor substrate. The capping layer is disposed on the air gap region. The isolating layer is disposed on the semiconductor substrate and partially encircles the capping layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.

Abstract: A first metal interconnect structure embedded in a first dielectric material layer includes a first metallic nitride liner containing a first conductive metal nitride and a first metallic fill material portion. A second metal interconnect structure embedded in a second dielectric material layer overlies the first dielectric material layer. The second metal interconnect structure includes a pillar portion having a straight sidewall and a foot portion adjoined to a bottom periphery of the pillar portion and laterally protruding from the bottom periphery of the pillar portion. The foot portion can be formed by oxidizing a top surface of the first metallic fill material portion, removing the oxidized portion after formation of a cavity through the second dielectric material layer, and depositing a second metallic nitride liner in a volume from which the oxidized portion is removed.

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate structure over a substrate, forming a disposable spacer on a sidewall of the gate structure, and forming a source region and a drain region at opposite sides of the gate structure. The method also includes depositing an interlayer dielectric layer around the disposable spacer, and forming a first hard mask on the interlayer dielectric layer. The method further includes removing an upper portion of the gate structure, and removing the disposable spacer to form a trench between the gate structure and the interlayer dielectric layer. In addition, the method includes sealing the trench to form an air-gap spacer, and forming a second hard mask on the gate structure.

Abstract: It is an object of the present invention to easily perform an electric characteristic test for ensuring quality of a semiconductor device on an electrode pattern defect or deficiency. A method of manufacturing a semiconductor device according to the present invention performs, a first etching having a higher selected ratio with respect to a semiconductor material of a first semiconductor layer than a material of a first electrode film over the first electrode film, and removes a region in the first semiconductor layer below a pattern defective part or a deficiency part of the first electrode film at least partially to form an electrode film in the pattern defective part or the deficiency part of the first electrode film.

Abstract: A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a dielectric etch stop layer disposed on the substrate, a memory stack disposed on the dielectric etch stop layer and including a plurality of interleaved conductor layers and dielectric layers, and a plurality of memory strings each extending vertically through the memory stack and including a selective epitaxial growth (SEG) plug in a bottom portion of the memory string. The SEG plug is disposed on the substrate.

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

Abstract: A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: A semiconductor device including a transistor having high reliability is provided. The semiconductor device includes a transistor. The transistor includes first and second gate electrodes, a source electrode, a drain electrode, first to third oxides, first and second barrier films, and first and second gate insulators. The first barrier film is located over the source electrode, the second barrier film is located over the drain electrode, and the first and second barrier films each have a function of blocking oxygen and impurities such as hydrogen.

Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.