Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Abstract: A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.

Abstract: After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.

Abstract: Interconnect structures and processes of fabricating the interconnect structures generally includes a recessed metal conductor and a discontinuous capping layer thereon. The discontinuous “capped” metal interconnect structure provides improved performance and reliability for the semiconductor industry.

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a wiring layer having a metal line, and forming a patterned disposable material layer over the wiring layer and having an opening aligned with the metal line. The method also includes depositing a first dielectric film in the opening and in contact with the metal line, and removing the patterned disposable material layer to leave the first dielectric film. The method further includes depositing a second dielectric film over the first dielectric film, and etching the second dielectric film to form a trench above the first dielectric film. In addition, the method includes removing a portion of the first dielectric film to form a via hole under the trench, and depositing a conductive material in the trench and the via hole.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.

Abstract: A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line.

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

Abstract: A semiconductor device may include a semiconductor substrate, an insulator film provided directly or indirectly on the semiconductor substrate, a main electrode for power provided on the insulator film, a pad for signal provided on the insulator film. The insulator film may include a cell region where the main electrode is provided and a pad region where the pad is provided. The cell region and the pad region of the insulator film each may include a contact hole. A height position of the contact hole located within the pad region may be higher than a height position of the contact hole located within the cell region. A width of the contact hole located within the pad region may be greater than a width of the contact hole located within the cell region.

Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

Abstract: Transition metal precursors are disclosed herein along with methods of using these precursors to deposit metal thin films. Advantageous properties of these precursors and methods are also disclosed, as well as superior films that can be achieved with the precursors and methods.

Abstract: A semiconductor apparatus includes a conductive member penetrating through a first semiconductor layer, a first insulator layer, and a third insulator layer, and connecting a first conductor layer with a second conductor layer. The conductive member has a first region containing copper, and a second region containing a material different from the copper is located at least between a first region and the first semiconductor layer, between the first region and the first insulator layer, and between the first region and the third insulator layer. A diffusion coefficient of the copper to a material is lower than a diffusion coefficient of the copper to the first semiconductor layer and a diffusion coefficient of the copper to the first insulator layer.

Abstract: A semiconductor device comprising a first circuit component and a second circuit component, the first circuit component having a first wiring structure formed by stacking one or more wiring layers and one or more insulating layers on a first semiconductor substrate, the second circuit component having a second wiring structure formed by stacking one or more wiring layers and one or more insulating layers on a second semiconductor substrate, the first and second wiring structures being bonded to each other, their bonding planes being composed of oxygen atoms and carbon atoms and/or nitrogen atoms bonded to silicon atoms, and, numbers of their atoms satisfying a predetermined equation.

Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate having a metal pattern, and forming an etch stop layer over the substrate. The etch stop layer includes a first material. The method also includes forming a diffused area in the etch stop layer by diffusing a second material from the metal pattern to the etch stop layer, and forming an insulative layer over the etch stop layer. The diffused area includes a lower etch rate to a first etchant than the insulative layer. A semiconductor device is also provided.

Abstract: A method of manufacturing a semiconductor structure includes loading the substrate from a first load lock chamber into a first processing chamber; disposing a conductive layer over the substrate in the first processing chamber; loading the substrate from the first processing chamber into the first load lock chamber; loading the substrate from the first load lock chamber into an enclosure filled with an inert gas and disposed between the first load lock chamber and a second load lock chamber; loading the substrate from the enclosure into the second load lock chamber; loading the substrate from the second load lock chamber into a second processing chamber; disposing a conductive member over the conductive layer in the second processing chamber; loading the substrate from the second processing chamber into the second load lock chamber; and loading the substrate from the second load lock chamber into a second load port.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.

Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.

Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

Abstract: Embodiments of the invention provide a semiconductor memory device. In some embodiments, the device includes a bottom electrode extending in a y-direction relative to top surface of a substrate and a top electrode extending in an x-direction relative to the top surface of the substrate. An active area is located at the cross-section between the bottom electrode and the top electrode and is located on vertical side walls extending in a z-direction of the semiconductor memory device with respect to the top surface of the substrate. An insulating layer is located in the active area in between the top electrode and the bottom electrode.

Abstract: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.

Abstract: A microelectronic device comprises a first conductive material comprising copper, a conductive plug comprising tungsten in electrical communication with the first conductive material, and manganese particles dispersed along an interface between the first conductive material and the conductive plug. Related electronic systems and related methods are also disclosed.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.

Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

Abstract: In an embodiment, a device includes: a first and second integrated circuit die; and a hybrid redistribution structure including: a first photonic die; a second photonic die; a first dielectric layer laterally surrounding the first photonic die and the second photonic die, the first integrated circuit die and the second integrated circuit die being disposed adjacent a first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a major surface of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; a second dielectric layer disposed adjacent a second side of the first dielectric layer; and a waveguide disposed between the first dielectric layer and the second dielectric layer, the waveguide optically coupling the first and second photonic dies.

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

Abstract: A TiN-based film includes TiON films having an oxygen content of 50% or above and TiN films which are laminated alternately on a substrate. In a TiN-based film forming method, a TiON film having an oxygen content of 50 at % or above and a TiN film are alternately formed on a substrate.

Abstract: A multi-wafer bonding structure and bonding method are disclosed. The multi-wafer bonding structure includes a first unit and a second unit, a metal layer of each wafer in the first unit electrically connected to an interconnection layer of the first unit, a first bonding layer in the first unit electrically connected to the interconnection layer of the first unit, a second bonding layer in the second unit electrically connected to a metal layer of the second unit, and the first bonding layer being in contact with the second bonding layer to achieve an electrical connection, thereby achieving the electrical connection among the interconnection layer of the first unit, the first bonding layer, the second bonding layer and the metal layer of each wafer.

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.

Abstract: A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally patterning a dielectric layer formed of SiC, SiN or SiC (N, H) and filled the openings in the patterned dielectric layer with a metal conductor. Optionally, the surfaces defining the openings of the dielectric layer are subjected to a nitridation process to form a nitride layer at the surface. Still further, the metallization structures can include a pure metal liner on the surfaces defining the openings of the dielectric layer.

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

Abstract: Patterning methods for forming patterned device substrates are provided. Also provided are devices made using the methods. The methods utilize photoresist features have re-entrant profiles to form a secondary metal hard mask that can be used to pattern an underlying device substrate.

Abstract: A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.

Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include selectively modifying a top surface of an ultra-low k dielectric intermediate trench openings. The modified top surface of the ultra-low k dielectric includes an element such as nitrogen, carbon, silicon, or mixture thereof and has greater hydrophobicity than the ultra-low k dielectric underlying the top surface.

Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a gate electrode provided via a gate insulating film, an interlayer insulating film, and a barrier metal. At a temperature T (K) and where a guaranteed time of no negative bias temperature instability is L (h), a surface density tTi1 of Ti contained in the barrier metal satisfies: t Ti ? ? 1 > 1 1.58 × 10 5 ? { ln ? ( L 1.74 × 10 - 8 ) + Ea 473 × k - Ea kT } where, k is Boltzmann's constant, and Ea is activation energy satisfying 1.0 (eV)<Ea<1.5 (eV).

Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.

Abstract: A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.

Abstract: A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.

Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function including a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors. The through-vias include a first top level via and at least a second top level via lateral to the first top level via. A composite layer includes copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level. A plurality of Cu traces includes a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu metal trace on the composite layer contacting the second top level via.

Abstract: A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized.

Abstract: A method of forming a memory structure includes forming an opening on opposing sides of a plurality of memory pillars disposed on a substrate, the opening extends through a capping layer located above a first dielectric layer and a top portion of an oxide layer, the oxide layer is located between the first dielectric layer and an encapsulation layer on the substrate, the encapsulation layer surrounds the plurality of pillars, removing the oxide layer from areas of the memory structure located between the memory pillars, above the encapsulation layer and below the first dielectric layer, after removing the oxide layer a gap remains within the areas of the memory structure, and forming a second dielectric directly above the capping layer, wherein the second dielectric layer pinches off the opening to form airgaps.