Abstract: A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

Abstract: The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching.

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

Abstract: An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.

Abstract: According to the invention a method for filling one or more gaps created during manufacturing of a feature on a substrate is provided by providing the substrate in a reaction chamber and providing a deposition method. The deposition method comprises; providing an anisotropic plasma to bombard a bottom area of a surface of the one or more gaps with ions thereby creating adsorption sites at the bottom area; introducing a first reactant to the substrate; and, allowing the first reactant to react with the adsorption sites at the bottom area of the surface to fill the one or more gaps from the bottom area upwards.

Abstract: A semiconductor device having a silicon carbide (SiC) substrate, a SiC layer formed on a front surface of the SiC substrate, a first region selectively formed in the SiC layer at a surface thereof, a source region and a contact region formed in the first region, a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region, a gate electrode disposed on the gate insulating film above the portion of the first region, an interlayer insulating film covering the gate electrode, a source electrode electrically connected to the source region and the contact region, a drain electrode formed on a back surface of the SiC substrate, a first barrier film formed on, and covering, the interlayer insulating film, and a metal electrode formed on the source electrode and the first barrier film.

Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

Abstract: Aspects of the disclosure are directed to apparatuses and methods involving an electrical connector and methods thereof. As may be consistent with one or more embodiments, an interposer includes respective barrier layers having barrier material that is coplanar with, and laterally surrounds, traces having connected via pads. Vias connect pads of stacked pairs of the traces in different ones of the barrier layers. The traces vary in width along their respective lengths. The barrier material is offset from each trace by a continuous gap having a length extending around the trace, with the gaps extending around each stacked pair being offset from one another along the majority of their respective lengths.

Abstract: A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.

Abstract: Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.

Abstract: Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Cl2 plasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Cl2 plasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.

Abstract: The present disclosure relates to semiconductor components. The teachings thereof may be embodied in a lead frame for a semiconductor component including: a frame having a recess; an electrically conductive connecting element for establishing an electrical connection to the semiconductor component arranged in the recess; and an insulating element arranged in the recess and mechanically connecting the connecting element to the frame and electrically insulating it from the frame.

Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

Abstract: A chemical vapor deposition method comprises flowing a carrier liquid through a reactor. A fluid comprising one or more reactants is introduced into the carrier liquid. The fluid is at a first temperature and first pressure and is sufficiently immiscible in the carrier liquid so as to form a plurality of microreactors suspended in the carrier liquid. Each of the microreactors comprise a discrete volume of the fluid and have a surface boundary defined by an interface of the fluid with the carrier liquid. The fluid is heated and optionally pressurized to a second temperature and second pressure at which a chemical vapor deposition reaction occurs within the microreactors to form a plurality of chemical vapor deposition products. The plurality of chemical vapor deposition products are separated from the carrier liquid. A system for carrying out the method of the present disclosure is also taught.

Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.

Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.

Abstract: Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.

Abstract: The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In some embodiments, a dielectric layer is formed over a semiconductor substrate having an opening arranged within the dielectric layer. A metal seed layer is formed on the surfaces of the opening using a chemical vapor deposition (CVD) process. Then a metal layer is plated onto the metal seed layer to fill the opening. Forming the metal seed layer using a CVD process provides the seed layer with a good uniformity, which allows for high aspect ratio openings in the dielectric layer to be filled without voids or pinch off.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: A semiconductor device includes: a conductive structure, a conductive bump extending into the conductive structure and contacting the conductive structure along a first surface, the conductive bump configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface than the second surface.

Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane, an insulating layer provided in the first plane side of the semiconductor layer, a metal layer provided on or above the insulating layer, and a through electrode penetrating through the semiconductor layer and in contact with the metal layer. When a width of the through electrode in the first plane is a first width, a width of the through electrode in an intermediate plane between the first plane and the second plane is a second width, and a width of the metal layer is a third width, a first difference between the second width and the first width is larger than a second difference between the third width and the first width.

Abstract: A use of an amine-containing silane for forming a transition metal nitride is provided. In this use, the amine of the amine-containing silane is the source of at least some, preferably most and most preferably all of the nitrogen present in the transition metal nitride.

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.

Abstract: The present disclosure provides a contact element of a semiconductor device structure, wherein an opening is formed in an insulating material layer, the insulating material layer being provided over a semiconductor substrate. Within a lower portion of the opening, a contact liner portion is formed, the contact liner portion covering a bottom of the opening and partially covering a lower sidewall portion of the lower portion of the opening such that an upper sidewall portion at an upper portion of the opening is exposed to further processing. An insulating liner portion is formed within the opening, the insulating liner portion covering the exposed upper sidewall portion. Furthermore, a contact liner is formed within the opening, the contact liner covering the contact liner portion in the insulating liner portion, and the opening is filled with a conductive material.

Abstract: Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the dielectric layer at one or more sidewalls of the dual-damascene opening. A first conductor layer is formed in a portion of the dual-damascene opening. The first liner is removed from the one or more sidewalls of the dual-damascene opening vertically between the first conductor layer and a top surface of the dielectric layer. After the first liner is removed, a second liner is formed on the dielectric layer at the one or more sidewalls of the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. A second conductor layer is formed in the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. The first and second liner materials differ in composition.

Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Abstract: A method for fabricating an advanced metal insulator metal capacitor structure includes providing a pattern in a dielectric layer. The pattern includes a set of features in the dielectric layer. A first metal layer is deposited in the set of features in the dielectric layer. A phase change material layer is deposited over the metal layer in the set of features in the dielectric layer. The phase change material is an insulator in a deposited state. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A second metal layer is deposited on the top surface layer of the phase change layer.

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

Abstract: The resin composition for sealing semiconductor according to the present invention is characterized by containing a maleimide-based compound represented by the following general formula (1), at least one of the benzoxazine-based compounds represented by the following general formula (2-1) and the following general formula (2-2), a curing catalyst, and an inorganic filler. In the general formulae (1), (2-1) and (2-2), each of X2, X3 and X4 independently represents an alkylene group having 1 to 10 carbon atoms, a group represented by the following general formula (3), a group represented by the formula “—SO2—” or “—CO—”, an oxygen atom or a single bond.

Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract: A system includes a deposition chamber comprising first, second, and third stations, a delivery system providing a substrate to the deposition chamber, a processing system processing the substrate, a controller controlling the delivery system and the processing system, and an etch chamber. The delivery system provides the substrate to the first station, where the processing system performs a nucleation process on the substrate to form a metal nucleation layer, the substrate is then provided by the delivery system to the second station, where the processing system performs a first deposition process at a first temperature to form a first metal layer, the delivery system provides the substrate including the first metal layer metal to the etch chamber, where the first metal layer is etched back using a first gas. The substrate is provided back to the first station, wherein it undergoes a cleaning process using a second gas.