Abstract: A contact hole in a diffusion region is narrowed by a buffer layer formed at about the middle of an interlayer insulating film in its thickness direction. This buffer layer serves as effective alignment tolerances to the diffusion region and a contact electrode at the time of forming the contact hole. The structure having a wiring conductor filled in the contact hole and having the contact electrode formed on this wiring conductor can assure a highly reliable contact. Forming a buffer layer as a sidewall on this contact electrode and a first wiring layer formed on the same layer can assure an effective alignment tolerance to the first wiring layer at the time of forming a VIA hole. Filling a wiring conductor in the VIA hole can eliminate the need for any contact tolerance for a second wiring layer to be formed on this wiring conductor. Accordingly, the individual contact tolerances can be assured by self-alignment.

Abstract: A semiconductor device comprises an element separating insulation film formed on a main surface of a silicon substrate, an insulation film formed to project from the edge portion of the element separating insulation film onto a part of a silicon region of the substrate and having a thickness smaller than the thickness of the element separating insulation film, a first metal silicide film formed to cover the element separating insulation film and the thin insulation film in the vicinity of the edge portion of the element separating insulation film, a second metal silicide film formed on the silicon region in the vicinity of the thin insulation film, and a third metal silicide film formed in the vicinity of the tip portion of the thin insulation film for connecting the first and and second metal silicide films.

Abstract: A lightly doped drain, field effect transistor with an inverted "T"-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.

Abstract: A semiconductor device, wherein an electrode wiring, which is in contact with semiconductor layers of mutually different conductive types and serves to connect at least the layers of mutually different conductive types, comprises a first portion principally composed of the same component as the principal component of the semiconductor layers, and a second portion consisting of a metal.

Abstract: A semiconductor integrated circuit device includes at least two bipolar transistors having a first type structure in which a wiring layer is formed in direct contact with the emitter region thereof and at least one bipolar transistor having a second type structure in which a polysilicon layer is formed on the emitter region thereof. The transistor having the first type structure is used in a circuit which is required to have a high matching degree. The transistor having the second type structure is used in a circuit which is required to have a high performance, low power consumption and high integration density rather than a high matching degree.

Abstract: A method of depositing tungsten on a substrate utilizing silicon reduction wherein the process is non-limiting as to the thickness of silicon that may be converted to tungsten. A silicon substrate is provided with at least one area of silicon material having a predetermined thickness and the substrate is exposed to a tungsten hexafluoride gas flow in a chemical vapor deposition environment. By adjusting the WF.sub.6 gas flow rate and the CVD process parameters, such as pressure, temperature and deposition time, the thickness of silicon converted to tungsten can be adjusted in order to convert the entire thickness. A novel structure having a midgap tungsten gate and tungsten source and drain metallized layers is also disclosed.

Abstract: A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure.

Abstract: In a semiconductor integrated circuit comprising an array of memory cells of floating gate type MOS transistors, an insulating film is formed on the top surface and the side walls of the gate electrode portion. The insulating films on the side walls serve as an offset region of a channel contacting with the drain region. The side end portions of the drain region, contacting the channel region has a lower impurity concentration than the remaining portion of the drain region. A conductive layer covers the surface of the drain region and at least the insulating films on the side walls of the gate electrode, which upstands above both ends of the drain region. A metal interconnection layer is deposited on the conductive layer.

Abstract: There is disclosed a semiconductor device in which the resistance pattern on the semiconductor substrate is formed by the resistance film and the wiring pattern connected to the resistance pattern is formed by the resistance film and the conductive film deposited and formed thereon. Furthermore, a method of manufacturing such a semiconductor device by a photolithographic process is disclosed. In accordance with this method, after the resistance film is formed, a conductive film is formed thereon and the conductive film corresponding to the portion serving as a resistance element is removed. A convex portion may be provided on the insulating substrate, thus to form wiring only on this region or to form wiring only around this region.

Abstract: A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.

Abstract: Disclosed is a stacked capacitor type semiconductor memory device having an increased capacitance of a capacitor. An upward projection member projecting upward is provided on an interlayer insulation film. A storage node is provided on the interlayer insulation film to cover the upward projection member. A capacitor insulation film is provided to cover the storage node. A cell plate electrode is provided to cover the capacitor insulation film. With such a semiconductor memory device, the storage node is formed to cover the upward projection member provided on the interlayer insulation film, thereby to increase a surface area of the storage node.

Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapsulated by a thin film of titanium nitride.