Abstract: A method and structure for manufacturing a self-aligned contact, for connecting conductive lines to active regions in a silicon substrate, is described. There is a first insulating layer over the silicon substrate, with openings over the active regions. A barrier metal layer is formed over the active regions, along surfaces of the openings, and over a portion of the horizontal surfaces of the first insulating layer in the region adjacent to the openings. There is a refractory metal layer over the barrier metal layer. Conductive lines are self-aligned over the barrier metal layer and over the refractory metal layer. Sidewall spacers are formed adjacent to the conductive lines and over those regions of the refractory metal layer not covered by the conductive lines.

Abstract: A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.

Abstract: A semiconductor bond pad prevents cratering by including an etch stop layer which is formed between the field oxide layer and the first dielectric layer to prevent erosion of the field oxide while allowing etching and removal of the first dielectric layer to prevent cratering.

Abstract: In a bipolar device, selective epitaxial silicon provides an improved intrinsic-extrinsic base link. A trench physically separates an intrinsic and extrinsic base portion. The trench includes sidewalls having a thin oxide layer formed thereon. The bottom of the trench is exposed during processing. A shallow link between the intrinsic-extrinsic regions of a bipolar transistor base is formed by depositing a heavily boron doped layer of silicon on the exposed portion of the trench. During subsequent processing, including rapid thermal anneal, there is some boron out-diffusion which forms a shallow diffused intrinsic-extrinsic base link.

Abstract: An integrated circuit is fabricated on a semiconductor substrate and comprises an n channel type field effect transistor, a p channel type field effect transistor and an interconnection coupled between the drain regions of the two field effect transistors, and each of the gate electrodes and the interconnection is provided with a polycrystalline silicon and a refractory metal silicide deposited over the polycrystalline silicon, wherein side spacers are eliminated from the gate electrodes and the interconnection, because no short circuiting takes place between the gate electrodes and the source and drain regions by virtue of the deposition of the refractory metal silicide.

Abstract: A conductive structure for an integrated circuit. An amorphous silicon layer overlies a silicide layer atop a conductive polycrystalline silicon structure. An insulating layer overlies the overall structure formed by the three layers. An opening through the insulating layer also extends through the amorphous silicon layer to expose a portion of the silicide layer. An upper interconnect layer extends through the insulating layer and the amorphous silicon layer to make contact with the silicide layer.

Abstract: A contact structure of a semiconductor device comprises a lamination of at least first insulating film, first conductive film and second insulating film formed in that order a through hole formed to penetrate through at least the first insulating film and the first conductive film so that a cross-section of the first conductive film is exposed to the through-hole and a second conductive film formed on an inner surface of the through-hole so that the second conductive film electrically contacts with the cross-section of the first conductive film.

Abstract: An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

Abstract: A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. The MOSFET is typically created by a five-mask process. A defreckle etch is performed subsequent to metal deposition and patterning to define the two peripheral polycrystalline segments.

Abstract: An integrated circuit has an interconnection pattern which is recessed in the insulating layer, for example, an oxide layer. A groove is etched in the insulating layer corresponding to the metal pattern by means of a mask which is the inverted image of the interconnection pattern during manufacture. Etching is continued until contact windows are fully opened. To prevent the oxide between the contact windows also being removed, an etching stopper layer is provided in the oxide layer. A layer already present in the process may be used for this etching stopper layer, for example, a polycrystalline silicon layer, so that extra process steps are made redundant.

Abstract: This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is (111) is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of <110> axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.

Abstract: A contact structure for connecting a semiconductor device to a wiring electrode includes a semiconductor layer forming a part of the semiconductor device. A first contact layer of reduced resistivity covers a surface of the semiconductor layer. An insulating structure is provided on the first contact layer so as to bury the first contact layer underneath. A penetrating hole is opened through the insulating structure so as to expose a part of the first contact layer. A second contact layer of reduced resistivity is provided on the part of the first contact layer exposed by the penetrating hole. The second contact layer extends from a bottom of the penetrating hole along its side wall. A conductor layer forms the wiring electrode provided on the second contact layer.

Abstract: The MOS field-effect transistor has a semiconductor substrate of a first conductivity type, a pair of first polycrystalline silicon layers of a second conductivity type different from the first conductivity type which are formed on the semiconductor substrate and separated from each other by a small gap, a pair of diffusion layers of the second conductivity type formed in those regions of the semiconductor substrate which are in contact with the pair of first polycrystalline silicon layers, respectively, a gate insulating film formed to cover the pair of first polycrystalline silicon layers of the second conductivity type and a part of the semiconductor substrate exposed to an outside at the small gap, and a gate electrode formed on the gate insulating film. The nonvolatile semiconductor memory device is arranged by using the MOS field-effect transistor mentioned above.

Abstract: A contact between a heavily-doped region in the substrate and metal is made via a hole in a thick oxide layer and a polysilicon layer. The polysilicon layer is first etched to form a hole for establishing a mask for the eventual contact hole. Prior to forming the contact hole, a sidewall spacer of polysilicon is formed in the hole in the polysilicon layer. A thin oxide layer over the polysilicon layer is used for convenient end point detection during the formation of the polysilicon sidewall spacers. The sidewall spacer reduces the bore dimension of the hole in the polysilicon used for the mask for forming the contact hole. A hole is then etched in the thick oxide which is sloped and which has a bore dimension determined by the hole in the polysilicon which is reduced due to the sidewall spacer. The heavily-doped region, the contact hole, and the remaining polysilicon are coated with a barrier. The contact hole is then filled with a conductive material which also coats the barrier.

Abstract: According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via.

Abstract: This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropically etching the bonding layer forming chambers in the bonding layer; stacking the first and second wafers with the metal against the second wafer's bonding layer; forming a chemical bond between the metal layer and the bonding layer (e.g. between the titanium 20 and the poly 38) in a vacuum chamber, thereby creating micro-vacuum chambers (42) between the wafers; selectively etching the second wafer to form a thin semiconductor layer ( e.g. epi layer 30). This is also a semiconductor-on-insulator wafer. The wafer comprises: a substrate (e.g. semiconductor substrate 20); a layer of metal (e.g. titanium 24) and semiconductor ( e.g. silicide 40) over the substrate; a bonding layer (e.g.

Abstract: A semiconductor device is provided which includes a conductive layer, an insulating film formed on the surface of the conductive layer, and a conductive metal interconnection layer formed on the insulating film and electrically connected to the conductive layer through a contact hole formed in a predetermined position of the insulating film. The conductive metal interconnection and the surface of the conductive layer are directly joined together and a silicon layer including a single crystal or polycrystalline silicon having a grain size of at least about 10 .mu.m is interposed between the conductive metal interconnection layer and the insulating film. The conductive metal interconnection layer becomes a single crystal or a polycrystal having a grain size of about 10 .mu.m or above under the influence of the crystalline properties of the underlying crystal of the silicon layer.

Abstract: A grid-like arrangement of membranes of doped polysilicon are mounted on a substrate but are electrically insulated therefrom each membrane extends over a cavity and is joined to the substrate at at least two supporting locations so that they cavity lies between the membrane and the substrate. Changes in an electrical quantity existing between the membranes and the substrate are measured as forces exerted on the grid-like arrangement of sensor elements so that the ridges in the skin on a finger tip may be sensed for detecting a fingerprint.

Abstract: A semiconducting diamond electroluminescence element comprises an electrically conductive substrate, a semiconducting diamond layer formed on the substrate, an insulating diamond layer formed on the semiconducting diamond layer, a front electrode formed on the insulating diamond layer, and a back electrode formed on the conductive substrate in ohmic contact with the same. The color of light to be emitted by the semiconducting diamond electroluminescence element can readily be determined by changing the impurity content in the semiconducting diamond layer. The luminescence intensity of the semiconducting diamond electroluminescence element can readily be changed by changing the voltage applied across the front and back electrodes without entailing dielectric breakdown.

Abstract: The method for fabrication of semiconductor contacts resulting in rounded contact corners providing for increased step coverage includes depositing a glass layer over a substrate and heating the glass layer to reflow. The glass layer is patterned and etched to form a contact opening. A barrier layer is deposited, annealed, and selectively wet etched leaving the barrier layer only in the bottom of the contact opening. The glass layer is reflowed again to form rounded contact corners.

Abstract: A MIS semiconductor device comprises, on a silicon wafer, a gate oxide layer, a polysilicon gate electrode comprising a gate layer of polysilicon of grain size of not less than 0.3 .mu.m doped with boron in a doping amount of not less than 3.times.10.sup.19 atoms/cm.sup.3, and a gate insulation layer, provided with metal electrodes.

Abstract: A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.

Abstract: A Bi-MOS semiconductor device of the type having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor aubstrate and a method of producing the same. The device includes a plurality of element isolation regions each thereof being composed of a first semiconductor region formed in the semiconductor substrate and having the same type of conductivity as the semiconductor substrate, and a thick insulation layer formed on the first semiconductor region, and at least one of an emitter electrode and a collector electrode formed in the bipolar device, gate electrodes formed in the MBS devices, a low-resistivity polycrystalline layer formed by a buried contact from one of the MOS devices and a high-resistivity portion formed by a high resistivity polycrystalline silicon layer connected to the low-resistivty polycrystalline silicon layer are formed from a polycrystalline silicon layer formed by the same layer formation.

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region formed above a more heavily-doped n+ layer. Directly above the collector is a p-type base which has an extrinsic region disposed laterally about an intrinsic region. An n+ emitter is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract: An improved density semiconductor device having a novel buried interconnect is described. The buried interconnect electrically connects electrical device regions on a semiconductor substrate such that other structures may directly overlie the buried interconnect but not be electrically connected to the electrically conductive portions of the interconnect. The interconnect is composed of a buried conductor and conductive segments. The conductive segments are electrically joined to the buried conductor so as to form an electrical pathway. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. A nonconductive portion of selective poly-epi silicon is then formed over the buried conductor by oxidizing at least some of the selective poly-epi silicon layer.

Abstract: In a turn off type semiconductor device, an n-type emitter layer is divided into a plurality of elements by trenches. A silicide layer of a high melting point metal is provided on a p-type layer adjacent to the individual elements of the n-type emitter layer on a bottom of each of the trenches. A gate electrode is provided on the associated silicide layer so as to surround the plurality of elements of the n-type emitter layer obtained by the division of the emitter layer. An insulator is filled in each of the trenches dividing the n-type emitter layer surrounded by the gate electrode. A cathode electrode is provided on both the insulators and the n-type emitter layer.

Abstract: Semiconductor devices and methods for producing semiconductor devices to be produced by conducting a combination of a step for producing a gate elctrode of a first conductor layer which is piled on a gate insulator, a step for producing a drain region which is connected with an n.sup.+ -region located under the gate electrode by employing the gate electrode as a part of the mask, and a step for piling, on or over the gate electrode, a second conductor layer connected with the n.sup.+ -region through a contact hole produced in the gate electrode.

Abstract: An MIS device which includes a source diffusion layer and a drain diffusion layer under the surface of a semiconductor substrate, and a plurality of gate insulation films on the surface of the semiconductor substrate. Further, a plurality of gate electrodes are formed on the plurality of gate insulation films in series with one another between the source diffusion layer and the drain diffusion layer. Moreover, inter-gate-electrode diffusion layers are formed under the surfaces of regions of the semiconductor substrate among the plurality of the gate electrodes. Insulating side walls are provided on both sides of each of the gate electrodes.

Abstract: In accordance with the present invention, a silicon device fabricated on a (100) silicon substrate is provided with a (111) slant surface and an electrical contact comprising epitaxial low Schottky barrier silicide is formed on the (111) surface. For example, low resistance rare earth silicide contacts on V-groove surfaces are provided for the source and drain contacts of a field effect transistor. The resulting high quality contact permits downward scaling of the source and drain junction depths. As another example, rare earth silicide Schottky contacts are epitaxially grown on V-groove surfaces to provide low voltage rectifiers having both low power dissipation under forward bias and low reverse-bias leakage current.

Abstract: A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Abstract: In a laser-broken fuse used in a memory redundancy technique, an aluminum wiring layer is formed on an interlevel insulating film. A portion of the wiring layer is selected to be broken to shut off conduction of the layer. A polysilicon-made heat member is provided in the interlevel insulating film at the place which is underneath the selected portion. The heat member is located on a field insulating film. This heat member generates heat by absorbing energy from a laser beam, and thermal-explodes in a sealed atmosphere so as to break the selected portion.

Abstract: There is disclosed a semiconductor device which has a first insulating film formed on a surface of a semiconductor substrate, a polysilicon layer formed on the first insulating film, a second insulating film formed on the polysilicon layer, and a metallic interconnection layer formed on the second insulating film. The polysilicon layer is formed thicker at a connection portion than other portions and is connected to the metallic interconnection layer via a hole formed in the second insulating layer. The film thickness of the polysilicon layer is large at the contact forming portion so that it is possible to prevent the contact hole from being formed passing through the polysilicon layer even if the lower polysilicon layer is excessively etched during the contact hole forming process.

Abstract: A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed.

Abstract: A local interconnect structure for an integrated circuit is formed from a patterned refractory metal silicide. The local interconnect has an overlying oxide layer, which prevents part of the amorphous silicon used to form the interconnect from becoming silicided. This results in a local interconnect layer which has thinner silicide portions than silicide regions formed over adjacent source/drain regions and gate electrodes.

Abstract: A is a heat-resisting ohmic electrode on diamond film, including: a p-type semiconducting diamond film; a boron-doped diamond layer provided on the semiconducting diamond film; and an electrode element made of p-type Si selectively formed on the boron-doped diamond layer; wherein the boron concentration in the boron-doped diamond layer is from 1.0.times.10.sup.19 to 1.8.times.10.sup.23 cm.sup.-3, and at least one impurity selected from the group consisting of B, Al and Ga is doped in the electrode element with a concentration from 1.0.times.10.sup.20 to 5.0.times.10.sup.22 cm.sup.-3. The ohmic electrode on diamond film is applicable for electronic devices operative at high temperature.

Abstract: A contact structure for interconnection in semiconductor devices provides electrical contact between an impurity-diffused region formed in a silicon substrate and a polycrystalline silicon layer through a contact hole. The contact structure for interconnection comprises the silicon substrate, the impurity-diffused region, an insulating oxide film, the interconnection layer formed of a polycrystalline silicon layer containing impurities. The impurity-diffused region is formed in a main surface of the silicon substrate as a source/drain region of an MOS transistor. The insulating oxide film has a contact hole formed therethrough to reach a surface of this impurity-diffused region. A sidewall layer of polycrystalline silicon is formed on the bottom peripheral edge of the contact hole. The interconnection layer is formed on the sidewall layer of polycrystalline silicon and over the insulating oxide film to get contact with the surface of the impurity-diffused region exposed by the contact hole.

Abstract: An electrode assembly for a semiconductor device includes a contact layer formed on a semiconductor substrate and consisting mainly of a rare-earth metal or metals, or a silicide thereof, or a mixture thereof, and a diffusion barrier layer formed on the contact layer and consisting mainly of iron or an iron alloy. The assembly is bonded to a mount by a solder layer formed on the diffusion barrier layer and consisting mainly of lead and tin.

Abstract: A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.

Abstract: An ohmic contact electrode formed on an n-type semiconductor cubic boron nitride by using a IVa metal; an alloy with a IVa metal; a metal with Si or S; an alloy with Si or S; a metal with B, Al, Ga, or In; an alloy with B, Al, Ga, or In; a Va metal; or an alloy with a Va metal.

Abstract: An improved electric device utilizing a superconducting material. In order to avoid undesirable oxidation during firing of a ceramic to be superconducting material formed on the substrate, the superconducting material is provided only on the position in which the superconducting material does not contact the operational region of said semiconductor substrate.

Abstract: A semiconductor device comprises;a collector region of first conductivity type;a base region of second conductivity type;an emitter region of the first conductivity type; a thin film provided on the emitter region and capable of flowing therein a tunnel current; anda polycrystalline layer laminated on the thin film. An energy .DELTA..phi..sub.B of potential barrier formed at a grain boundary is not less than a heat energy kT at a temperature therein.

Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A semiconductor body (1) defines at least one active device. In the example shown in FIG. 1 complementary n channel and p channel IGFETs (10 and 20) are provided. An electrically conductive region, which may form the gate conductive region (101 and 102) of the insulated gates (11 and 21) of an IGFET, is provided on a first major surface (2) of the semiconductor body (1) and is encapsulated within a covering insulating region (300,400). An area (100a) of the electrically conductive region (101 and 102) contacts a relatively highly doped semiconductor region (50) provided adjacent the one major surface (2) and electrical contact is made to the electrically conductive region (101 and 102) via a conductive track (205) provided on the first major surface (2) and a conductive path provided by the relatively highly doped semiconductor region (50).

Abstract: Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.

Abstract: A metal silicide layer in or on a body of silicon wafer is used for interconnecting two or more CMOS circuit devices. In addition to a polysilicon layer and a metal layer, the metal silicide layer provides an additional layer of local interconnect which can be performed at high density to reduce the size of the die while including the same number of circuit devices. An amorphous silicon layer doped at selected regions may be used as an additional interconnect.

Abstract: A semiconductor device in which both a bipolar element and a MOS element are formed on a single semiconductor substrate. This device is composed of a semiconductor substrate, a bipolar element formed on the substrate so as to insulate a base region and an emitter electrode from one another by a base/emitter electrode insulating film, and a MOS element formed on the substrate in such a manner that a gate electrode together with an emitter electrode of the bipolar element are formed in a common layer and that a gate oxide film is formed between the gate electrode and another layer adjacent to and under the first-named layer. The base/emitter electrode insulating film has a thickness greater than that of the gate oxide film.

Abstract: A high integration semiconductor device comprises a semiconductor substrate and element separating regions formed on the semiconductor substrate to divide the semiconductor substrate into a plurality of regions to be formed as semiconductor active regions. The semiconductor active regions have contact portions for conducting the semiconductor active regions to other portions. The element separating regions are so constituted that the width of a short side of each of the semiconductor active regions at each contact portion is narrower than the width of a short side of the other portion of the semiconductor active region.

Abstract: A semiconductor integrated circuit device capable of having a high integration density and excellent performance and a method of fabricating the semiconductor integrated circuit device are disclosed. In this semiconductor integrated circuit device, a connecting conductor for connecting gate wiring which is formed on a field oxide film and extended from the gate of a MOSFET, to the source/drain region of another MOSFET is interposed between the gate wiring and one of two side space layers for defining the width of the gate wiring.

Abstract: A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.