At Least One Layer Of An Alloy Containing Aluminum Patents (Class 257/765)
  • Patent number: 10872846
    Abstract: A solid top terminal for discrete power devices. In one embodiment, an apparatus is formed that includes a first die comprising a transistor, which in turn includes a first electrode such as an emitter. The apparatus also includes a first conductor sintered to an electroplated second conductor such as a solid top terminal. Importantly, the first conductor is electrically coupled to the first electrode.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 22, 2020
    Assignee: Renesas Electronics America Inc.
    Inventor: Jean Claude Harel
  • Patent number: 10847470
    Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 24, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia Ching Chen, Yi Chuan Ding
  • Patent number: 10763184
    Abstract: A power module substrate or the like including an insulating substrate with an upper surface and a lower surface, a metal plate with an upper surface and a lower surface, the lower surface facing and being bonded to the upper surface of the insulating substrate, and a first electroplating layer that partly covers the central portion of the upper surface of the metal plate. The first electroplating layer includes at least a silver layer, and the grain size of silver in the silver layer is more than or equal to the grain size of a metal in an upper surface portion of the metal plate.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 1, 2020
    Assignee: Kyocera Corporation
    Inventors: Kenji Suetsugu, Akira Takeo, Kensou Ochiai
  • Patent number: 10559659
    Abstract: A power semiconductor device includes an emitter electrode disposed on a semiconductor substrate and through which a main current flows, a conductive layer that is disposed on the emitter electrode and is not a sintered compact, and a sintered metal layer that is disposed on the conductive layer and is a sintered compact. The sintered metal layer has a size to cover all the emitter electrode in plan view, and has higher heat conductivity than the conductive layer. The power semiconductor device can improve heat dissipation performance and adhesion.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: February 11, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Atsufumi Inoue, Seiji Oka, Tsuyoshi Kawakami, Akihiko Furukawa, Hidetada Tokioka, Mutsumi Tsuda, Yasushi Fujioka
  • Patent number: 10510688
    Abstract: The present disclosure relates to an integrated circuit having a via rail that prevents reliability concerns such as electro-migration. In some embodiments, the integrated circuit has a first plurality of conductive contacts arranged over a semiconductor substrate. A first metal interconnect wire is arranged over the first plurality of conductive contacts, and a second metal interconnect wire is arranged over the first metal interconnect wire. A via rail is arranged over the first metal interconnect wire and electrically couples the first metal interconnect wire and the second metal interconnect wire. The via rail has a length that continuously extends over two or more of the plurality of conductive contacts. The length of via rail provides for an increased cross-sectional area both between the first metal interconnect wire and the second metal interconnect wire and along a length of the via rail, thereby mitigating electro-migration within the integrated circuit.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Patent number: 9691870
    Abstract: A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 ?m.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 27, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takashi Ushijima, Tsuyoshi Nishiwaki, Masakazu Okada
  • Patent number: 9504152
    Abstract: A printed circuit board for a semiconductor package including a printed circuit board body, a plurality of ball lands on one surface of the printed circuit board body, a first plating layer on a portion of each of the ball lands, and a second plating layer on another portion of each of the ball lands may be provided. An upper surface of the first plating layer may be coplanar with an upper surface of the second plating layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hai Liu
  • Patent number: 9343422
    Abstract: A semiconductor structure is disclosed, wherein for a certain percentage of a plurality of bonding pads, the bonding pad metal may include a plurality of grains, wherein the plurality of grains may include a bonding grain. The bonding grain may have a width substantially the same as the width of the wire bonded to the bonding pad such that no grain boundaries are present below the wire bond.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 17, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Rama I. Hegde
  • Patent number: 9337113
    Abstract: A semiconductor device includes a transistor, lead frames, a metal spacer, one surface of which is bonded to the transistor by a first bonding material and the other surface of which is bonded to the lead frame by a second bonding material, and a plastic mold. The plastic mold packages the transistor and the metal spacer. One surface of each of the lead frames is attached to the plastic mold. Strength of the second bonding material is lower than strength of the first bonding material. According to the above configuration, when stress is repeatedly applied to the semiconductor device, a crack occurs earlier in the second bonding material than in the first bonding material. The stress is buffered at the first bonding material.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 10, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Rintaro Asai, Atsushi Tanida
  • Patent number: 9153525
    Abstract: A semiconductor device includes: a semiconductor element that includes an electrode layer on a surface of the semiconductor element; a low-strength layer that is provided on a surface of the electrode layer; a bonding layer that is provided on a surface of the low-strength layer; and a conductive plate that is provided on a surface of the bonding layer. Strength of the bonding layer is higher than strength of the electrode layer, and strength of the low-strength layer is lower than the strength of the electrode layer.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 6, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Toru Tanaka
  • Patent number: 9117799
    Abstract: In a method of manufacturing semiconductor device, an insulating film is provided on a surface of a semiconductor substrate, a porous metal film containing numerous voids is formed on a region of the insulating film, and a protective film is provided on the porous metal film. The protective film is provided with an opening portion on the porous metal film, with the opening portion defining a pad region. A wire is wire-bonded to the porous metal film in the pad region.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 25, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Masaru Akino
  • Patent number: 9082756
    Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 14, 2015
    Assignee: Fujitsu Limited
    Inventors: Kozo Shimizu, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
  • Patent number: 9040992
    Abstract: A display device includes a laminated wiring formed of a low-resistance conductive film, and a low-reflection film mainly containing Al and functioning as an antireflective film which are sequentially arranged on a transparent substrate, a wiring terminal part provided at an end part of the laminated wiring and has the same laminated structure as that of the laminated wiring, and an insulating film for covering the laminated wiring and the wiring terminal part, in which the insulating film side serves as a display surface side, the wiring terminal part has a first opening part penetrating the insulating film and the low-reflection film and reaching the low-resistance conductive film, and an outer peripheral portion of the first opening part has a laminated structure of the low-resistance conductive film, the low-reflection film, and the insulating film, in at least one part.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: May 26, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masami Hayashi, Kenichi Miyamoto, Kazushi Yamayoshi, Junichi Tsuchimichi
  • Publication number: 20150123279
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • Patent number: 9006899
    Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Kurt Matoy, Martin Sporn, Mark Harrison
  • Patent number: 9006900
    Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chih Wang, Yao-Hsiang Liang
  • Patent number: 8975670
    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20150054161
    Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 26, 2015
    Inventors: Kuei-Sung Chang, Nien-Tsung Tsai, Ting-Hau Wu, Yi Heng Tsai
  • Patent number: 8963325
    Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Baik-woo Lee, Young-hun Byun, Seong-woon Booh, Chang-mo Jeong
  • Patent number: 8952543
    Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Pil-Kyu Kang, Kyu-Ha Lee, Byung-Lyul Park, Hyun-Soo Chung, Gil-Heyun Choi
  • Patent number: 8912559
    Abstract: A Group III nitride semiconductor light-emitting device, includes a groove having a depth extending from the top surface of a p-type layer to an n-type layer is provided in a region overlapping (in plan view) with the wiring portion of an n-electrode or the wiring portion of a p-electrode. An insulating film is provided so as to continuously cover the side surfaces and bottom surface of the groove, the p-type layer, and an ITO electrode. The insulating film incorporates therein reflective films in regions directly below the n-electrode and the p-electrode (on the side of a sapphire substrate). The reflective films in regions directly below the wiring portion of the n-electrode and the wiring portion of the p-electrode are located at a level lower than that of a light-emitting layer. The n-electrode and the p-electrode are covered with an additional insulating film.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 16, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shingo Totani, Masashi Deguchi, Naoki Nakajo
  • Publication number: 20140339702
    Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Applicant: INVENSAS CORPORATION
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Michael Newman, Pezhman Monadgemi, Terrence Caskey
  • Patent number: 8872341
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Heike Rosslau, Norbert Urbansky, Scott Wallace
  • Patent number: 8866298
    Abstract: A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8860135
    Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 14, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Wei-Yu Chen, Chin-Fu Lin, Jing-Gang Li, Min-Hsien Chen, Jian-Hong Su
  • Patent number: 8823136
    Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Wayne H. Woods
  • Patent number: 8791576
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8786090
    Abstract: The present invention provides an Al alloy film for a display device, to be directly connected to a conductive oxide film on a substrate, the Al alloy film comprising Ge in an amount of 0.05 to 0.5 at %, and comprising Gd and/or La in a total amount of 0.05 to 0.45 at %, a display device using the same, and a sputtering target for the display device. For the Al alloy film of the present invention, even when a barrier metal is not provided, and a conductive oxide film and the Al alloy film are directly connected, the adhesion between the conductive oxide film and the Al alloy film is high, and the contact resistivity is low, and preferably, the dry etching property is also excellent.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: July 22, 2014
    Assignee: Kobe Steel, Ltd.
    Inventors: Hiroshi Gotou, Katsufumi Tomihisa, Aya Hino, Hiroyuki Okuno, Junichi Nakai, Nobuyuki Kawakami, Mototaka Ochi
  • Patent number: 8766448
    Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 1, 2014
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Xuhong Hu, Michael Shur
  • Publication number: 20140167268
    Abstract: A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 8735280
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A conductive layer is deposited on the substrate. A patterned hard mask is formed on the conductive layer and then a patterned photoresist is formed on the patterned hard mask and the conductive layer. A local metal catalyst layer is formed on the conductive layer in the openings of the patterned photoresist. Carbon nanotubes (CNTs) are grown from the local metal catalyst layer. The conductive layer is etched by using the CNTs and the patterned hard mask as etching mask to form metal features. An inter-level dielectric (ILD) layer is deposited between metal features.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 27, 2014
    Inventors: Ching-Fu Yeh, Hsiang-Huan Lee, Chao-Hsien Peng, Hsien-Chang Wu
  • Patent number: 8729707
    Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 20, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8716864
    Abstract: A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: May 6, 2014
    Assignee: IXYS Corporation
    Inventor: Nathan Zommer
  • Patent number: 8710673
    Abstract: A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Soon Bae, Sei-Ryung Choi
  • Patent number: 8653663
    Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: February 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kuang Kao, Huei-Wen Yang, Yung-Sheng Huang, Yu-Wen Lin
  • Patent number: 8648465
    Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Geraud Jean-Michel Dubois, Daniel C. Edelstein, Takeshi Nogami, Daniel P. Sanders
  • Publication number: 20140021619
    Abstract: An integrated circuit chip includes a substrate; at least one inter-metal dielectric layer over the substrate; a topmost metal layer overlying the inter-metal dielectric layer; a bonding pad in the topmost metal layer, the bonding pad comprising a central thinner portion and a peripheral thicker portion surrounding the central thinner portion; and a passivation layer covering the peripheral thicker portion.
    Type: Application
    Filed: October 1, 2013
    Publication date: January 23, 2014
    Applicant: MEDIATEK INC.
    Inventor: Yu-Hua Huang
  • Publication number: 20130328204
    Abstract: A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicant: IXYS Corporation
    Inventor: Nathan Zommer
  • Patent number: 8598703
    Abstract: A semiconductor device having a via chain circuit including a plurality of fine interconnections and an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the via chain circuit. One or more of the fine interconnections becomes wider gradually towards the connection to the extension interconnection. The extension interconnection is formed in a same layer as the one or more of the fine interconnections connected to the extension interconnection. The one or more of the fine interconnections connected to the extension interconnection is connected to the extension interconnections at a position where the fine interconnections become wider.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: December 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihisa Matsubara
  • Patent number: 8592977
    Abstract: A method for fabricating an integrated circuit (IC) chip includes providing a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, next forming a first titanium-containing layer over the pad exposed by the opening, next performing an annealing process by heating the titanium-containing layer at a temperature of between 300 and 410° C. for a time of between 20 and 150 minutes in a nitrogen ambient with a nitrogen purity of great than 99%, next forming a second titanium-containing layer on the first titanium-containing layer, and then forming a metal layer on the second titanium-containing layer.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 26, 2013
    Assignee: Megit Acquisition Corp.
    Inventors: Chiu-Ming Chou, Jin-Yuan Lee
  • Patent number: 8546944
    Abstract: A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventor: Kyu S. Min
  • Patent number: 8525330
    Abstract: Provided is a connecting part for a semiconductor device including a semiconductor element, a frame, and a connecting part which connects the semiconductor element and the frame to each other, in which an interface between the connecting part and the semiconductor element and an interface between the connecting part and the frame respectively have the area of Al oxide film which is more than 0% and less than 5% of entire area of the respective interfaces. The connecting part has an Al-based layer and first and second Zn-based layers on main surfaces of the Al-based layer, a thickness ratio of the Al-based layer relative to the Zn-based layers being less than 0.59.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 3, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Masahide Okamoto, Osamu Ikeda, Yuki Murasato
  • Patent number: 8519539
    Abstract: A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 27, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Ha Jung, Baek Mann Kim, Soo Hyun Kim, Young Jin Lee, Sun Woo Hwang, Jeong Tae Kim
  • Patent number: 8513115
    Abstract: A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 20, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Jung Wang
  • Patent number: 8508046
    Abstract: A circuit substrate is presented. The circuit substrate comprises internal terminal electrode 2; a substrate 1; a wiring layer 21 formed on a portion of the surface of the substrate and having one end thereof connected to the internal terminal electrode; an insulating film contacting as a surface with the wiring layer; and an external terminal electrode 9 connected to the other end of the wiring layer and used for connecting to the exterior. The angle of the cross-section of the wiring layer taken perpendicularly to the surface of the substrate in the edge portion that the wiring layer contains is 55° (55 degree) or less, and the wiring layer that contains multiple mutually independent columnar crystals extending perpendicularly in a direction different from the direction of the surface of the substrate.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: August 13, 2013
    Assignee: DISCO Corporation
    Inventors: Masao Sakuma, Kanji Otsuka
  • Patent number: 8466569
    Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: June 18, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen Arlon Meisner, Scott R. Summerfelt
  • Publication number: 20130105979
    Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.
    Type: Application
    Filed: May 30, 2012
    Publication date: May 2, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chen Yung Ching
  • Patent number: 8426972
    Abstract: A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an Al—Si (aluminum-silicon alloy) layer, an Al—Cu (aluminum-copper alloy) layer and an Al—Si—Cu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 23, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Keisuke Kimura
  • Patent number: 8422207
    Abstract: Disclosed is an Al alloy film for a display device that, even when low-temperature heat treatment is applied, can realize satisfactorily low electric resistance, can realize a satisfactory reduction in contact resistance between the Al alloy film and a transparent pixel electrode connected directly to the Al alloy film, and has excellent corrosion resistance. The Al alloy film is connected directly to a transparent electroconductive film on the substrate in the display device. The Al alloy film comprises 0.05 to 0.5 atomic % of Co and 0.2 to 1.0 atomic % of Ge and satisfies the requirement that the content of Co and the content of Ge in the Al alloy film have a relationship represented by formula (1): [Ge]??0.25×[Co]+0.2 (1) In formula (1), [Ge] represents the content of Ge in the Al alloy film, atomic %; and [Co] represents the content of Co in the Al alloy film, atomic %.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: April 16, 2013
    Assignee: Kobe Steel, Ltd.
    Inventors: Junichi Nakai, Akira Nanbu, Hiroshi Goto, Hiroyuki Okuno, Aya Miki
  • Patent number: RE45481
    Abstract: An interconnector line of thin film comprising 0.001 to 30 at % of at least one kind of a first element capable of constituting an intermetallic compound of aluminum and/or having a higher standard electrode potential than aluminum, for example, at least one kind of the first element selected from Y, Sc, La, Ce, Nd, Sm, Gd, Tb, Dy, Er, Th, Sr, Ti, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Tc, Re, Fe, Co, Ni, Pd, Ir, Pt, Cu, Ag, Au, Cd, Si, Pb and B; and one kind of a second element selected from C, O, N and H in a proportion of 0.01 at ppm to 50 at % of the first element, with the balance comprising substantially Al. In addition to having low resistance, such an Al interconnector line of thin film can prevent the occurrence of hillocks and the electrochemical reaction with an ITO electrode. The interconnector line of thin film can be obtained by sputtering in a dust-free manner by using a sputter target having a similar composition.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ishigami, Koichi Watanabe, Akihisa Nitta, Toshihiro Maki, Noriaki Yagi