Abstract: Disclosed is an Al alloy film for a display device that, even when low-temperature heat treatment is applied, can realize satisfactorily low electric resistance, can realize a satisfactory reduction in contact resistance between the Al alloy film and a transparent pixel electrode connected directly to the Al alloy film, and has excellent corrosion resistance. The Al alloy film is connected directly to a transparent electroconductive film on the substrate in the display device. The Al alloy film comprises 0.05 to 0.5 atomic % of Co and 0.2 to 1.0 atomic % of Ge and satisfies the requirement that the content of Co and the content of Ge in the Al alloy film have a relationship represented by formula (1): [Ge]??0.25×[Co]+0.2 (1) In formula (1), [Ge] represents the content of Ge in the Al alloy film, atomic %; and [Co] represents the content of Co in the Al alloy film, atomic %.

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: According to one embodiment, between the mounting substrate and the semiconductor chip, there is a joint support layer including a metal or its alloy selected from the group of Cu, Al, Ag, Ni, Cr, Zr and Ti and a melt layer laminated across the joint support layer, and formed of a metal selected from the group of Sn, Zn and In or of an alloy of at least two metals selected from the same metals. The process of joining the mounting substrate and the semiconductor chip includes intervening a joining layer which is formed, at least for its outermost layer, by the melt layer, maintaining the temperature to be higher than the melting point of the melt layer, then forming an alloy layer which has a higher melting point than the melt layer by liquid phase diffusion.

Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.

Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

Abstract: A semiconductor device having a via chain circuit including a plurality of fine interconnections and an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the via chain circuit. One or more of the fine interconnections becomes wider gradually towards the connection to the extension interconnection. The extension interconnection is formed in a same layer as the one or more of the fine interconnections connected to the extension interconnection. The one or more of the fine interconnections connected to the extension interconnection is connected to the extension interconnections at a position where the fine interconnections become wider.

Abstract: A vertical semiconductor power switch has a semiconductor body having a first surface and a second surface. At least one anode and one control electrode are positioned on the first surface and at least one cathode is positioned on the second surface. The cathode comprises a multi-layer contact structure which comprises an inner contact layer positioned directly on the second surface of the semiconductor body, and an outermost layer consisting essentially of a Ni-alloy.

Abstract: A semiconductor apparatus includes an aluminum electrode film formed on a semiconductor chip; and a nickel plated layer formed on the aluminum electrode film, wherein a concentration of sodium and potassium present in the nickel plated layer and at an interface between the nickel plated layer and the aluminum electrode film is 3.20×1014 atoms/cm2 or less.

Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Abstract: A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the cobalt species by a metallic species having a less negative standard electrode potential, such as nickel. Consequently, device performance may be enhanced, while at the same time the overall process complexity may be reduced.

Abstract: An interconnection structure, containing a substrate and, in the following order from a side of the substrate: (I) a semiconductor layer; (II) a multilayer structure including (II-a) a first layer containing at least one type of an element selected from the group consisting of nitrogen, carbon and fluorine and (II-b) an Al—Si diffusion layer containing Al and Si; and (III) an Al film of pure Al or an Al alloy, wherein the at least one of element selected from the group consisting of nitrogen, carbon, and fluorine in the first layer is bonded with Si contained in the semiconductor layer.

Abstract: An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded between the aluminum bond pad of the die and the silver bond pad of the lead frame. The package including an encapsulant envelope and including various materials and bond pad structures and constructed in a manner formed by thermosonically or thermocompressionally bonding the gold balls to the bond pads. Also, disclosed are methods of making the package.

Abstract: A semiconductor light-emitting element includes a semiconductor laminated body including a first conductivity type layer, a light-emitting layer and a second conductivity type layer in this order, a transparent electrode formed on the first conductivity type layer and comprising an oxide, and an auxiliary electrode formed between the first conductivity type layer and the transparent electrode, the auxiliary electrode having a higher reflectivity to light emitted from the light-emitting layer, a larger contact resistance with the first conductivity type layer and a smaller sheet resistance than the transparent electrode.

Abstract: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.

Abstract: A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate.

Abstract: Disclosed is a reflective anode electrode for an organic EL display, which comprises a novel Al-based alloy reflective film. The reflective anode electrode is capable of assuring low contact resistance and high reflectance even in cases where the Al reflective film is in direct contact with an oxide conductive film such as an ITO or IZO film. In addition, when the Al reflective film is formed into a laminated structure together with the oxide conductive film, the work function of the surface of the upper oxide conductive film is equally high with the work function of a laminated structure that is composed of a general-purpose Ag-based alloy film and an oxide conductive film. Specifically disclosed is a reflective anode electrode for an organic EL display, which is formed on a substrate and characterized by comprising a laminated structure that is composed of an Al-based alloy film containing 0.

Abstract: Lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between the input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper.

Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.

Abstract: The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the interface to avoid electromigration and stress-inducing voids, and having a highly reliable wire. An interlayer insulating film, and a first etching-stopper film are formed on a semiconductor substrate on which a semiconductor device is fabricated. A first alloy-wire covered with a first barrier metal film is formed on the first etching-stopper film by a damascene process. The first alloy-wire is covered at an upper surface thereof with a first wire-protection film. The first wire-protection film covering an upper surface of the first alloy-wire contains at least one metal among metals contained in the first alloy-wire.

Abstract: A method of manufacturing a semiconductor device having a back surface electrode, including: a step of preparing a semiconductor wafer having a front surface and a back surface; a thermal processing step of forming a first metal layer on the back surface of the semiconductor wafer and executing thermal processing, thereby creating an ohmic contact between the semiconductor wafer and the first metal layer; and a step of forming a second metal layer of Ni on the back surface of the semiconductor substrate after the thermal processing step.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: When connecting with a conventional Zn/Al/Zn cladding material, thickness of a connecting part needs to be less than double an existing high-lead solder (about 100 ?m) in order to make heat resistance in the connecting part at least equivalent to a level of the existing solder. Moreover, thickness of an Al layer needs to make as thick as possible in order to fully exhibit stress relaxation performance of the Al layer. Provided is a semiconductor device including a semiconductor element, a frame, and a connecting part which connects the semiconductor element and the frame to each other, in which an interface between the connecting part and the semiconductor element and an interface between the connecting part and the frame respectively have the area of Al oxide film which is more than 0% and less than 5% of entire area of the respective interfaces.

Abstract: A display device in which an Al alloy film and a conductive oxide film are directly connected without interposition of refractory metal and some or all of Al alloy components deposit or are concentrated at the interface of contact between the Al alloy film and the conductive oxide film. The Al alloy film contains 0.1 to 6 at % of at least one element selected from the group consisting of Ni, Ag, Zn, Cu and Ge, and further contains 1) 0.1 to 2 at % of at least one element selected from the group consisting of Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu and Dy or 2) 0.1 to 1 at % of at least one element selected from the group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta and W, as the alloy components.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer.

Abstract: An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.

Abstract: A method of manufacturing a semiconductor device having a back surface electrode, including: a step of preparing a semiconductor wafer having a front surface and a back surface; a thermal processing step of forming a first metal layer on the back surface of the semiconductor wafer and executing thermal processing, thereby creating an ohmic contact between the semiconductor wafer and the first metal layer; and a step of forming a second metal layer of Ni on the back surface of the semiconductor substrate after the thermal processing step.

Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

Abstract: According to the method for manufacturing a semiconductor device, a surface of a lower insulating film (55) is planarized by CMP or the like, and an upper insulating film (56) and a protective metal film (59) are formed on the lower insulating film (55). Accordingly, the upper insulating film (56) and the protective metal film (59) are formed in such a manner they have an excellent coverage and the water/hydrogen blocking capability of the upper insulating film (56) and the protective metal film (59) is maximized.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer.

Abstract: An IC chip coating material includes first metal oxide particles; a metal alkoxide; an organic solvent; and second metal oxide particles and/or flat particles of a composite oxide, the second metal oxide particles having a composition identical to or different from that of the first metal oxide particles and also having a mean particle size and/or a shape different from that of the first metal oxide particles. Further, a vacuum fluorescent display device includes an IC chip, wherein the IC chip is at least partially coated by a coating material layer including the first metal oxide particles; a metal forming metal alkoxide; and the second metal oxide particles and/or flat particles of a composite oxide.

Abstract: One or more embodiments relate to a semiconductor device, comprising: a Si-containing layer; a barrier layer disposed over the Si-containing layer, the barrier layer comprising a compound including a metallic element; a metallic nucleation_seed layer disposed over the barrier layer, the nucleation_seed layer including the metallic element; and a metallic interconnect layer disposed over the nucleation_seed layer, the interconnect layer comprising at least one element selected from the group consisting of Cu (copper), Au (gold), and Ag (silver).

Abstract: An arrangement having a first and a second substrate is disclosed, wherein the two substrates are connected to one another by means of an SLID (Solid Liquid InterDiffusion) bond. The SLID bond exhibits a first metallic material and a second metallic material, wherein the SLID bond comprises the intermetallic Al/Sn-phase.

Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film, a tungsten film, a first barrier metal film, a second barrier metal film and a metal wiring film. The interlayer insulating film is formed on the semiconductor substrate, and has an opening. The tungsten film is embedded in the opening. The first barrier metal film is formed on the tungsten film and excludes a Ti film. The second barrier metal film is formed on the first barrier metal film and is a Ti-containing film. The metal wiring film is formed on the second barrier metal film.

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: An integrated circuit chip includes a substrate; a topmost metal layer overlying the substrate; and a pad in the topmost metal layer. A thickness of the pad is less than a thickness of the topmost metal layer.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: An electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode. A bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the constituent element of the metal nanoparticles.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: A hillock-free conductive layer comprising at least two aluminum (Al) layers formed on a substrate, wherein said at least two Al layers comprise a barrier Al layer formed on the substrate, and a pure Al layer formed on the barrier Al layer. The barrier Al layer could be an aluminum nitride (AlNx) layer, an aluminum oxide (AlOx) layer, an aluminum oxide-nitride (AlOxNy) layer, or an Al—Nd alloy layer. Also, the pure Al layer is physically thicker than the barrier Al layer, for effectively inhibiting the occurrence of hillocks and the like.

Abstract: A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a second conductor layer, and a third conductor layer. The first conductor layer makes contact with the surface of the silicon substrate and includes aluminum and silicon. The second conductor layer makes contact with the first conductor layer and includes titanium. The third conductor layer is separated from the first conductor layer by the second conductor layer and includes nickel.

Abstract: A redundant diffusion barrier structure and method of fabricated is provided for interconnect and wiring applications. The structure can also be a design structure. The structure includes a first liner lining at least one of a trench and a via and a second liner deposited over the first liner. The second liner comprises RuX. X is at least one of Boron and Phosphorous. The structure comprises a metal deposited on the second liner in the at least one trench and via to form a metal interconnect or wiring.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: An integrated circuit chip includes a substrate; a topmost metal layer over the substrate; a lower metal layer on or over the substrate and lower than the topmost metal layer; and at least one bonding pad in the lower metal layer.

Abstract: Disclosed is an electrode for semiconductor devices capable of suppressing the generation of hillocks and reducing the resistivity, which is suitable for an active matrixed liquid crystal display and the like in which a thin film transistor is used; its fabrication method; and a sputtering target for forming the electrode film for semiconductor devices. The electrode for semiconductor devices is made of an Al alloy containing the one or more alloying elements selected from Fe, Co, Ni, Ru, Rh and Ir, in a total amount from 0.1 to 10 At %, or one or more alloying elements selected from rare earth elements, in a total amount from 0.05 to 15 at %.