Abstract: In a semiconductor device having a first conductor layer (25) formed on a first insulator layer (23) and a second insulator layer (29) formed on the first conductor layer, a second conductor layer (31) has a primary conductor film (35) formed on the second insulator layer, a secondary conductor film (37) formed on the primary conductor film, and a ternary conductor film (63) formed on the secondary conductor film. The second insulator layer has a recessed surface (29b) which defines a contact perforation exposing a predetermined area of an upper surface (25a) of the first conductor layer. The secondary conductor film is further formed on the recessed surface and the predetermined area. The primary conductor film has a primary resistance value. The secondary conductor film has a secondary resistance value which is lower than the primary resistance value.

Abstract: A method of forming a contact diffusion barrier in a thin geometry integrated circuit device involves implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired. The low resistivity and implanted materials are selected to intereact with each other and form a contact diffusion barrier. Both materials may include transition metals, in which case the diffusion barrier is a composite transition metal. Alternately, the low resistivity material may include a transition metal, while implantation is performed with nitrogen. The implantation is performed by plasma etching, preferably with active cooling, which can be combined in a continuous step with the etching of the contact opening. The resulting contact diffusion barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.

Abstract: An improved solder-bonding structure is disclosed that is particularly suitable for soldering the components of hybrid ICs. The solder-bonding structure includes a conductor formed on a substrate. The conductor is formed from silver and platinum. A solder layer formed from a tin and silver solder is then formed on the conductor to couple an electronic element to the conductor. In preferred aspects of the invention, the platinum content in the conductor is in the range of approximately 0.7 to 1.0% by weight. The silver content in the solder layer is in the range of approximately 0.1 to 5.0% by weight.

Abstract: In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer insulating film is formed on the semiconductor substrate for the purpose of protecting and stabilizing the surface of the semiconductor substrate, and an interconnection electrically connected to the impurity diffused layer through a contact hole and formed on an Al-Si-Sn alloy, an Al-Si-Sb alloy or alloys having Ti added to the respective alloys, so that occurrence of an alloy pit and a silicon nodule is prevented. In addition, a completed protective film is formed on the interconnection and the underlayer insulating film and an aperture in a bonding pad region is formed in a predetermined region of the completed protective film, so that the interconnection and the bonding pad are electrically connected to each other.

Abstract: A microelectronic device (10) provides decreased use of bar area to form contacts between a conductive strap (24) or interconnect and subsequent levels. The conductive strap comprises a conducting layer (130) and an overlying semiconducting layer (132). Connection to subsequent levels is made generally overlying substrate conductive areas such as a gate (14) and/or a moat (16). Connection to conductive sublayer (130) is accomplished by doping an overlying semiconductor sublayer (132). Any counter-doping of substrate conductive areas is blocked by an overlying well of dopant-masking (33) or sufficiently thick semiconducting (32) material.

Abstract: In a semiconductor device having gold interconnections for connecting elements formed on a substrate with each other, the improvement is that the average dimension of gold grains constituting the gold interconnections is determined to be 0.17 through 0.25 times as large as width of the gold interconnections.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: A metallization composite comprises a refractory metal, nickel, and copper. The refractory metal is preferably titanium (Ti), but other suitable refractory metals such as zirconium and hafnium can also be utilized. An additional optional layer of gold can overlie the copper. The metallization composite is used to connect a solder contact to a semiconductor substrate.

Abstract: A plastic sealed semiconductor device designed to prevent sliding of wiring due to thermal stress is disclosed. A lower layer wiring is provided adjacent to an outside of a portion of an uppermost layer of wiring covered by a cover film, which is arranged closest to an outer periphery of the semiconductor chip. Compressive stress of the sealing resin is divided by a step portion due to the uppermost layer of wiring and a step portion due to the lower layer of wiring. Further, since the interlayer insulating film covering the lower layer of wiring is flattened, the step portions are inclined gently in which stress is further divided. Therefore, the sliding of wiring is reliably prevented.

Abstract: A micro metal-wiring construction comprises a substrate having a first insulating layer thereon, a metal wiring formed on the first insulating layer of the substrate, and a second insulating layer covering the metal wiring. The coefficient of thermal expansion of the metal wiring is greater than those of the first and the second insulating layers. Intersection lines formed between grain boundaries of the metal wiring and a surface of the first insulating layer is nearly perpendicular to an extending direction of the metal wiring and an angle between grain boundary planes and a line that is perpendicular to a surface of the first insulating layer is greater than 20 degrees. Metal-wiring having a good resistance against stress-induced-migration is obtained by providing when this angle is greater than 20.degree..

Abstract: A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).

Abstract: Interconnect or metallization structures for integrated circuits on semiconductor chips contain blocked conductor segments to limit atomic transport from one segment to another thus minimizing stress migration and electromigration damage. Since the blocked conductor segments prevent atomic transport between two neighboring segments, the total amount of atoms and vacancies available for hillock and void growth in a segment can be controlled by the length of the segment. The conductor segments are made of high electrical conductance metals, such as aluminum, copper or gold based alloys, and are separated by very short segments of a high melting temperature refractory metal or alloy. Because of their high melting temperatures, refractory metals or alloys suppress atomic transport. The interconnect structures can be fabricated by conventional lithographic and deposition techniques.

Abstract: A method consists of the steps of depositing a Ti--Pt metal film on a SiN layer insulation film mounted on GaAs substrate, etching the Ti--Pt metal film to form a first metal layer, depositing a SrTiO.sub.3 insulating film, etching the SrTiO.sub.3 insulating film to form an insulating film, depositing a WSiN metal film according to a sputtering technique while controlling a deposition pressure of nitrogenous gas, etching the WSiN metal film to simultaneously form a second metal layer on the insulating film and a thin metal film resistive element on the SiN layer insulation film, depositing a SiO.sub.2 passivation film, and making via holes. SrTiO.sub.3 has a high relative dielectric constant, and WSiN has a high melting point. Nitrogen atoms in WSiN prevent oxygen atoms in the insulating film from diffusing into the second metal layer. The adhesion of second metal film to the insulating film is tight because of the sputtering technique.

Abstract: In a multi-layer wiring structure of an integrated circuit device, occurrence of voids due to electromigration in the vicinity of an interface between upper and lower wiring layers is suppressed. The interface is cleaned in vacuum and grain size of the wiring layers is controlled. After an interlayer insulating film (16) having a connection hole (16A) is formed to cover a first wiring layer (14) of Al or an Al alloy, a second wiring layer (18) of Al or an Al alloy is formed and connected to the first wiring layer through the connection hole. When the second wiring layer is formed, grains (G.sub.2) of the second wiring layer are formed so as to be :respectively continuously adjacent to and substantially equal in size to grains (G.sub.1) of the first wiring layer which appear at the interface.

Abstract: A bipolar transistor fabricated on a silicon layer has a base electrode with a multi-layered structure implemented by a titanium film, a titanium nitride film, a platinum film and a gold film, and the platinum film is regulated to 5 to 30 nanometers thick for decreasing the thermal stress between the platinum film and the titanium nitride film equal to or greater than 50 nanometers, thereby preventing the bipolar transistor from damage due to heat applications in later stages.

Abstract: A semiconductor device having a gold wiring layer for an element region is disclosed, in which the gold wiring layer is connected to the element region through a barrier metal layer, the barrier metal layer comprising first and second layers each containing titanium and a third layer sandwiched between the first and second layers and made of a selected one from platinum and palladium. The third layer effectively prevents gold in the gold wiring layer from diffusing into the element region and the second layer enhances the adhesion between the gold wiring layer and an insulating film.

Abstract: Epitaxial growth of films on single crystal substrates having a lattice mismatch of at least 10% through domain matching is achieved by maintaining na.sub.1 within 5% of ma.sub.2, wherein a.sub.1 is the lattice constant of the substrate, a.sub.2 is the lattice constant of the epitaxial layer and n and m are integers. The epitaxial layer can be TiN and the substrate can be Si or GaAs. For instance, epitaxial TiN films having low resistivity can be provided on (100) silicon and (100) GaAs substrates using a pulsed laser deposition method. The TiN films were characterized using X-ray diffraction (XRD), Rutherford back scattering (RBS), four-point-probe ac resistivity, high resolution transmission electron microscopy (TEM) and scanning electron microscopy (SEM) techniques. Epitaxial relationship was found to be <100> TiN aligned with <100> Si. TiN films showed 10-20% channeling yield. In the plane, four unit cells of TiN match with three unit cells of silicon with less than 4.0% misfit.

Abstract: A semiconductor memory device in which a protection layer is disposed between a silicon storage electrode and a tantalum pentoxide dielectric layer. A conductive material having a larger free energy of oxide formation than that of the tantalum pentoxide is used for forming the protection layer. Therefore, no native oxide film is formed at the interface between the storage electrode and the dielectric layer. As a result, the dielectric constant of the dielectric layer does not decrease even when the dielectric layer is a thin film.

Abstract: For enhanced resistance to electromigration failure, a thin metal film interconnect on an integrated circuit chip should use multiple parallel minimum-width lines when the minimum linewidth is less than one and one-half times the mean grain size of the metal film. When the interconnect is longer than a certain predetermined length, then the multiple lines of the interconnect should have intermediate interconnections or bridges between neighboring ones of the multiple lines. When the interconnect is many times longer than the predetermined length, then the bridges define slots between the neighboring lines, and the slots should have a length of about the predetermined length. When the interconnect is many times longer than the predetermined length and the interconnect has more than two parallel lines, then the slots on one side of a parallel line should be staggered or offset with respect to the slots on the other side of the parallel line.

Abstract: A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16, 18) formed on a frontside surface (12a), and via holes (12c, 12d) formed through the chip (12) from the frontside surface (12a) to a backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c, 12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold-tin alloy (20) through the via holes (12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16, 18).

Abstract: A semiconductor device is provided which includes a conductive layer, an insulating film formed on the surface of the conductive layer, and a conductive metal interconnection layer formed on the insulating film and electrically connected to the conductive layer through a contact hole formed in a predetermined position of the insulating film. The conductive metal interconnection and the surface of the conductive layer are directly joined together and a silicon layer including a single crystal or polycrystalline silicon having a grain size of at least about 10 .mu.m is interposed between the conductive metal interconnection layer and the insulating film. The conductive metal interconnection layer becomes a single crystal or a polycrystal having a grain size of about 10 .mu.m or above under the influence of the crystalline properties of the underlying crystal of the silicon layer.

Abstract: A wiring board has a wiring circuit which is reliable and which can be easily miniaturized, and used for the production of a highly integrated, lighter, thinner, shorter, smaller and low-cost semiconductor device. This wiring board can be sealed in a plastic package. The wiring board has a metal plate and a thin-film dielectric layer formed on the surface of the metal plate. A semiconductor device is mounted on the surface of the dielectric layer or the exposed surface of the metal plate. Film wirings are formed on the dielectric layer. Each film wiring is in the form of a laminate formed by laminating, by vapor phase deposition or by plating, a an aluminum conductive layer, an adhesive layer of chromium, titanium or a laminate thereof, a diffusion barrier layer of nickel, copper or a laminate thereof, and a corrosion-preventive and wire bonding layer of gold.

Abstract: A semiconductor device aluminum-containing metallization system that is particularly useful for integrated circuits (ICs) having P-type contact regions and also having a likelihood of extended exposure to elevated temperatures. Use of an aluminum/silicon diffusion barrier formed of an amorphous tungsten/silicon on such ICs is made commercially practical. A titanium or transition metal silicide layer is disposed beneath the amorphous tungsten/silicon layer, to consistently provide durable low resistance electrical contacts to P-type regions of the IC.

Abstract: A method for forming a self-aligned contact utilizes a thin insulating layer formed on the upper surface of a conductive layer. A barrier layer is deposited over the insulating layer, and gate electrodes are then defined. Sidewall spacers are formed along the vertical sidewalls of the gate electrodes. During formation of the sidewall spacers the barrier layer protects the gate electrodes. A second insulating layer is then deposited and a via is opened to the substrate. A contact can now be created by depositing conductive material into the via.

Abstract: This invention relates generally to structure and method for preventing metal diffusion between a noble metal layer and an adjoining non-noble metal layer, and more specifically to new structures and methods for providing a superbarrier structure between copper and an adjoining noble metal layer. This is achieved by sequentially deposited a layer of non-noble metal, a layer of titanium, a layer of molybdenum, and a layer of noble or relatively less noble metal as the interconnecting metallurgy. This invention also relates to an improved multilayer metallurgical pad or metallurgical structure for mating at least a portion of a pin or a connector or a wire to a substrate.

Abstract: A local interconnect silicide structure (30) for connecting silicon regions (16) to silicon regions (20) separated by oxide regions (24) comprises a first portion of titanium silicide/titanium nitride/titanium silicide contacting the silicon regions and a second portion of titanium/titanium nitride/titanium silicide contacting the oxide regions. The silicide structure is also useful for connecting source/drain regions (14) and polysilicon interconnects (28). Two separate heating steps are employed, separated by an etch step to form the interconnects (34, 36). The first heating step forms (a) titanium silicides with single or polycrystalline silicon, using a first titanium layer (30a) at the bottom of the silicide structure and (b) titanium silicides with amorphous silicon (30d), using a second titanium layer (30c) on top of the titanium nitride layer (30b) on which the amorphous silicon is deposited and then patterned.

Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.

Abstract: A semiconductor device with a semiconductor body (1) whose surface (4) is provided with a barrier layer (8) of Ti.sub.x W.sub.1-x, with 0.1<x<0.3. The barrier layer (8) is used, for example, between contact zones (3) of silicon or metal silicides provided in the semiconductor body (1) and conductor tracks (9) of aluminium provided on the surface (4) with the purpose of counteracting chemical reactions between silicon and aluminium. According to the invention, the barrier layer (8) is so deposited that in this layer the distance between the (100) lattice faces of tungsten is greater than 2.25.ANG.. It is achieved in this way that the barrier layer (8) has equally good or even better barrier properties as/than a Ti.sub.x W.sub.1-x layer which has been exposed to air for a few days. It is found that, if the barrier layer (8) is deposited by means of a sputter deposition process, the distance between the (100) lattice faces of W is determined by the voltage applied to the sputter target during deposition.

Abstract: A packaged device with a lead frame, a lead frame and an article of manufacture comprising a base metal, a layer of nickel on the base metal, and a protective composite of metal layers on the nickel. The composite includes, in succession from the nickel layer, a layer of palladium or soft gold strike, a layer of palladium-nickel alloy, a layer of palladium and a layer of gold. The palladium or soft gold strike layer acts primarily as a bonding (an adhesive) layer between the Ni and Pd-Ni alloy layers and as a layer that enhances reduction in porosity of subsequent layers, Pd-Ni alloy layer acts as a trap for base metal ions, Pd layer acts as a trap for Ni ions from the Pd-Ni alloy layer, and the outer gold layer synergistically enhances the quality to the Pd layer. The various layers are in thickness sufficient to effectively accomplish each of their designated roles, depending on the processing and use conditions.

Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process.

Abstract: A semiconductor integrated circuit device has an interconnection structure in which multilayer aluminum interconnection layers are connected through connection holes. A first aluminum interconnection layer is formed on a main surface of the semiconductor substrate. The first aluminum interconnection layer has a surface layer which includes any of high melting point metal, high melting point metal compound, high melting point metal silicide, or amorphous silicon. An insulating layer is formed on the first aluminum interconnection layer, and has a through hole if formed extending to a surface of the first aluminum interconnection layer. A second aluminum interconnection layer is formed on the insulating layer and is electrically connected to the surface layer of the first aluminum interconnection layer through the through hole. The second aluminum interconnection layer includes a titanium layer, a titanium nitride layer and an aluminum alloy layer.

Abstract: The present invention concerns a method for contact metallization on a semiconductor where a contact hole is formed in an interlevel dielectric layer down to a doped silicon region on the silicon substrate, and then the wafer is placed into a sputtering chamber where titanium is sputtered onto the wafer. A titanium nitride layer is sputtered on top of the titanium layer in the contact hole. This invention saves time and money, because the titanium nitride layer depositing and titanium layer forming steps can occur in the same chamber without forming the boro-phosphorous silicate glass layer in between. The titanium layer reacts with the silicon to form a silicide layer at the time of the sputtering in a hot deposition or in later steps that supply heat to the wafer for a period of time. Optionally, an additional titanium layer can be formed on top of the titanium nitride layer to clean off the titanium target used to sputter the titanium and titanium nitride layers on the wafer.

Abstract: An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.

Abstract: Each of the bit lines of a semiconductor memory has an intermediate section with low electrical resistance and low electromigration resistance. If the bit line is shorted to a word line, during burn-in the electrical resistance of the intermediate section increases because of electromigration, thereby preventing excess current from leaking through the shorted bit line during subsequent use.

Abstract: A multilevel metallization structure for a semiconductor device having an antireflective film and a migration resistant film. The antireflective film is formed on a lower metallization and an dielectric inter-level film is formed on the antireflective film. The dielectric inter-level film has an opening hole for exposing the surface of the lower metallization. The migration resistant film is formed on the dielectric inter-level film and the surfaces of side walls of the opening hole. The upper metallization is formed on the migration resistant film and inside the opening hole so as to directly connect to the lower metallization.

Abstract: A structure formed by the method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is provided through an insulating layer. A thin first layer of aluminium having a first grain size is sputter deposited over and in the opening covering the surface of the semiconductor region. A second layer of aluminium having a second and substantially different grain size from the thin first layer of aluminium is sputter deposited thereover. The resulting aluminum structure is subjected in its normal process of manufacture to temperature cycling of greater than about 300.degree. C. whereby any formed silicon nodules are preferentially formed at the boundary of the thin first layer of aluminium and the second layer of aluminium. The second layer of aluminium may in one alternative completely fill the opening. In another alternative, a third layer has substantially the same grain size as the first aluminum.

Abstract: A method for connecting devices on an integrated circuit substrate to a metallization layer, wherein a thin layer of a dielectric material is deposited on the substrate, and openings are formed in the dielectric layer wherein electrical connection is to be made to the substrate. A metal barrier layer then is deposited selectively in the openings of the dielectric layer, the barrier layer completely covering the exposed portions of the substrate. A pillar metal layer then may be deposited as a blanket coating over the dielectric layer and over the portions of he barrier layer covering the exposed portions of the substrate. The pillar metal layer is etched for forming metal pillars extending from the exposed portions of the substrate. The substrate then is planarized by depositing a dielectric layer and etching it back for exposing the pillars for coupling to a later deposited metallization layer.

Abstract: In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer insulating film is formed on the semiconductor substrate for the purpose of protecting and stabilizing the surface of the semiconductor substrate, and an interconnection electrically connected to the impurity diffused layer through a contact hole and formed on an Al-Si-Sn alloy, an Al-Si-Sb alloy or alloys having Ti added to the respective alloys, so that occurrence of an alloy pit and a silicon nodule is prevented. In addition, a completed protective film is formed on the interconnection and the underlayer insulating film and an aperture in a bonding pad region is formed in a predetermined region of the completed protective film, so that the interconnection and the bonding pad are electrically connected to each other.

Abstract: A semiconductor device having a reliable contact is disclosed. The device includes a barrier film deposited on the bottom and side wall of a contact hole opened in a insulating film at a predetermined position; a first metal film filled in the contact hole; and a second metal film of low resistance for forming an interconnection which passes above the contact hole filled in with the first metal film. An oxide film is formed by oxidation on the barrier metal film. And a method of manufacturing the semiconductor device is disclosed.

Abstract: Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movement avoided but electromigration problems are also decreased.

Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.