Abstract: A titanium film 14 is formed on a whole surface including an inner surface of a hole 10. Then the titanium film 14 outside of the interior of the hole 10 is removed by the chemical mechanical polishing (CMP) method, the resist etchback method or the ECR plasma etching method. Thereafter a titanium nitride film 15 is formed on the whole surface. Consequently, when a tungsten film 16 is formed, using a fluorine containing gas such as WF.sub.6 gas, etc., since there exists no titanium film 14 outside of the hole 10 and only the titanium nitride film 15 resistant to the fluorine containing gas exists there, no peeling-off of the titanium nitride film 15 due to corrosion of the titanium film 14 takes place, and thus it is prevented that it produces a dust source.

Abstract: A semiconductor apparatus having at least a compound film containing nitrogen and a method for production of the same, wherein the compound film containing nitrogen is formed under conditions where the ratio of the flow rates of the nitrogen with respect to an inert gas is 0.125 to 1.0.

Abstract: An integrated circuit structure, such as a stackable integrated circuit chip, having at least one face. The structure comprises at least one elongate conductor running therein and terminating in a contact section having an exposed end at the at least at one face of the structure. At least one face conductor forms an electrical interface with the exposed end of the contact section. Means for limiting electromigration about the electrical interface, such as a contact section of the conductor having a cross-sectional area greater then a nominal-sectional area of the conductor, are disclosed.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: A ceramic substrate for use with a semiconductor device, includes an electrical conductor composed of Ag, a resistor composed of oxide, and a barrier layer located between the electrical conductor and the resistor and composed of a material selected from a group consisting of AgPd and AgPt. The ceramic substrate prevents a diffusion of Ag atoms between the electrical conductor and the resistor, and hence provides a stable internal resistance.

Abstract: A semiconductor device having metal leads 14 with improved reliability comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and dummy leads 16 proximate the metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16, and the dummy leads 16 are capable of dissipating the heat. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is improved reliability of metal leads for circuits using low-dielectric constant materials.

Abstract: An improvement in a metal stack used for interconnecting structures in an integrated circuit. The improvement comprises the entrapping in a titanium layer of nitrogen at the interface where the titanium layer contacts a bulk conductor layer such as an aluminum-copper alloy layer. The entrapped nitrogen prevents the formation of any substantial amount of titanium aluminide thereby reducing current densities and also improving the electromigration properties of the stack. As currently preferred, the nitrogen is entrapped in approximately the first 30.ANG. of the titanium layer.

Abstract: An encapsulated electronic component containing a plurality of connection leads and an outer case, where the connection leads extend externally to the outer case and contain martensitic structural-hardening conductive alloy.

Abstract: There is disclosed a structure of and a method for fabricating a ferroelectric film on a non-conductive substrate. An adhesion layer, e.g., a layer of silicon dioxide and a layer of zirconium oxide, is deposited over a substrate. A conductive layer, e.g., a noble metal, a non-noble metal, or a conductive oxide, is deposited over the adhesion layer. A seed layer, e.g., a compound containing lead, lanthanum, titanium, and oxygen, with a controlled crystal lattice orientation, is deposited on the conductive layer. This seed layer has ferroelectric properties. Over the seed layer, another ferroelectric material, e.g., lead zirconium titanate, can be deposited with a tetragonal or rhombohedral crystalline lattice structure with predetermined and controlled crystal orientation.

Abstract: The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line, or providing longitudinally spaced apart holes or vias, to optimize the Backflow Potential Capacity of the metal interconnection line.

Abstract: The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line or providing longitudinally spaced apart holes or vias to optimize the backflow potential capacity of the metal interconnection line. In addition, elongated slots are formed through the metal interconnection line so that the total width of metal across the interconnection line is selected for optimum electromigration lifetime in accordance with the Bamboo Effect for that metal.

Abstract: The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.

Abstract: A barrier metal integrated circuit structure, including relatively thin, highly nitrided layers of TiW (i.e., TiW:N) straddling a central conductor layer, and in turn each being straddled by adjacent layers of relatively thick substantially un-nitrided TiW material, and a method for its fabrication including deposition of layers of TiW and TiW:N, the latter in a N.sub.2 dominated atmosphere and/or under backbias conditions effective for establishing at least a saturated level of nitrogen into the TiW:N, resulting in an effective barrier to migration of conductor materials from the conductor layer.

Abstract: A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal, interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

Abstract: The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.

Abstract: Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA.

Abstract: An Al layer which serves as a lead-out electrode is formed on a semiconductor chip. An insulating layer is formed on the semiconductor chip and the Al layer. The insulating layer has an opening formed in that portion thereof which is located on the Al layer, thereby exposing a portion of the Al layer. A multi-level metal layer (barrier metal layer) is formed on the exposed portion of the Al layer and on that portion of the insulating layer which is located along the edge of the opening. A metallic nitride region is provided between a first-level metal layer in the multi-level metal layer and the insulating layer so as to be selectively formed at or under a peripheral portion of the first-level metal layer. A bump electrode is provided on the multi-level metal layer. The resultant semiconductor device is mounted on a circuit board by flip chip bonding, with the bump electrode interposed therebetween.

Abstract: An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.

Abstract: A high aspect ratio submicron VLSI contact and corresponding method of manufacture is disclosed. The contact is formed through an insulative layer, such as silicon dioxide, to an underlying active region on a substrate of silicon wafer. The contact comprises a layer of titanium germanosilicide at the bottom of the contact opening, and a layer of titanium germanide at the sides of the contact opening, with an overlying layer of titanium nitride. The contact is metallized, preferably using tungsten or aluminum. The disclosed method of manufacturing the contact comprises first etching the contact opening, then exposing the bottom of the contact opening to germane gas to clean native silicon dioxide from the bottom of the contact opening. A 50 Angstrom layer of germanium is then deposited over the contact opening. A layer of titanium is then deposited over the germanium layer in the contact opening. The deposition of titanium is preferably accomplished using a collimator having an aspect ratio lower than about 2.

Abstract: A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C.

Abstract: On an insulating film covering the surface of a semiconductor substrate, a lower wiring layer made of Al or Al alloy is formed. An insulating film having a contact hole is formed on the lower wiring layer and the substrate. An upper wiring layer made of Al or Al alloy is formed on the insulating film and connected to the lower wiring layer via the contact hole. In such a multilayered wiring structure, the size of Al grain of the lower wiring layer, at least at the surface just under the contact hole, is made smaller than the bottom size of the contact hole. With this setting, Al atoms are supplied sufficiently from the lower wiring layer to the interface between the lower and upper wiring layers, preventing wiring disconnection caused by the peeling off of the interface.

Abstract: A plurality of contact holes having different sizes are formed in an insulating film formed on the substrate. A first barrier metal layer is formed on the insulating film, and a tungsten layer is uniformly formed on the first barrier metal layer. The tungsten layer is etched back to form plug-shaped tungsten regions in small contact holes and sloped tungsten regions in large contact holes. The central area of the first barrier metal layer in the large contact hole is exposed. A second barrier metal layer is formed covering the plug-shaped tungsten region and the tapered tungsten region and the exposed first barrier metal layer and sandwiching the plug-shaped and sloped tungsten regions between the first and second barrier metal layers, preventing pinch-through of Al atoms from an Al layer to be thereafter formed, into the substrate, even when the first barrier metal layer is damaged during etch-back.

Abstract: A semiconductor device which includes device bonding pads exposed through oxide windows formed in a passivation oxide layer providing electrical connections to the metallized regions, a bonding pad of a different material electrically connected to the device bonding pad through a barrier layer, and a protective layer overlying the edges of said passivation oxide layer in contact with the device to seal the edges of the protective layer and a seal formed at said windows whereby the device is protected against the environment without the necessity of a separate metal or ceramic housing.

Abstract: An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers, According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: An endcap reservoir for extending electromigration lifetime and preventing harmful void formation that causes electromigration failure in interconnect lines. When a current is introduced into an interconnect line the current can drag metal atoms from behind the current flow down the interconnect line, leaving behind voids. Voids are regions of the interconnect line that no longer contain metal atoms. If a void grows to the entire width of the interconnect line it stops the current from flowing in the interconnect line and forces the current to flow in the shunt layer. Current flowing in the shunt layer raises the resistance of the interconnect line and can cause the interconnect line to suffer electromigration failure. The present invention, an endcap reservoir, is an extension of the interconnect line added at the upstream end of the interconnect line.

Abstract: A semiconductor device with a high-density wiring structure, and a producing method for such device are provided. The semiconductor device has a substrate such as silicon, an insulation layer laminated on the substrate and having a groove or a hole, and a wiring of a conductive material formed in the groove or hole in the insulation layer. The wiring is formed by depositing a conductive material such as aluminum or an aluminum alloy in the groove or hole of the insulation layer by a CVD method utilizing alkylaluminum hydride gas and hydrogen. The groove or hole can be formed by an ordinary patterning method combined with etching.

Abstract: An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings.

Abstract: A semiconductor device that includes a wiring line formed from an electrode wiring layer which uses, as an electrode material, an Al alloy containing Cu, wherein wiring line having a size smaller than a crystal grain diameter has a Cu concentration of 0.05 to 0.3 wt %, and a wiring line having a size larger than a crystal grain diameter has a Cu concentration of 0.5 to 10 wt %.

Abstract: A semiconductor device is disclosed which uses an embedded pillar 38 to prevent damage (e.g. dishing, smearing, overetching) to damascene conductors during fabrication, particularly where such conductors are relatively large. The device comprises an insulating layer 22 formed on a substrate 20 and having a substantially planar upper surface with a plurality of channels 26, 34 formed therein. Channel 34 may be described as comprised of contiguous narrow channel segments (including right segment 40, top segment 41, and left segment 42) enclosing pillar 38, which has a top surface substantially coplanar with the upper surface of layer 22. In one embodiment, pillar 38 is formed integrally as part of layer 22. In alternative embodiments, pillar 38 may be formed from an additional insulating or conducting layer.

Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via), a reactive spacer formed on the sidewall of the opening or a reactive layer formed on the sidewall and on the bottom surface of the opening and a first conductive layer formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer is formed on the sidewall of the opening, when the first conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer improves the reflow of the first conductive layer during a heat-treating step for filling the opening at a high temperature below a melting temperature. Thus, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 .mu.m in size and having an aspect ratio greater than 1.

Abstract: The invention provides an interconnect line which comprises a metallization layer and a plurality of transverse diffusion barriers spaced within said metallization layer. The transverse diffusion barriers separate the length of metallization of the line into discrete sections, such that each section is only 20-50 microns in length. The diffusion barriers reduce electromigration and metal creep within the metal line, each of which can cause failure of the line. The invention further provides such an interconnect line formed within an insulator layer, for use in multi-level interconnect structures.

Abstract: A method for forming an interconnect film (of aluminum or aluminum alloy) by high-temperature sputtering such that the resulting film has a flat surface. The flat surface is desirable for the multilayer interconnect structure, relieves the resist film from halation at the time of exposure, and makes the interconnect immune to electromigration.An interconnect for semiconductor devices which is fabricated from an underlying film, with crystals therein orienting in the direction perpendicular to the substrate surface, and an interconnect film formed on the underlying film, with crystals therein orienting in alignment with the orientation of crystals in the underlying film and in the direction perpendicular to the substrate surface. The underlying film may be a titanium film with its (002), (001), or (011) crystal plane orienting in the direction perpendicular to the substrate surface.

Abstract: A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.

Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plus is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.

Abstract: A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.

Abstract: An interconnect structure and method for an integrated circuit chip for resisting electromigration is described incorporating patterned interconnect layers of Al or Al-Cu and interlayer contact regions or studs of Al.sub.2 Cu between patterned interconnect layers. The invention overcomes the problem of electromigration at high current density in the interconnect structure by providing a continuous path for Cu and/or Al atoms to move in the interconnect structure.

Abstract: There is disclosed a leadframe for electrically interconnecting a semiconductor device to external circuitry. The leadframe has an electrically conductive substrate that is coated with an oxidation resistant external layer. An intervening layer is disposed between a portion of the substrate and the external layer. The intervening layer is absent from the outer lead ends of the leadframe. Subsequent removal of the external layer from the outer lead ends enables a solder to directly contact the leadframe substrate.

Abstract: A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the second side of the wafer such that a portion of the first layer becomes exposed in the trench. A second layer having a second material is formed over the second side of the wafer such that a portion of the second layer contacts the portion of the first layer exposed in the trench. The wafer is separated through the trench. The trench may be formed by sawing the second side of the wafer in an area where the trench is to be formed. The wafer may then be etched such that the trench is formed.

Abstract: A semiconductor device which includes device bonding pads exposed through oxide windows formed in a passivation oxide layer providing electrical connections to the metallized regions, a bonding pad of a different material electrically connected to the device bonding pad through a barrier layer, and a protective layer overlying the edges of said passivation oxide layer in contact with the device to seal the edges of the protective layer and a seal formed at said windows whereby the device is protected against the environment without the necessity of a separate metal or ceramic housing.

Abstract: An electrical ceramic oxide capacitor utilizable in an integrated circuit memory device, and a method for making same is presented. A transistor is fabricated on a semiconductor substrate according to conventional techniques. A diffusion barrier is deposited over the transistor to protect it from subsequent process steps. Metal contacts are formed to contact the active transistor regions in the substrate, and additional barriers are formed to insulate the metal contacts. In a vertical embodiment, the barriers above the metal contacts can serve as bottom electrodes for the capacitor. In a lateral embodiment, the barriers on the side of the metal contacts serve as electrodes for the capacitor. Electrical ceramic oxide material is deposited between the electrode plates.

Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed by means of collimated sputter deposition in the antifuse cell opening to form a layer of uniform thickness existing only within the antifuse cell opening in order to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer and optionally formed by collimated sputter deposition, and a top electrode disposed over the second barrier metal layer.

Abstract: A semiconductor device comprises a capacitor consisting of an Al region formed on a semiconductor substrate, an Al oxide film formed on a surface of said Al region, and electrodes opposed to said Al region with interposition of said Al oxide film.

Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed in the antifuse cell opening to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer, and a top electrode disposed over the second barrier metal layer.

Abstract: A particular layout (38) of transistors along a continuous conductor line (54), such as the transistors in a CMOS inverter, has been found which reduces breaks or voids in the conductor line due to electromigration of the conductor atoms from predominantly unidirectional current flows. The conductor line may be a metal line. By alternating the two types of transistors, p- and n-type (40, 41, 46 & 47), along the length of the metal line, almost the entire length of the line can be changed to one with bidirectional current flow which significantly reduces the mean-time-to-failure for electromigration-related damage. The layout arrangement will find greater advantage for large transistors, long metal lines, relatively large unidirectional current flows and devices that run at high frequency, such as clock drivers.

Abstract: A contact and interconnect structure for a semiconductor integrated circuit includes a thin layer of refractory metal on a contact surface of the substrate through an opening in an overlying insulation layer with boron ions implanted into the substrate through the layer of refractory metal and the contact surface to ensure a uniform ohmic contact. An interconnect structure is then formed on the insulation layer and on the thin layer of refractory metal including a first layer of a refractory metal nitride on the insulation layer, a second layer of refractory metal on the first layer of refractory metal nitride, and a second layer of refractory metal nitride on the second layer of refractory metal.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.

Abstract: Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA.

Abstract: Semiconductor devices having improved electromigration resistance in their connections through dielectric layers are described. Where a conductive metal line overlies a dielectric layer and makes contact to a lower conductive structure through the dielectric layer by virtue of a conductive member, such as a tungsten plug or metal contact, the conductive metal line is provided with an end portion not otherwise connected to a conductive structure. The end portion serves as a reservoir of extra conductive material supplying the conductive metal line as the line is depleted through stress migration and/or electromigration.

Abstract: The present invention relates to a semiconductor device which has a wiring system including a wiring formed by completely surrounding a periphery of isolation films with a metal conductor as a main wiring material as viewed in a cross sectional profile and a contact opening and a through hole opening where the main wiring material is buried and a manufacturing method thereof.