Abstract: A semiconductor device capable of the area reduction of a resistor. A semiconductor substrate having a first conductive region is prepared. A dielectric layer is formed to cover the first conductive region. The dielectric layer has a contact hole formed to vertically penetrate the dielectric layer. The first conductive region is exposed from the dielectric layer in the contact hole. A semiconductor plug is formed to fill the contact hole with a material of the plug. The plug is doped with an impurity. The bottom of the plug is contacted with the first conductive region. A second conductive region is selectively formed to cover the semiconductor plug. The second conductive region is contacted with the top of the semiconductor plug. The semiconductor plug has a resistance. The semiconductor plug and the second conductive region has a contact resistance.

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: In a method of manufacturing a semiconductor device, a titanium silicide layer is formed on a region of a diffusion layer formed in a semiconductor substrate. A silicon nitride film functioning as an etching stopper is formed on the semiconductor substrate. The silicon nitride film covers the layer. An interlayered insulating film is formed on the silicon nitride film. A barrier metal of Tin/Ti is formed in a contact hole, which is formed in the interlayered insulating film. The contact holes is opened toward the diffusion layer. A conductive film comprising a Ti—Si—N based alloy is formed between a metal wiring and the diffusion layer. The conductive film is formed by reacting the silicon nitride film with titanium contained in the titanium silicide layer or the barrier metal. With these manufacturing features, the manufacturing process is not increased and the manufacturing cost can be reduced.

Abstract: An electrode substrate comprises a backing substrate carrying thereon a metal electrode layer and/or a recording layer, the layer or layers having a smooth surface area with a surface roughness of less than 1 nm by more than 1 &mgr;m2. The smooth surface of the metal electrode layer and/or the recording layer is formed by firstly forming the layer on another substrate having a corresponding smooth surface and then peeling another substrate off the layer after the layer is bonded to the surface of the backing substrate, whereby the smooth surface profile of another substrate is transferred to the surface of the layer formed on the backing substrate.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.

Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.

Abstract: The present invention is directed to a method for forming semiconductor devices and semiconductor device precursors having gradual slope contacts. The method for forming a semiconductor precursor includes the steps of: forming a layer of conductive material in a first layer; forming a layer of a hard mask material onto at least a portion of the first layer; etching the layer of hard mask material to expose a portion of the first layer; forming facets on the layer of hard mask material; and forming a via in the first layer such that the via extends through the first layer to expose at least a portion of the layer of conductive material.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A copper interconnect structure is formed in a semiconductor device using self-aligned copper or tungsten via pillars to connect upper and lower copper interconnect layers separated by a dielectric. The lower copper interconnect layer is formed on an underlying layer. The via pillars are formed on the lower copper interconnect layer. The copper upper interconnect layer is formed to make electrical contact to exposed upper surfaces of the via pillars.

Abstract: The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact.

Abstract: Disclosed is a low cost contact and interconnect layer and method for fabricating the same. A contact via is opened within an insulating layer, exposing a circuit node (e.g., transistor active area within a semiconductor substrate). The via is filled with a chemical vapor deposited (CVD) titanium silicide layer, forming electrical contact with the circuit node. The silicide layer may simultaneously form the interconnect layer for one embodiment. In other embodiments, the interconnect layer may comprise a metal strap over the titanium silicide layer, or a metal layer over an etched-back titanium silicide plug in the contact via. For any of these embodiments, the contact via may be opened after the formation of interconnect trenches, the via extending from the bottom of a trench to the circuit node. CVD provides good step coverage of the via within the trench, despite the higher aspect ratio. The interconnect layer is deposited and etched back, such that the interconnect lines are defined by the trenches.

Abstract: A semiconductor memory device includes a floating gate, a control gate, source and drain regions, a lightly doped region of the second conductivity type, and a silicide layer. The floating gate is formed on a semiconductor substrate of the first conductivity type via a gate insulating film. The control gate is formed on the floating gate via an insulating film. The source and drain regions are formed by diffusing an impurity of the second conductivity type in the surface of the semiconductor substrate on the two sides of the floating gate. The lightly doped region is formed with a surface exposed at a position distant from the floating gate in at least the source region. The lightly doped region has an impurity dose lower than that of the source region. The silicide layer is formed on the exposed surface of the lightly doped region.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a layer of nitridated cobalt on a surface including silicon. A film cap including titanium is formed over the layer of cobalt and a thermal treatment is performed to form cobalt silicide from the layer of cobalt and the silicon. Further, a layer of cobalt or nickel may be formed over a titanium film on a surface including silicon. The titanium film is formed in an atmosphere including at least one of nitrogen and oxygen and a thermal treatment is performed for reversal and silicidation of the titanium film and the layer of cobalt or nickel to form cobalt silicide or cobalt nickel. The methods may be used for silicidation of a contact area, in forming a polycide line, or in use for other metal silicidation applications.

Abstract: A polycide wiring layer constituted by a polysilicon film and a silicide film is used as a bit line of a DRAM. When a memory cell region having an n-type impurity diffusion layer and a peripheral circuit region having a p-type impurity diffusion layer are to be electrically connected through the polysilicon film, a diffusion prevention film consisting of TiSiN or WSiN is formed as an underlying film of the polysilicon film. With this diffusion prevention film, interdiffusion between the n- and p-type impurity diffusion layers can be prevented. In addition, heat resistance at 900.degree. C. or more can be obtained in processes after formation of the diffusion prevention film.

Abstract: A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

Abstract: A lead structure is provided in a semiconductor device, having a body of a lead having at least a part of which is in contact with an adhesive which bonds with an insulation tape, and a protection layer selectively provided on the body of the lead so that the protection layer coats at least the part of the body in contact with the adhesive to completely isolate the body of the lead from the adhesive, to prevent an ion migration of a material of the body and also to prevent leakage of currents from and into the body of the lead.

Abstract: A thin-film microstructure sensor includes a substrate having an insulation layer. A thin-film platinum temperature-sensitive resistor is provided on the insulation layer of the substrate, the thin-film platinum temperature-sensitive resistor comprising a platinum layer, the platinum layer having a maximum crystal grain size above a reference grain size of 800 .ANG.. The thin-film platinum temperature-sensitive resistor is formed by a sputtering process to provide a temperature coefficient of resistance TCR above a reference TCR level of 3200 ppm.

Abstract: A dual damascene process using selective tungsten chemical vapor deposition is provided for forming composite structures for local interconnects comprising line trenches with contact holes, and composite structures for intermetal interconnects comprising line trenches with via holes. It is shown that by forming a seed layer in judiciously selected portions of the dual damascene structure and depositing tungsten selectively in one step, contact holes and via holes can be formed free of voids and key-holes.

Abstract: The semiconductor device manufacturing method includes the step of forming a second tungsten film on a first tungsten film, which is formed by using a reduction gas not-containing diborane, by using a gas containing the diborane, or forming the second tungsten film on the first tungsten film after the first tungsten film has been exposed to the gas containing the diborane.

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a shared contact. A gate oxide layer is firstly formed on a semiconductor substrate, and a polysilicon layer is then formed on the gate oxide layer. A dielectric spacer abuts surface of the polysilicon layer of the SRAM except on a top surface of the expect on a top surface of the polysilicon layer of the SRAM. Moreover, first ions of a first conductive type are implanted between the substrate. And second ions of the first conductive type are implanted into substrate to form a source/drain region of a first gate, and a second gate without the source/drain region using the dielectric spacers as a mask. The SRAM has at least three silicidation regions abutting top surface of the source/drain region, and the first and second gate, and the side wall second gate with no space is also covered a silicidation region. Finally, an inter-layer dielectric (ILD) is deposited over the substrate.

Abstract: Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon may be amorphous silicon in which case the deposition temperature can be as low as 580.degree. C. If polysilicon is deposited, the deposition temperature has to be at least 620.degree. C.

Abstract: A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by providing a plurality of refractory metal atoms and a plurality of silicon atoms in the processing chamber. The atoms are ionized by applying a first bias to the atoms to form a plasma. The substrate is then biased by a first stage bias followed by a second stage bias to accelerate the plasma to the substrate to form the copper barrier layer, where the first stage bias is less than the second stage bias. The copper-containing metal is then deposited on the copper barrier layer over the insulating layer and in the opening. The present invention further includes a semiconductor device formed by the above method.

Abstract: This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG..

Abstract: Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si--Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

Abstract: A method of forming a multi-layered interconnect structure is provided. A first conductive pattern is formed over an insulation layer. A first dielectric material is deposited over the first conductive pattern, and plugs are formed in the first dielectric material. A second conductive pattern is formed over the first dielectric material and plugs so as to form the multi-layered interconnect structure in part. Then, the first dielectric material is stripped away to leave the multi-layered interconnect structure exposed to air. A thin layer of second dielectric material is deposited so as to coat at least a portion of the interconnect structure. Next, a thin layer of metal is deposited so as to coat the at least a portion of the interconnect structure coated with the thin layer of second dielectric material. A third dielectric material is deposited over the interconnect structure to replace the stripped away first dielectric material.

Abstract: In a semiconductor device such as a thin film transistor a semiconductor region is formed and an insulating film is formed on the semiconductor region to have a contact hole extending to the semiconductor region. An electrically conductive metal layer is formed of aluminum to fill the contact hole. An electrically conductive protection layer is formed on the metal layer to prevent oxidation of the metal layer during manufacturing of the semiconductor device. Material of the protection layer is more difficult to be oxidized than aluminum. A transparent electrode is formed on the protection layer such that the electrode is electrically connected to the semiconductor region. The protection layer may be formed of titanium or a laminate layer of a titanium layer and a titanium nitride layer.

Abstract: In a semiconductor chip for Si chip based liquid crystal having insulating films and interconnection layers formed on a semiconductor substrate, a thin interconnection layer made of TiN/Ti having strong erosion resistance is formed on an uppermost interlayer insulating film having a flat surface to substantially expose the thin uppermost interconnection layer to the surface of the chip, the uppermost insulating film is covered with a protection film made of p-SiN and a thin insulating film having a mirror-like flat surface is formed on the uppermost interconnection layer.

Abstract: A semiconductor device having a semiconductor substrate, an impurity diffused layer formed in a principal surface of the semiconductor substrate, a conductive member formed on the semiconductor substrate adjacent to the impurity diffused layer and having a sloped surface inclined to the principal surface of the semiconductor substrate, an insulator film deposited to cover the impurity diffused layer and the conductive member, and a common contact hole formed through the insulator film to extend over a surface of the impurity diffused layer and the sloped surface of the conductive member.

Abstract: A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.

Abstract: A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer.

Abstract: In a metal alloy formed by first and second metal members for a semiconductor device, the first metal member is composed of approximately 0.1 to 10 wt. percent Cu with the residual amount being substantially composed of Al, and the second metal member is composed of approximately 0.5 to 5 wt. percent with the residual amount being substantially composed of Au.

Abstract: A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction of a diode in a single crystalline substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with most of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and a more stable and conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.

Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature within the reaction chamber at from about 0.degree. C. to less than 300.degree. C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.

Abstract: An iridium oxide local interconnect method for a ferroelectric memory cell includes the steps of forming a conductive layer that extends from a source/drain contact of the transistor proximate to an electrode contact of the ferroelectric capacitor and forming an iridium oxide local interconnect extending from the source/drain contact of the transistor to the electrode contact of the ferroelectric capacitor. The conductive layer is laterally terminated not less than one-half micron from the electrode contact of the ferroelectric capacitor. The conductive layer can include an upper iridium layer and a bottom titanium nitride layer, or can include a single layer of completely reacted titanium nitride. After the local interconnect is formed a top oxide layer is deposited. A late recovery anneal is then performed in oxygen at an elevated temperature to rejuvenate the electrical characteristics of the ferroelectric capacitor. Finally, a bit line contact is opened and metalized.

Abstract: Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over-simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations.

Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.

Abstract: By treating the silicon-oxide insulating layer of a semiconductor device with an aqueous metal-salt solution of a metal of an ion radius of less than 0.110 nm, for example, Sc, La or Zr, before a platinum electrode layer is provided on the insulating layer, the platinum layer shows excellent adhesive properties.

Abstract: A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.

Abstract: A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

Abstract: A low-resistance metal-semiconductor contact for use in integrated circuits includes a titanium silicide layer overlaying a semiconductor body. The top surface of the titanium silicide layer is a combination of silicides and titanium nitride formed by exposing the top surface to a nitrogen plasma. This combination surface is covered by a layer of titanium nitride, which is in turn covered by a layer of conductive metal, such as tungsten.

Abstract: The invention relates to a process of forming a semiconductor structure. The process includes patterning a conductive layer with a top surface and opposing sides over an area of a semiconductor substrate, depositing a dielectric layer over the conductive layer, and etching the dielectric layer to form spacer portions adjacent the sides of the conductive layer and to expose the top surface and a portion of the conductive layer. The process may be used to form salicides wherein the thickness of the silicide layer of the conductive layer is greater than the thickness of the silicide layer in the diffusion region of a device. The invention also relates to a semiconductor device that includes a conductive layer with opposing side portions over an active area of a semiconductor substrate and a dielectric spacer adjacent to less than the entire portion of a side portion of the conductive layer.

Abstract: A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the conductive insulated gate layer is lowered.

Abstract: A semiconductor device in which mutual diffusion of doped impurities occurring through an upper silicide electrode layer is prevented. A silicide electrode layer is doped with both the same degree of p-type impurities as the concentration of p-type impurities of the lower gate electrode layer and the same degree of n-type impurities as the concentration of n-type impurities. As a result, the concentration of doped impurities of the gate electrode layer is balanced at the two sides of the interface of the pMOS side and nMOS side. Therefore, heat diffusion caused by subsequent heat treatment is prevented and the problem of mutual diffusion can be solved. The present invention is also suitable for the SALICIDE process.

Abstract: A semiconductor device comprising a semiconductor substrate and a capacitor formed on the semiconductor substrate, wherein the capacitor is formed of a multilayer comprising a first electrode disposed close to the semiconductor substrate, a second electrode disposed remote from the semiconductor substrate and a dielectric film formed of a metal oxide and interposed between the first electrode and the second electrode, and at least either one of the first and second electrodes contains oxygen and is constituted by an element selected from either one of Group 7A and Group 8 elements belonging to either one of the fifth and sixth periods of Periodic Table, the content of oxygen being in a range of 0.004 to 5 atom.%.

Abstract: A multi-level wiring structure having: a first wiring formed on an insulating surface, the first wiring containing refractory metal as a main composition thereof; an inter-level insulating film formed to cover the first wiring and having a contact hole at a predetermined region of the first wiring; a second wiring formed over said inter-level insulating film to be electrically connected to an upper surface of the first wiring at a region of the contact hole, the second wiring containing Al as a main composition thereof; and a barrier layer disposed at an interface where the first and second wirings are electrically connected, the barrier layer being made of a material different from, and substantially not reacting with, both Al and the refractory metal constituting the main composition of the first wiring.

Abstract: A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole.

Abstract: A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the length of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of a polysilicon and/or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

Abstract: A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of a high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on at least the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by selective Al--CVD, and a metal wiring formed on the insulating film. The metal wiring is electrically connected to the diffusion region by the plug, the anti-diffusion film and the silicide film. The anti-diffusion film is formed by nitriding the surface of the silicide film such that only the grain boundaries of the grains of the silicide film are nitrided.