Abstract: A method of making a stoichiometric monazite (LaPO4) composition or a mixture of LaPO4 and LaP3O9 composition, as defined herein. Also disclosed is a method of joining or sealing materials with the compositions, as defined herein.

Abstract: A memory and a method for manufacturing the same are provided. The memory includes: a substrate including an isolation structure and an active area between adjacent isolation structures; a first gate structure, the first gate structure locates in a first groove of the isolation structure, includes a first gate filled in the first groove, and the first gate includes a first conductive layer filled at the bottom of the first groove and a second conductive layer, the second conductive layer locates above the first conductive layer, and the work function of the material of the first conductive layer is greater than that of the material of the second conductive layer; a second gate structure, located in the second groove of the active area, includes a second gate filled in the second groove, and the material of the second gate is the same as that of the second conductive layer.

Abstract: A method for manufacturing a dynamic random access memory includes: forming a buried bit line in a substrate; forming a plurality of buried word lines in the substrate, wherein the bottom surfaces of the buried word lines are higher than the top surface of the buried bit line; forming a bit line contact structure on the buried bit line; forming a through hole passing through the bit line contact structure, wherein the bit line contact structure is not in direct contact with the buried bit line, and the material of the bit line contact structure is different from the material of the buried bit line; forming a conductive plug between the bit line contact structure and the buried bit line; and forming a capacitor structure on the substrate.

Abstract: A semiconductor package includes a first redistribution layer. A plurality of posts is disposed on the first redistribution layer. A semiconductor chip is disposed on the first redistribution layer between the plurality of posts. A second redistribution layer is formed on the plurality of posts and the semiconductor chip. A first memory stack is disposed on the second redistribution layer. A height of each of the plurality of posts extends from an upper surface of the first redistribution layer to a lower surface of the second redistribution layer.

Abstract: A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.

Abstract: A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first substrate, a first dielectric, and a first via structure. The first via structure includes a first contact via and first metal impurities doped in the first contact via. The second semiconductor structure includes a second substrate, a second dielectric layer, and a second via structure. The second via structure includes a second contact via and second metal impurities doped in the second contact via. The method further includes bonding the first semiconductor structure with the second semiconductor and forming a self-barrier layer by an alloying process. The self-barrier layer is formed by a multi-component oxide corresponding to the first and second metal impurities.

Abstract: First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Abstract: The present invention relates to a conductive paste composition for solar photovoltaic cells comprising metal particles dispersed in a suitable carrier therefor, wherein said carrier comprises a solvent and a resin, and wherein at least a portion of said metal particles are characterized by having a ? value, as defined by X-ray diffraction<0.0020, having at least 50% degree of crystallinity, and being anisotropic with respect to crystallographic direction.

Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

Abstract: A semiconductor device includes a first substrate, a through substrate via, a second substrate, and a bonding structure. The first substrate includes a first dielectric material, and the first dielectric material includes a first conductive pad embedded therein. The through substrate via is formed in the first substrate. The second substrate includes a second dielectric material, the second dielectric material includes a second conductive pad embedded therein, the first dielectric material is different from the second dielectric material, the second conductive pad has a first height, the second dielectric material has a second height, and the first height is less than the second height. The bonding structure is formed between the first substrate and the second substrate, wherein the bonding structure includes the first conductive pad bonded to the second conductive pad and the first dielectric material bonded to the second dielectric material.

Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.

Abstract: An encoder includes a scale unit having a substrate configured of a metal material and in which a pattern is formed on a first surface of the substrate and a passive state member is formed on a second surface different from the first surface in the substrate, and a detection unit that is configured to move relative to the scale unit and detects the pattern.

Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.

Abstract: A micromechanical pressure sensor device and a corresponding manufacturing method. The micromechanical pressure sensor device includes an ASIC wafer, a rewiring system, formed on the front side, which includes a plurality of strip conductor levels and insulating layers situated in between, a structured insulating layer formed above an uppermost strip conductor level, a micromechanical functional layer formed on the insulating layer and which includes a diaphragm area, which may be acted on by pressure, above a recess in the insulating layer as a first pressure detection electrode, and a second pressure detection electrode on the uppermost strip conductor level, formed in the recess at a distance from the diaphragm area and is electrically insulated from the diaphragm area. The diaphragm area is electrically connected to the uppermost strip conductor level by one or multiple first contact plugs which are led through the diaphragm area and through the insulating layer.

Abstract: A transflective liquid crystal display includes: a first substrate divided into a pixel part and first and second pad parts; a gate electrode and a gate line formed at the pixel part of the first substrate; a first insulation film formed on the first substrate; an active pattern formed as an island at an upper portion of the gate electrode and having a width smaller than the gate electrode; an ohmic-contact layer and a barrier metal layer formed on the first substrate and on source and drain regions of the active pattern; source and drain electrodes formed at the pixel part of the first substrate and electrically connected with the source and drain regions of the active pattern via the ohmic-contact layer and the barrier metal layer; a data line formed at the pixel part of the first substrate and crossing the gate line to define a pixel region including a reflective portion and a transmissive portion; a pixel electrode formed at the transmissive portion of the pixel region and electrically connected with the

Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C.

Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.

Abstract: A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

Abstract: A pressure sensor using the MEMS device comprises an airtight ring surrounding a chamber defined by the first substrate and the second substrate. The airtight ring extends from the upper surface of the second substrate to the surface between the first substrate and the second substrate and further breaks out the surface. The pressure sensor utilizes the airtight ring to retain the airtightness of the chamber. The manufacture method of the pressure sensor is also disclosed.

Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.

Abstract: An electronic device according to an aspect of the invention include: a substrate; an underlayer having an opening and being formed on the substrate; a functional element provided on the underlayer; and a surrounding wall forming a cavity that accommodates the functional element, at least a part of the surrounding wall being disposed in the opening.

Abstract: The invention provides a manufacturing method of a MEMS device, which includes: providing an integrated circuit device including a substrate and an electrical structure on the substrate, the electrical structure includes at least one sensing region and at least one first connection section; providing a structure layer, and forming at least one second connection section on the structure layer; bonding the at least one first connection section and the at least one second connection section; etching the structure layer for forming at least one movable structure, the movable structure being located at a position corresponding to a position of the sensing region, and the movable structure being connected to the at least one first connection section via the at least one second connection section; and thereafter, providing a cap to cover the movable structure and the sensing region, wherein the movable structure is not directly connected to the cap.

Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.

Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.

Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.

Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, where the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, where the second layer is less than about 2 micron thick, where the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, where the connection path includes at least one through-layer via, where the at least one through-layer via is formed through and in direct contact with a source or drain of at least one of the second transistors.

Abstract: A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g., <50 ?m). In implementations, the wafer-level package device that employs the techniques of the present disclosure includes an active device wafer, a thin integrated circuit chip, an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip, a redistribution layer structure, and at least one solder bump for providing electrical interconnectivity. Once the wafer is singulated into semiconductor devices, each semiconductor device including the embedded thin integrated circuit chip may be mounted to a printed circuit board.

Abstract: An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.

Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Abstract: An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.

Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.

Abstract: The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.

Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.

Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.

Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

Abstract: Interconnects for semiconductors formed of materials that exhibit crystallographic anisotropy of the resistivity size effect such that line resistivity in one crystallographic orientation becomes lower than the resistivity in the other directions and methods of fabrication and use thereof are described. A wire having a dimension that results in an increase in the electrical resistivity of the wire can be formed of a material with a conductive anisotropy due to crystallographic orientation relative to the direction of current flow that minimizes the increase in the electrical resistivity as compared to the other orientations at that dimension.

Abstract: An interconnector line of thin film comprising 0.001 to 30 at % of at least one kind of a first element capable of constituting an intermetallic compound of aluminum and/or having a higher standard electrode potential than aluminum, for example, at least one kind of the first element selected from Y, Sc, La, Ce, Nd, Sm, Gd, Tb, Dy, Er, Th, Sr, Ti, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Tc, Re, Fe, Co, Ni, Pd, Ir, Pt, Cu, Ag, Au, Cd, Si, Pb and B; and one kind of a second element selected from C, O, N and H in a proportion of 0.01 at ppm to 50 at % of the first element, with the balance comprising substantially Al. In addition to having low resistance, such an Al interconnector line of thin film can prevent the occurrence of hillocks and the electrochemical reaction with an ITO electrode. The interconnector line of thin film can be obtained by sputtering in a dust-free manner by using a sputter target having a similar composition.