Molybdenum, Tungsten, Or Titanium Or Their Silicides Patents (Class 257/770)
  • Patent number: 10361449
    Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Su
  • Patent number: 10234308
    Abstract: An encoder includes a scale unit having a substrate configured of a metal material and in which a pattern is formed on a first surface of the substrate and a passive state member is formed on a second surface different from the first surface in the substrate, and a detection unit that is configured to move relative to the scale unit and detects the pattern.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 19, 2019
    Assignee: NIKON CORPORATION
    Inventors: Shintaro Hikichi, Hideaki Sugiyama
  • Patent number: 10115582
    Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 30, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
  • Patent number: 10031038
    Abstract: A micromechanical pressure sensor device and a corresponding manufacturing method. The micromechanical pressure sensor device includes an ASIC wafer, a rewiring system, formed on the front side, which includes a plurality of strip conductor levels and insulating layers situated in between, a structured insulating layer formed above an uppermost strip conductor level, a micromechanical functional layer formed on the insulating layer and which includes a diaphragm area, which may be acted on by pressure, above a recess in the insulating layer as a first pressure detection electrode, and a second pressure detection electrode on the uppermost strip conductor level, formed in the recess at a distance from the diaphragm area and is electrically insulated from the diaphragm area. The diaphragm area is electrically connected to the uppermost strip conductor level by one or multiple first contact plugs which are led through the diaphragm area and through the insulating layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 24, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Johannes Classen
  • Patent number: 9857644
    Abstract: A transflective liquid crystal display includes: a first substrate divided into a pixel part and first and second pad parts; a gate electrode and a gate line formed at the pixel part of the first substrate; a first insulation film formed on the first substrate; an active pattern formed as an island at an upper portion of the gate electrode and having a width smaller than the gate electrode; an ohmic-contact layer and a barrier metal layer formed on the first substrate and on source and drain regions of the active pattern; source and drain electrodes formed at the pixel part of the first substrate and electrically connected with the source and drain regions of the active pattern via the ohmic-contact layer and the barrier metal layer; a data line formed at the pixel part of the first substrate and crossing the gate line to define a pixel region including a reflective portion and a transmissive portion; a pixel electrode formed at the transmissive portion of the pixel region and electrically connected with the
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 2, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Dong-Yung Kim, Byoung-Ho Lim
  • Patent number: 9831100
    Abstract: Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25° C. and 85° C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25° C. and 85° C.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: November 28, 2017
    Assignees: Intermolecular, Inc., International Business Machines
    Inventors: John Foster, Sean Lin, Muthumanickam Sankarapandian, Ruilong Xie
  • Patent number: 9799678
    Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Beom Kim, Je-Hyeong Park, Jae-Hyoung Youn, Jean-Ho Song, Jong-In Kim
  • Patent number: 9793230
    Abstract: A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 9653615
    Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chung-Hsun Lin, Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman
  • Patent number: 9598275
    Abstract: A pressure sensor using the MEMS device comprises an airtight ring surrounding a chamber defined by the first substrate and the second substrate. The airtight ring extends from the upper surface of the second substrate to the surface between the first substrate and the second substrate and further breaks out the surface. The pressure sensor utilizes the airtight ring to retain the airtightness of the chamber. The manufacture method of the pressure sensor is also disclosed.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: March 21, 2017
    Assignee: MIRAMEMS SENSING TECHNOLOGY CO., LTD
    Inventors: Yu-Hao Chien, Li-Tien Tseng
  • Patent number: 9508589
    Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 29, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Kern Rim, Zhongze Wang, Jeffrey Junhao Xu, Xiangdong Chen, Choh Fei Yeap
  • Patent number: 9490216
    Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Jin Moon, Tae-Seong Kim, Byung-Lyul Park, Jae-Hwa Park, Suk-Chul Bang
  • Patent number: 9190954
    Abstract: An electronic device according to an aspect of the invention include: a substrate; an underlayer having an opening and being formed on the substrate; a functional element provided on the underlayer; and a surrounding wall forming a cavity that accommodates the functional element, at least a part of the surrounding wall being disposed in the opening.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: November 17, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takahiko Yoshizawa
  • Patent number: 9073750
    Abstract: The invention provides a manufacturing method of a MEMS device, which includes: providing an integrated circuit device including a substrate and an electrical structure on the substrate, the electrical structure includes at least one sensing region and at least one first connection section; providing a structure layer, and forming at least one second connection section on the structure layer; bonding the at least one first connection section and the at least one second connection section; etching the structure layer for forming at least one movable structure, the movable structure being located at a position corresponding to a position of the sensing region, and the movable structure being connected to the at least one first connection section via the at least one second connection section; and thereafter, providing a cap to cover the movable structure and the sensing region, wherein the movable structure is not directly connected to the cap.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: July 7, 2015
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chiung-Cheng Lo, Kuan-Lin Chen
  • Patent number: 9059166
    Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
  • Publication number: 20150123280
    Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Shyam Surthi, Lars Heineck
  • Publication number: 20150115444
    Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Peter Brockhaus, Uwe Koeckritz
  • Publication number: 20150115453
    Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 30, 2015
    Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Huamao LIN, Pradeep YELEHANKA
  • Publication number: 20150108651
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 23, 2015
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 9013002
    Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: David James Spry
  • Patent number: 9000587
    Abstract: A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g., <50 ?m). In implementations, the wafer-level package device that employs the techniques of the present disclosure includes an active device wafer, a thin integrated circuit chip, an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip, a redistribution layer structure, and at least one solder bump for providing electrical interconnectivity. Once the wafer is singulated into semiconductor devices, each semiconductor device including the embedded thin integrated circuit chip may be mounted to a printed circuit board.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 7, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Amit S. Kelkar, Vivek S. Sridharan
  • Patent number: 9000557
    Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, where the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, where the second layer is less than about 2 micron thick, where the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, where the connection path includes at least one through-layer via, where the at least one through-layer via is formed through and in direct contact with a source or drain of at least one of the second transistors.
    Type: Grant
    Filed: March 17, 2012
    Date of Patent: April 7, 2015
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20150091174
    Abstract: An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: James S. Clarke, Anthony C. Schmitz, Richard E. Schenker
  • Patent number: 8994176
    Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
  • Publication number: 20150076683
    Abstract: An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 19, 2015
    Applicant: HANA MICRON CO., LTD.
    Inventors: Jae-Sung Lim, Ju-Hyung Kim, Jin-Wook Jeong, Hyun-Joo Kim, Hyouk Lee
  • Patent number: 8975708
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Shiang Yang Ong, Elgin Quek
  • Publication number: 20150048506
    Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi-Hsuan Hsiao, Yen-Hao Shih, Shih-Hung Chen, Hang-Ting Lue
  • Patent number: 8941123
    Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Cyril Cabral, Jr., Anirban Basu, Jr.
  • Publication number: 20150001727
    Abstract: The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Chia-Yen LEE, Hsin-Chang TSAI, Peng-Hsin LEE
  • Publication number: 20150004805
    Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 1, 2015
    Inventors: Thomas R. Omstead, Cole S. Franklin
  • Patent number: 8896120
    Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
  • Publication number: 20140327062
    Abstract: An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.
    Type: Application
    Filed: November 6, 2013
    Publication date: November 6, 2014
    Inventors: Ki-Yeon PARK, Hyun-Jun Kim, Se-Hyoung Ahn, Young-Geun Park, Ki-Vin Im
  • Publication number: 20140319447
    Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.
    Type: Application
    Filed: July 3, 2014
    Publication date: October 30, 2014
    Inventors: Andrea Redaelli, Cinzia Perrone
  • Patent number: 8872341
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Dallmann, Heike Rosslau, Norbert Urbansky, Scott Wallace
  • Patent number: 8847412
    Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 30, 2014
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Simon McElrea
  • Publication number: 20140264886
    Abstract: A spacer transfer process produces sub-lithographic patterns of conductive lines in a semiconductor die. A dielectric then a conductive material are deposited onto a face of a semiconductor substrate. A sacrificial dielectric is deposited on the conductive material and portions thereof are removed to form at least one trench comprising walls and a bottom exposing the conductive material. A hard mask is deposited over the sacrificial dielectric including the walls and bottom of the trench. Then the hard mask is removed therefrom except from the walls of the trench. Thereafter, the remaining sacrificial dielectric is removed leaving only the hard mask from the walls of the trench. Then all conductive material not protected by the remaining hard mask is removed. Thereafter, the hard mask is removed exposing a sub-lithographic pattern of fence conductors wherein portions thereof are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Microchip Technology Incorporated
    Inventor: Paul Fest
  • Publication number: 20140264887
    Abstract: Interconnects for semiconductors formed of materials that exhibit crystallographic anisotropy of the resistivity size effect such that line resistivity in one crystallographic orientation becomes lower than the resistivity in the other directions and methods of fabrication and use thereof are described. A wire having a dimension that results in an increase in the electrical resistivity of the wire can be formed of a material with a conductive anisotropy due to crystallographic orientation relative to the direction of current flow that minimizes the increase in the electrical resistivity as compared to the other orientations at that dimension.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Inventors: KATAYUN BARMAK VAZIRI, KEVIN COFFEY, DOOHO CHOI
  • Patent number: 8816407
    Abstract: Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-yeon Kim, Tae-hong Min, Yeong-kwon Ko, Tae-je Cho
  • Patent number: 8816503
    Abstract: A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten Ahrens, Johannes Baumgartl, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20140210058
    Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, SK hynix Inc.
    Inventors: Jong Ho LEE, Kyung Do KIM
  • Patent number: 8786091
    Abstract: A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. In one embodiment a first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadayoshi Muta
  • Patent number: 8772939
    Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8759213
    Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Francois Pagette, Anna W. Topol
  • Publication number: 20140167253
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 8754529
    Abstract: A MEMS device comprises a substrate for manufacturing a moving MEMS component is divided into two electrically isolated conducting regions to allow the moving MEMS component and a circuit disposed on its surface to connect electrically with another substrate below respectively through their corresponding conducting regions, thereby the electrical conducting paths and manufacturing process can be simplified.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: June 17, 2014
    Assignee: Miradia, Inc.
    Inventors: Yu-Hao Chien, Hua-Shu Wu, Shih-Yung Chung, Li-Tien Tseng, Yu-Te Yeh
  • Publication number: 20140159242
    Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.
    Type: Application
    Filed: January 4, 2013
    Publication date: June 12, 2014
    Applicant: International Business Machines Corporation
    Inventors: Cyril Cabral, JR., Sebastian U. Engelmann, Benjamin L. Fletcher, Michael S. Gordon, Eric A. Joseph
  • Publication number: 20140159243
    Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Soon-Kang Huang, Han-Hsin Kuo, Chi-Ming Yang, Shwang-Ming Jeng, Chin-Hsiang Lin
  • Patent number: 8736057
    Abstract: A substrate having, on a base material, a barrier film for preventing copper diffusion containing one or more metal elements selected from tungsten, molybdenum and niobium, a metal element having a catalytic function in electroless plating such as platinum, gold, silver and palladium, and nitrogen contained in the form of a nitride of the aforementioned one or more metal elements selected from tungsten, molybdenum and niobium. The barrier film for preventing copper diffusion is manufactured by sputtering in a nitrogen atmosphere using a target containing one or more metal elements selected from tungsten, molybdenum and niobium and the aforementioned metal element having a catalytic function in electroless plating.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: May 27, 2014
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Junichi Ito, Atsushi Yabe, Junnosuke Sekiguchi, Toru Imori
  • Publication number: 20140131877
    Abstract: A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Patent number: RE45481
    Abstract: An interconnector line of thin film comprising 0.001 to 30 at % of at least one kind of a first element capable of constituting an intermetallic compound of aluminum and/or having a higher standard electrode potential than aluminum, for example, at least one kind of the first element selected from Y, Sc, La, Ce, Nd, Sm, Gd, Tb, Dy, Er, Th, Sr, Ti, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Tc, Re, Fe, Co, Ni, Pd, Ir, Pt, Cu, Ag, Au, Cd, Si, Pb and B; and one kind of a second element selected from C, O, N and H in a proportion of 0.01 at ppm to 50 at % of the first element, with the balance comprising substantially Al. In addition to having low resistance, such an Al interconnector line of thin film can prevent the occurrence of hillocks and the electrochemical reaction with an ITO electrode. The interconnector line of thin film can be obtained by sputtering in a dust-free manner by using a sputter target having a similar composition.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ishigami, Koichi Watanabe, Akihisa Nitta, Toshihiro Maki, Noriaki Yagi