Refractory Or Platinum Group Metal Or Alloy Or Silicide Thereof Patents (Class 257/768)
  • Patent number: 10170617
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES
    Inventors: Jiseok Kim, Hiroaki Niimi, Hoon Kim, Puneet Harischandra Suvarna, Steven Bentley, Jody A. Fronheiser
  • Patent number: 9553141
    Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jeong Yang, Soon-Wook Jung, Bong-Jin Kuh, Wan-Don Kim, Byung-Hong Chung, Yong-Suk Tak
  • Patent number: 9484362
    Abstract: A display substrate includes an active pattern, a gate electrode, a first insulation layer and a pixel electrode. The active pattern is disposed on a base substrate. The active pattern includes a metal oxide semiconductor. The gate electrode overlaps the active pattern. The first insulation layer covers the gate electrode and the active pattern, and a contact hole is defined in the first insulation layer. The pixel electrode is electrically connected to the active pattern via the contact hole penetrating the first insulation layer. A first angle defined by a bottom surface of the first insulation layer and a sidewall of the first insulation layer exposed by the contact hole is between about 30° and about 50°.
    Type: Grant
    Filed: April 27, 2014
    Date of Patent: November 1, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dae-Ho Kim, Hyun-Jae Na, Jae-Neung Kim, Yu-Gwang Jeong, Myoung-Geun Cha, Sang-Gab Kim
  • Patent number: 9425277
    Abstract: An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: August 23, 2016
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 9214528
    Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 15, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao
  • Publication number: 20150137275
    Abstract: The present invention relates to a method for decreasing the impedance of a titanium nitride element for use in an electrode component. The method comprises obtaining a titanium nitride element and hydrothermally treating the titanium nitride element by immersing the titanium nitride element in a liquid comprising water while heating said liquid.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 21, 2015
    Applicant: IMEC VZW
    Inventor: Silke Musa
  • Publication number: 20150115393
    Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
    Type: Application
    Filed: October 31, 2014
    Publication date: April 30, 2015
    Inventor: Hong Shen
  • Patent number: 9013002
    Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: David James Spry
  • Publication number: 20150097292
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Jun HE, Kevin J. FISCHER, Ying ZHOU, Peter K. MOON
  • Patent number: 8975708
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Shiang Yang Ong, Elgin Quek
  • Publication number: 20150028484
    Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.
    Type: Application
    Filed: August 21, 2014
    Publication date: January 29, 2015
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Wai-Kin Li, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8941123
    Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Cyril Cabral, Jr., Anirban Basu, Jr.
  • Publication number: 20140374911
    Abstract: The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer.
    Type: Application
    Filed: April 18, 2014
    Publication date: December 25, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xinpeng WANG, Chenglong ZHANG, Ruixuan HUANG
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8896136
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20140332965
    Abstract: An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second interconnects may have different aspect ratio and may have different line heights while being co-planar with each other. The second line of the second interconnect may abut or partially surround the first line of the first interconnect. The first interconnect includes a refractory metal material as the main conductor, whereas the second interconnect includes a lower resistivity material as its main conductor.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20140332759
    Abstract: According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 13, 2014
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Dirk Meinhold, Sven Schmidbauer, Markus Fischer, Norbert Urbansky
  • Publication number: 20140327062
    Abstract: An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.
    Type: Application
    Filed: November 6, 2013
    Publication date: November 6, 2014
    Inventors: Ki-Yeon PARK, Hyun-Jun Kim, Se-Hyoung Ahn, Young-Geun Park, Ki-Vin Im
  • Patent number: 8878175
    Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8835309
    Abstract: A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: David F. Hilscher, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 8796852
    Abstract: A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: August 5, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 8785320
    Abstract: A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Fenton R. McFeely
  • Publication number: 20140197540
    Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 17, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • Patent number: 8766445
    Abstract: A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Hisaka, Takahiro Nakamoto, Toshihiko Shiga, Koichiro Nishizawa
  • Patent number: 8759213
    Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Francois Pagette, Anna W. Topol
  • Publication number: 20140159242
    Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.
    Type: Application
    Filed: January 4, 2013
    Publication date: June 12, 2014
    Applicant: International Business Machines Corporation
    Inventors: Cyril Cabral, JR., Sebastian U. Engelmann, Benjamin L. Fletcher, Michael S. Gordon, Eric A. Joseph
  • Patent number: 8749057
    Abstract: Methods for forming structures to use in atomic force probing of a conductive feature embedded in a dielectric layer and structures for use in atomic force probing. An insulator layer is formed on the dielectric layer such that the conductive feature is covered. A contact hole penetrates from a top surface of the insulator layer through the insulator layer to the conductive feature. The contact hole is at least partially filled with a conductive stud that is in electrical contact with the conductive feature and exposed at the top surface of the insulator layer so as to define a structure. A probe tip of an atomic force probe tool is landed on a portion of the structure and used to electrically characterize a device structure connected with the conductive feature.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: David R. Goulet, Walter V. Lepuschenko
  • Publication number: 20140079954
    Abstract: A non-catalytic palladium precursor composition is disclosed, including a palladium salt and an organoamine, wherein the composition is substantially free of water. The composition permits the use of solution processing methods to form a palladium layer on a wide variety of substrates, including in a pattern to form circuitry or pathways for electronic devices.
    Type: Application
    Filed: October 16, 2013
    Publication date: March 20, 2014
    Applicant: Xerox Corporation
    Inventors: Yiliang Wu, Ping Liu
  • Publication number: 20140061930
    Abstract: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8648464
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Atsuko Sakata, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Patent number: 8648444
    Abstract: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Yu-Wen Liu
  • Patent number: 8643119
    Abstract: A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: February 4, 2014
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing LTD
    Inventors: Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo
  • Patent number: 8637937
    Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: January 28, 2014
    Assignee: Ultratech, Inc.
    Inventors: Paul Stephen Andry, Edmund Juris Sprogis, Cornelia Kang-I Tsang
  • Publication number: 20140021620
    Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.
    Type: Application
    Filed: January 11, 2013
    Publication date: January 23, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baik-woo LEE, Young-hun BYUN, Seong-woon BOOH, Chang-mo JEONG
  • Patent number: 8581404
    Abstract: A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: November 12, 2013
    Assignee: Megit Acquistion Corp.
    Inventors: Chiu-Ming Chou, Mou-Shiung Lin
  • Publication number: 20130234335
    Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Clemens Fitz, Jochen Poth, Kristin Schupke
  • Publication number: 20130228931
    Abstract: There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning.
    Type: Application
    Filed: April 12, 2013
    Publication date: September 5, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tadayoshi Muta
  • Publication number: 20130207271
    Abstract: There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.
    Type: Application
    Filed: January 31, 2013
    Publication date: August 15, 2013
    Applicant: SONY CORPORATION
    Inventor: SONY CORPORATION
  • Patent number: 8501623
    Abstract: A semiconductor device includes an electrode having a metal silicide layer and a metal alloy layer, and a data storage element formed on the electrode. The metal silicide layer has a concave surface to correspond to a convex surface of the metal alloy layer such that the concave surface of the metal silicide layer and the convex surface of the metal alloy layer form a curved boundary.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: August 6, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Gyuhwan Oh, Young-Lim Park, Soonoh Park, Dongho Ahn, Jinil Lee
  • Patent number: 8497580
    Abstract: An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Fenton R. McFeely
  • Patent number: 8466555
    Abstract: A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 18, 2013
    Assignee: Raytheon Company
    Inventors: Ram V. Chelakara, Thomas E. Kazior, Jeffrey R. LaRoche
  • Publication number: 20130147048
    Abstract: A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 13, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Samsung Electronics Co., Ltd.
  • Patent number: 8450204
    Abstract: A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Fenton R. McFeely
  • Patent number: 8378490
    Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Hsin-Kuei Lee, Ching-Hou Su
  • Patent number: 8349730
    Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsueh Shih, Shau-Lin Shue
  • Patent number: 8344438
    Abstract: The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: January 1, 2013
    Assignee: Qimonda AG
    Inventors: Uwe Schroeder, Stefan Jakschik, Johannes Heitmann, Tim Boescke, Annette Saenger
  • Publication number: 20120326318
    Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
    Type: Application
    Filed: September 10, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Lavoie, Francois Pagette, Anna W. Topol
  • Patent number: 8334574
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Keun Park
  • Patent number: 8330234
    Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 11, 2012
    Assignee: NEC Corporation
    Inventor: Takashi Hase
  • Publication number: 20120280397
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 8, 2012
    Inventors: Jung Geun KIM, Whee Won Cho, Eun Soo Kim