Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first groove and the first connection slot. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove. The connection metal layer covers the under bump metallurgy layer to form a third groove, wherein the under bump metallurgy layer covers a first coverage area of the first polymer block and a second coverage area of the second polymer block and reveals a first exposure area of the first polymer block and a second exposure area of the second polymer block.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

Abstract: There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Abstract: A power layout of an integrated circuit includes at least one power grid cell. Each power gird cell includes at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The at least one first power layer has conductive lines in at least two different directions. The at least one second power layer has conductive lines in at least two different directions.

Abstract: A lead pin for a package substrate includes a coupling pin, a head portion, and a flowing prevention portion. The coupling pin is to be inserted into a hole which is formed in an external substrate. The head portion is formed at one end of the coupling pin. The flowing prevention portion is formed on the top surface of the head portion and prevents a solder paste from flowing toward the coupling pin on the top surface of the head portion when the head portion is mounted on the package substrate.

Abstract: A semiconductor device includes a semiconductor element having a plurality of element electrodes formed thereon, a circuit board having board electrodes respectively corresponding to the element electrodes formed thereon and having the semiconductor element mounted thereon, and bumps each of which is provided on at least one of the element electrode and the board electrode, and connects together the element electrode and the board electrode corresponding to each other when the semiconductor element is mounted on the circuit board. Furthermore, at least one of a dielectric layer and a resistive layer is provided between at least one of the bumps and the element or board electrode on which the at least one of the bumps is provided, so that the element or board electrode, the dielectric layer or the resistive layer, and the bump form a parallel-plate capacitor or electrical resistance.

Abstract: A semiconductor device includes a vertical transistor and an external contact plane. The transistor includes: a first side with a first load electrode and a control electrode, and an opposite second side with a second load electrode. The first side of the transistor faces the external contact plane. A dielectric layer extends from at least one edge side of the transistor as far as the second load terminal. An electrically conductive deposited layer is arranged on the dielectric layer and electrically connects the second load electrode to the second load terminal.

Abstract: A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad.

Abstract: A semiconductor device includes an electrode pad provided on a semiconductor chip, the electrode pad includes aluminum (Al) of between 50% wt. and 99.9% wt. and further includes copper (Cu), a coupling ball that primarily includes Cu, the coupling ball being coupled to the electrode pad so that a CuAl2 layer, a CuAl layer, a layer including one of Cu9Al4 and Cu3Al2, and the coupling ball are vertically stacked in this order on the electrode pad, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and a junction between the electrode pad and the coupling ball.

Abstract: Provided is a wiring board wherein a circuit is not short-circuited when a IC chip is mounted on the wiring board. A wiring board (2) is provided with a substrate (4); wiring layers (5-8), which are formed on a surface of the substrate (4) and have prescribed wiring patterns; connecting terminals (9-12), which are formed on a part of the wiring layers (5-8) and electrically connected with bumps (18-21) of an integrated circuit chip (IC chip) (3); a mounting region (14), which is arranged on the surface of the substrate (4) and has the integrated circuit chip (3) mounted therein; and an insulating layer (13), which is formed on the surface of the substrate (4) so as to surround the circumference of the mounting region (14) for protecting wiring layers (5-8). A part of the insulating layer (3) is arranged inside the mounting region (14), and the thickness of the insulating layer (13) is more than that of the bumps (18-21) of the integrated circuit chip (3).

Abstract: A semiconductor substrate structure includes an electrode pad formed on a semiconductor substrate, a protective film formed on the semiconductor substrate with a distance from the electrode pad, and a bump formed on the electrode pad. The protective film has a barrier portion surrounding the electrode pad. The barrier portion has a height different from a height of a part of the protective film other than the barrier portion.

Abstract: A semiconductor element mounted on an insulating resin layer formed on a wiring layer is sealed by a sealing resin. On the wiring layer, a protruding electrode protruding to the side of the semiconductor element and a protruding section are integrally formed with the wiring layer, respectively. The protruding electrode is electrically connected to an element electrode of the semiconductor element by penetrating the insulating resin layer. The protruding section is arranged to surround the semiconductor element along the four sides of the semiconductor element, and is embedded in the sealing resin up to a position above a section where the protruding electrode and the element electrode are bonded.

Abstract: A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

Abstract: A semiconductor device is provided in which a semiconductor chip is bonded to a substrate with a sufficiently increased bonding strength and cracking is assuredly prevented which may otherwise occur due to heat shock, heat cycle and the like. The semiconductor device includes a semiconductor chip and a substrate having a bonding area to which the semiconductor chip is bonded via a metal layer. The metal layer includes an Au—Sn—Ni alloy layer and a solder layer provided on the Au—Sn—Ni alloy layer. Undulations are formed in an interface between the Au—Sn—Ni alloy layer and the solder layer.

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.

Abstract: A stacked semiconductor package includes an upper unit package and a lower unit package. The lower unit package includes a substrate, a semiconductor chip disposed on an upper surface of the substrate, terminal pads arranged on an upper surface of the semiconductor chip, protrusions formed on the terminal pads, a protective layer formed on the substrate and covering the semiconductor chip and the protrusions, and openings formed in the protective layer and exposing the protrusions. The upper unit package includes a substrate, ball lands provided on a lower surface of the substrate, and solder balls formed on the ball lands. The solder balls of the upper unit package are inserted into the openings of the lower unit package to be connected to the protrusions of the lower unit package.

Abstract: A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure.

Abstract: A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate.

Abstract: A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip.

Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.

Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Abstract: Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized.

Abstract: The invention concerns a nanoprinted device comprising point shaped metallic patterns, in which each metallic pattern has a bilayer structure controlled in hardness and in chemical properties comprising a lower layer (30) constituting the base of the point and an upper layer (31) constituting the point itself.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.

Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.

Abstract: A copper post is formed in a passivation layer to electrically connect an underlying bond pad region, and extends to protrude from the passivation layer. A protection layer is formed on a sidewall surface or a top surface of the copper post in a self-aligned manner. The protection layer is a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm2 or above; grinding a surface of the first Au bump; stripping the photoresist; and removing the seed film by dry-etching.

Abstract: Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step.

Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.

Abstract: A circuit board and method of manufacturing a circuit board. The circuit board includes a substrate, a conductor layer formed on the substrate, and an insulation layer formed on the substrate and the conductor layer, the insulating layer having an opening with an undercut therein, the opening reaching the conductor layer. A metal layer is formed in the opening of the insulation layer and connected to the conductor layer, a solder layer formed in the opening of the insulation layer and outside of the opening; and an alloy layer formed in a boundary region between the metal layer and the solder layer in the opening. The alloy layer includes a metal of the metal layer and a composition of the solder layer, the alloy layer being more fragile than the metal layer and being formed in a position misaligned from an edge of the undercut of the opening formed on the insulation layer.

Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate having a transistor and a metallization layer; forming a metal pad in direct contact with the metallization layer of the substrate; forming a passivation layer in direct contact with the metal pad and covering the substrate; forming a routing trace above the passivation layer in direct contact with the metal pad, and the routing trace is substantially larger than the metal pad, and the routing trace is not electrically insulated by a subsequent layer; and forming a bump connected to the metal pad with the routing trace.

Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.

Abstract: A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a gold material. The gold material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the gold material. Additionally, the method includes conductively connecting the gold material with the substrate.

Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.

Abstract: Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective one of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.

Abstract: An apparatus and method for reducing delamination of an integrated circuit module is disclosed. The integrated circuit module includes a laminate substrate. The integrated circuit module further includes an integrated circuit die operably coupled with the laminate substrate and a plastic semiconductor package overmolded with the laminate substrate. The laminate substrate includes a die attach pad including a plurality of metal oxide regions and non-oxidized metal regions disposed on the die attach pads.

Abstract: A semiconductor device includes a semiconductor layer, an electrode pad that is composed of Au and is provided on the semiconductor layer, a silicon nitride film provided on the semiconductor layer and the electrode pad so that an end portion of the silicon nitride film is located, and a metal layer that contacts a part of a surface of the electrode pad and the end portion of the silicon nitride film and is provided so that another part of the surface of the electrode pad is exposed, the metal layer including any of Ti, Ta and Pt.

Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

Abstract: A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is between the active portion and the carrier substrate and a platinum barrier layer is between the nickel-tin bonding system and the titanium adhesion layer. The platinum layer has a thickness sufficient to substantially prevent tin in the nickel tin bonding system from migrating into or through the titanium adhesion layer.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract: A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate.