Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.

Abstract: A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side.

Abstract: A carrier structure embedded with semiconductor chips is disclosed, which comprises a core board and a plurality of semiconductor chips mounted therein. The core board comprises two metal plates between which an adhesive material is disposed. An etching stop layer is deposited on the both surfaces of the core board. Pluralities of cavities are formed to penetrate through the core board. The semiconductor chips each have an active surface on which a plurality of electrode pads are disposed, and those are embedded in the cavities and mounted in the core board. An etching groove formed on the core board between the neighboring semiconductor chips is filled with the adhesive material. The present invention avoids the production of metal burrs when the carrier structure is cut.

Abstract: A semiconductor device such as a COF or the like is provided on a semiconductor chip on a film-like shaped flexile wiring substrate on which a wiring pattern is formed. Between the semiconductor chip and the flexile wiring substrate, a sealing resin is filled for protecting the semiconductor chip. In the semiconductor device, a resin trace is 0.1 to 1.0 mm in width and 10 ?m in thickness, the resin trace being formed when applying the sealing resin along a longitudinal side of the semiconductor chip.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including at least two electronic components which are provided in a stacked arrangement, and are each electrically connected to an underlying substrate through the use of conductive wires. In accordance with one embodiment of the present invention, the electronic components are separated from each other by an intervening spacer which is typically fabricated from aluminum, or from silicon coated with aluminum. In this particular embodiment, the uppermost electronic component of the stack is electrically connected to at least one of the conductive wires through the use of a conductive paste layer which is also used to secure the uppermost electronic component to the underlying spacer.

Abstract: A semiconductor chip includes flip chip contacts that are arranged on contact surfaces of an active top side of the semiconductor chip. The contact surfaces are surrounded by a passivation layer that covers the active top side while leaving exposed the contact surfaces. The passivation layer includes thickened portions that surround the contact surfaces. The semiconductor chip formed with thickened portions around the contact surfaces is protected from delamination during packaging of the semiconductor chip to form a semiconductor device.

Abstract: A semiconductor device is provided which comprises a thermally radiative and electrically conductive support plate 1; and a regulatory semiconducting element 2 mounted on one main surface of support plate 1 through an insulator 3. Insulator 3 comprises an insulative layer 3a mounted on support plate 1 and an adiabatic layer 3b interposed between insulative layer 3a and regulatory semiconducting element 2 to fully protect regulatory semiconducting element 2 from heated environment therearound in the semiconductor device.

Abstract: A bonding head includes a pressure plate to press a component (e.g., a semiconductor chip) onto a substrate. The pressure plate includes a holding surface configured to hold the component and to allow the component to be pressed uniformly onto the substrate, thus allowing a particularly reliable connection. The bonding head can further include an apparatus configured to vary the curvature of the holding surface of the pressure plate.

Abstract: A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Abstract: The image pickup apparatus includes: an image pickup device including a pixel region and an electrode; an electric board including the image pickup device arranged to cover an opening and a connection pattern arranged in the vicinity of an edge portion of the opening, in which a first adhesive is applied between the image pickup device and the electric board from the outer edge of the image pickup device at least to an electric connection portion between the connection pattern and the electrode and applied annularly with a first band along an outer edge of the image pickup device; and a protective cover fixed by a second adhesive so as to cover the opening on the other surface of the electric board, wherein the second adhesive is applied annularly with a second band so that the first band width overlaps within the second one.

Abstract: A semiconductor chip and manufacturing method thereof, the semiconductor chip including a plurality of bumps connected to a driving circuit integrated on a semiconductor substrate and an organic insulating layer disposed on the driving circuit. The organic insulating layer extends from the semiconductor substrate less than the plurality of bumps such that a lower edge of the plurality of bumps protrudes further than a lower edge of the organic insulating layer.

Abstract: A chip card catching mechanism installed in a body of a portable electronic device for receiving and securing a chip card is provided. The chip card catching mechanism includes a base, a housing, and a hatch. The base includes a connector arranged thereon for electrically connecting to the chip card. The housing includes a top cover and a circumferential wall extending from edges of the top cover. The top cover is arranged over the connector of the base with the wall therebetween and a hatchway is defined on the circumferential wall. The hatch is rotatably fixed to on two sides of the hatchway for exposing or hiding the hatchway. Further, a portable electronic device using the chip card catching mechanism is also provided.

Abstract: Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and an upper metal interconnection layer disposed on the intermetallic dielectric layer and electrically connected through the intermetallic dielectric layer and buffer layer to the lower metal interconnection layers.

Abstract: A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located. Discrete conductive elements, such as solder balls, may protrude from the contact pads of the substrate.

Abstract: In a semiconductor device, a semiconductor substrate may include a plurality of first conductive pads. An insulating isolation layer may be on the semiconductor substrate so as to separate the first conductive pads. A package substrate may include a plurality of second conductive pads. A conductive adhesive layer may connect the first conductive pads and the second conductive pads.

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract: The present invention relates to a semiconductor device, and more particularly to a manufacturing method for said semiconductor device. The semiconductor device comprises a die that connects with a substrate or a lead frame via an adhesion layer, a metal layer, and/or a back metal layer. Furthermore, the adhesion layer can be made of aluminum, and the die can connect with the substrate or the lead frame by ultrasonic bonding technology, which can avoid heat damaging the die during the manufacturing process.

Abstract: A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.

Abstract: A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.

Abstract: A semiconductor device in accordance with the present invention includes IC chips (semiconductor elements) (2, 3, 4) having solder bumps (24) (projecting electrodes) formed on electrode pads, and a first wiring board (1) having connection terminals (7) to which the respective solder bumps (24) of the IC chips (2, 3, 4) are connected, external connection terminals (8) for connection to an external apparatus, and conductor wires (9) provided in respective groove portions formed in a board surface and connected to the respective connection terminals (7). In spite of the reduced pitch of the conductor wires (9), the presence of the groove portions enables an increase in cross section, allowing a reduction in wiring resistance.

Abstract: A microelectronic device wafer includes an adhesive molded in-situ on the wafer. Adhesives and wafers are positioned in molds and a method that includes drawing in the molds at least a partial vacuum and partially curing the adhesive provides an in-situ molded adhesive that is positioned on the wafer. The adhesives can be in liquid, solid, or other forms prior to molding. During molding, the adhesive can be partially cured by heating or irradiating.

Abstract: An integrated circuit may be secured to a substrate using an anisotropically conductive adhesive that may be cured at a temperature of less than 150° C. In some embodiments, an acrylic resin with embedded metallic particles may be used as the anisotropically conductive adhesive. In some embodiments, the board level reliability of the resulting product may be improved through the use of the anisotropically conductive adhesive that may be cured at a temperature of less than 150° C.

Abstract: A method of packaging a semiconductor component with a printed wiring board is disclosed. The method includes determining a first distance, applying a thin film onto a surface of the semiconductor component such that the thin film is spaced apart from a support of the semiconductor, applying a solder pad onto the printed wiring board, placing the semiconductor component with the thin film onto the printed wiring board, and positioning the thin film adjacent the solder pad.

Abstract: A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die.

Abstract: The semiconductor device includes: a semiconductor chip; a die pad for holding the semiconductor chip; a lead; and a sealing resin material for sealing the semiconductor chip, the die pad and an inner portion of the lead. The die pad has an upset portion protruding upward to form a flat face smaller in area than the semiconductor chip, and the portion of the die pad excluding the upset portion is covered with a buffer resin material smaller in elasticity than the sealing resin material.

Abstract: Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming in contact partially with the semiconductor chip; a mounting material provided on a contact surface between each of the island and hanging leads and the semiconductor chip so as to adhere the semiconductor chip to the island and the hanging leads; and sealing resin for sealing the semiconductor chip. The modulus of elasticity of the mounting material is lower than that of the sealing resin. The mounting material is further coated on the back surfaces of the contact surfaces of the island and the hanging leads.

Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.

Abstract: A method of manufacturing a module, formed of a semiconductor element flip-chip bonded to a substrate and chip component soldered to the substrate, is disclosed. The method includes a step of mounting the chip component and the semiconductor element to the substrate, a first injection step for injecting first resin from a center of a lateral face of the semiconductor element into a gap between the semiconductor element and the substrate, a second injection step for applying second resin having a greater viscosity than the first resin to corners of the semiconductor element before the first resin reaches the corners, and a curing step for heating the module. This method allows mounting the chip component closer to the semiconductor element, so that the component can be mounted at a higher density on the module.

Abstract: A semiconductor device includes semiconductor device components, an adhesion promoter structure and a plastic housing composition. The semiconductor device components are embedded in the plastic housing composition with the adhesion promoter structure being disposed between the device components and the housing composition. The adhesion promoter structure includes first and second adhesion promoter layers. The first layer includes metal oxides. The metal oxides being silicates of a reactive compound composed of oxygen and organometallic molecules. The second layer includes at least one polymer.

Abstract: A method for manufacturing a substrate embedded with a passive device, comprising the steps of (a) molding the passive device and (b) mounting the molded passive device in a cavity formed on the substrate, is disclosed. The substrate embedded with a passive device and the manufacturing method thereof in accordance with the present invention can prevent warpage of the substrate caused by disproportioned properties of materials.

Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

Abstract: A semiconductor device manufacturing method includes (a) bonding a first surface of a metal plate to a substrate, (b) forming a plurality of metal posts that are arranged in vertical and lateral directions in a plan view and include a first metal post and a second metal post, by partially etching the metal plate bonded to the substrate from a second surface of the metal plate, (c) fixing an integrated circuit (IC) element to the second surface of the first metal post, (d) coupling the second metal post and a pad terminal of the integrated circuit element via a conductive material, (e) resin-sealing the integrated circuit element, the metal posts, and the conductive material by providing a resin onto the substrate, and (f) removing the substrate from the resin and the first surfaces of the metal posts sealed using the resin.

Abstract: This publication discloses a method for manufacturing an electronic module, in which manufacture commences from an insulating-material sheet (1). At least one recess (2) is made in the sheet (1) and extends through the insulating-material layer (1) as far as the conductive layer on the opposite surface (1a). A component (6) is set in the recess, with its contact surface towards the conductive layer and the component (6) is attached to the conductive layer. After this, a conductive pattern (14) is formed from the conductive pattern closing the recess, which is electrically connected from at least some of the contact areas or contact protrusions of the component (6) set in the recess.

Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.

Abstract: A die attach process employs a temperature gradient lead free soft solder metal sheet or thin film as the die attach material. The sheet or thin film is formed to a uniform thickness and has a heat vaporizable polymer adhesive layer on one surface, by which the thin film is laminated onto the back metal of the silicon wafer. The thin film is lead-free and composed of acceptably non-toxic materials. The thin film remains semi-molten (that is, not flowable) in reflow temperatures in the range about 260° C. to 280° C. The polymer adhesive layer is effectively vaporized at the high reflow temperatures during the die mount.

Abstract: The present invention provides a method for manufacturing a semiconductor device which includes at least supplying an adhesive for bonding an electronic component which has a plurality of bumps with a substrate which has a plurality of bonding pads corresponding to the bumps, to at least a portion of the substrate, between the electronic component and the substrate, flow-casting the adhesive on the substrate by a flow-casting unit, in such a manner that the expression S1/S0>1 is satisfied, where S0 is the total contact surface area with the substrate of the adhesive supplied to the substrate, and S1 is the total contact surface area with the substrate of the adhesive after the flow-casting, and curing the adhesive while making the adhesive contact with the electronic component and the substrate in a state where the bumps are abutted against the bonding pads.

Abstract: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation.

Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.

Abstract: A semiconductor device includes: a package case in which a semiconductor element is mounted, the package case having a bonding portion; a cap having a bonding portion bonded to the bonding portion of the package case so as to hermetically seal the semiconductor element; and one or more bonding/sealing wires disposed between and in contact with the bonding portion of the package case and the bonding portion of the cap such that the one or more bonding/sealing wires form a closed loop and hermetically seal the semiconductor element.

Abstract: A removable wafer expander for die bonding equipment for a singularized wafer supported by a flexible sticky substrate, the removable wafer expander provided with a first ring member to be coupled with a second ring member for remote expansion of the flexible sticky substrate therebetween before the mounting of the wafer expander onto the die bonding equipment.

Abstract: A semiconductor device includes a carrier such as a lead frame, a semiconductor die and an attachment member affixing the semiconductor die to the carrier. The attachment device includes an electrically conductive organic material.

Abstract: A leadframe-based semiconductor package is revealed, primarily comprising a chip, a plurality of leads of a leadframe, a multi-layer tape, and an encapsulant. The multi-layer tape is attached to the chip and includes an adhesive layer disposed on a dielectric core layer. The internal leads of the leads are partially embedded in the adhesive layer in a manner not to directly contact the dielectric core layer. A bonding interface with a U-shaped profile is formed between the adhesive layer and each internal lead to increase the adhesions of the leads so that the internal leads will not be shifted nor delaminated during molding processes. The concentrated stresses exerted on the internal leads disposed at the corners of the packages will be released and reduced.

Abstract: A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin.

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.

Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.

Abstract: A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract: A technique for mounting a plurality of electronic parts on one surface of a wiring substrate is provided.

Abstract: A micro chip-scale-package system including providing a metal pattern on an adhesion material, attaching an integrated circuit die to the metal pattern, and molding an encapsulant over the integrated circuit die and the metal pattern.

Abstract: A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.