Abstract: It is an object to provide a semiconductor device capable of transmitting and receiving data with a reader/writer and reducing breakdown or interference due to static electricity. A semiconductor device includes a semiconductor integrated circuit, a conductive layer serving as an antenna that is connected to the semiconductor integrated circuit, and a substrate interposing the semiconductor integrated circuit and the conductive layer, where at least one of a layer forming the semiconductor integrated circuit, a layer covering the semiconductor integrated circuit, and the substrate is formed from a conductive polymer. In accordance with the above structure, wireless communication with a reader/writer is possible, and breakdown or malfunction in the semiconductor integrated circuit due to static electricity is reduced.

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract: A semiconductor device has a plurality of semiconductor die mounted to a carrier. An adhesive material is deposited over a portion of the semiconductor die and carrier to secure the semiconductor die to the carrier. The adhesive material is deposited over a side of the semiconductor die and over a surface of the carrier. The adhesive material can be deposited over a corner of the semiconductor die, or over a side of the semiconductor die, or around a perimeter of the semiconductor die. An encapsulant is deposited over the semiconductor die and carrier. The adhesive material reduces shifting of the semiconductor die with respect to the carrier during encapsulation. The adhesive material is cured and the carrier is removed. The adhesive material can also be removed. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die are singulated through the encapsulant and interconnect structure.

Abstract: A printed board comprising a packaging surface on which an electronic component is packaged, an adhesion prohibited portion which is provided at a region of the printed board different from a region where the electronic component is provided, and to which adhesion of the adhesive material is prohibited, and a blocking step portion which is formed at a region between the region where the electronic component is provided and the region where the adhesion prohibited portion is provided, which blocks any adhesive material which has spilled out from between the bottom surface of the electronic component and the packaging surface from reaching the adhesion prohibited portion.

Abstract: An electronic part mounting structure includes electronic part having a plurality of electrode terminals, a substrate provided with connection terminals in locations corresponding to these electrode terminals, and protruding electrode for connecting one of electrode terminals and one of connection terminals, where electrode terminal of electronic part and connection terminal of substrate are connected through protruding electrode and protruding electrode is formed of a conductive resin including a photosensitive resin and a conductive filler.

Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.

Abstract: This invention provides a wiring-terminal-connecting adhesive comprising a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles, and a wiring-terminal-connecting method and a wiring structure which make use of such an adhesive.

Abstract: The disclosed subject matter includes a surface mount electronic device with high reliability and favorable optical characteristics. The surface mount electronic device can include a circuit board with at least one conductor pattern formed on an insulating board and an electronic component that is mounted on a die bonding pad located on the at least one conductor pattern with an adhesive material. The die bonding pad can include a plurality of cutout sections that expose the insulating board and extend towards a center from a circumference thereof. Therefore, the adhesive material can adhere to both the die bonding pad and the insulating board exposed in the plurality of cutout sections along with the electronic component. In this case, the plurality of cutout sections can be formed so as not to drag the adhesive material upwards on each of the side surfaces of the electronic component.

Abstract: In a semiconductor apparatus, a semiconductor element is mounted on a wiring substrate. Wiring patterns and protrusions are formed on a surface of a substrate with the wiring patterns extending on tops of the protrusions. The surface of the substrate on which the wiring patterns are formed are covered with an insulating layer. Surfaces of connection parts of the wiring patterns formed on the tops of the protrusions are formed with the surfaces of the connection parts exposed to a surface of the insulating layer on a level with the surface of the insulating layer or in a position lower than the surface of the insulating layer. The connection parts are formed as pads for connection formed in alignment with connection electrodes of the semiconductor element. The semiconductor element is mounted by making electrical connection to the connection parts by flip chip bonding.

Abstract: An adhesive sheet is provided enabling to efficiently produce the very small size semiconductor chip by a stealth dicing method. An adhesive sheet for a stealth dicing includes a substrate and an adhesive layer formed on one side of the substrate, wherein a Young's modulus of the adhesive sheet at 23° C. is 200 to 600 MPa, and a storage elastic modulus of the adhesive layer at 23° C. is 0.10 to 50 MPa.

Abstract: A semiconductor apparatus includes a first wiring substrate, a second wiring substrate, a semiconductor chip, an adhesive layer and a molding resin. The second wiring substrate is stacked and connected on the first wiring substrate through a bump electrode. The semiconductor chip is mounted on the first wiring substrate by flip chip bonding and received between the first wiring substrate and the second wiring substrate. An upper surface of the semiconductor chip is subject to a mirror treatment. The adhesive layer is formed on the upper surface of the semiconductor chip. The molding resin is filled in a gap between the first wiring substrate and the second wiring substrate.

Abstract: In a semiconductor device mounted structure in which device electrodes of a semiconductor device and board electrodes of a board are connected to each other via bump electrodes, respectively, and in which a sealing-bonding resin is placed between the semiconductor device and the board, a void portion is placed at a position corresponding to an edge portion of the semiconductor device in the sealing-bonding resin. Thus, stress loads generated at corner portions of the semiconductor device due to board flexures for differences in thermal expansion and thermal contraction among the individual members caused by heating and cooling during mounting of the semiconductor device, as well as for mechanical loads after the mounting process, can be absorbed by the void portion and thereby reduced, so that breakdown of the semiconductor device mounted structure is prevented.

Abstract: A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive polymeric compound 105 between bodies 104. Metal bodies 104 form metal inter-diffusions with carrier 102 and extend from the carrier across thickness 103a, stopping at and contacting second chip surface 101b. The high thermal conductivity of metal bodies 104 greatly increases the thermal conductivity of the attachment layer. The metal bodies may be arrayed in a regularly spaced pattern in x- and y-directions, as well as in enhanced concentrations in locations of thermal hot spots and of high thermomechnical stresses. In the latter application, the metal bodies prevent the growth of microcracks and delamination.

Abstract: A device comprising a first component (5) having a first surface (6), a second component (8) having a second surface (9) and a connection layer (7) between the first surface (6) of the first component (5) and the second surface (9) of the second component (8), wherein the connection layer (7) comprises an electrically insulating adhesive and there is an electrically conductive contact between the first surface (6) of the first component (5) and the second surface (9) of the second component (8).

Abstract: A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.

Abstract: An underfill composition is formulated to increase the surface tension thereof for use in capillary underfilling of an integrated circuit die that is coupled to a mounting substrate. A method includes mixing a surface tension-increasing additive with a bulk polymer and a hardener and allowing the underfill composition to flow between the integrated circuit die and the mounting substrate. An article is achieved by the method. The article can be assembled into a computing system.

Abstract: There is provided an LED package having high heat dissipation efficiency. An LED package according to an aspect of the invention may include: a package body including a first groove portion being recessed into the package body and provided as a mounting area on the top of the package body; first and second lead frames arranged on a lower surface of the first groove portion while parts of the first and second lead frames are exposed; an LED chip mounted onto the lower surface of the first groove portion and electrically connected to the first and second lead frames; and a plurality of heat dissipation patterns provided on the bottom of the package body and formed of carbon nanotubes.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including at least two electronic components which are provided in a stacked arrangement, and are each electrically connected to an underlying substrate through the use of conductive wires. In accordance with one embodiment of the present invention, the electronic components are separated from each other by an intervening spacer which is typically fabricated from aluminum, or from silicon coated with aluminum. In this particular embodiment, the uppermost electronic component of the stack is electrically connected to at least one of the conductive wires through the use of a conductive paste layer which is also used to secure the uppermost electronic component to the underlying spacer.

Abstract: A module substrate may include a substrate body on which a plurality of chip mounting regions having connection pads are defined. Repair structures may be respectively formed, or placed, in the chip mounting regions. Each repair structure includes conductive layer patterns formed over the connection pads in each chip mounting region, an insulation layer pattern formed over the substrate body in each chip mounting region in such a way as to expose the conductive layer patterns, plastic conductive members formed between the connection pads and the conductive layer patterns, and a plastic insulation member formed between the substrate body and the insulation layer pattern in each chip mounting region.

Abstract: A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Abstract: A method for producing semiconductor components and a component obtainable by such a method is disclosed. The method comprises the following steps: fixing a conductive film on a carrier; adhesively bonding semiconductor chips onto the conductive film using an adhesive layer, wherein active surfaces of the semiconductor chips, the active surfaces having connection contacts, are situated on that side of the chips which faces the film; overmolding the chips adhesively bonded onto the conductive film with a molding compound; and releasing the conductive film with the overmolded chips from the carrier. In this case, the adhesive layer is structured in such a way that at least connection contacts of the semiconductor chips are free of the adhesive layer and are kept free of the molding compound.

Abstract: A method of producing an electronic module with at least one electronic component and one carrier. A structure is provided on the carrier so that the electronic component can take a desired target position relative to the structure. The structure is coated with a liquid meniscus suitable for receiving the electronic component. Multiple electronic components are provided at a delivery point for the electronic components. The carrier, with the structure, is moved nearby and opposite to the delivery point, where the delivery point delivers one of the electronic components without contact, while the structure on the carrier is moving near the delivery point, so that after a phase of free movement the electronic component at least partly touches the material, and the carrier, with the structure, is moved to a downstream processing point, while the electronic component aligns itself to the structure on the liquid meniscus.

Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.

Abstract: On a printed-wiring board 1-1, a conductor layer 2 is laminated to both the top surface and the bottom surface of a substrate core 7 so as to pattern the substrate core, and a solder resist 4 is laminated to the substrate core. The solder resist 4 laminated to the top surface of the printed-wiring board 1-1 forms a raised portion 40 in a semiconductor chip mounting area such that the thickness of the raised portion is greater than the thickness of the solder resist 4 laminated to areas other than the semiconductor chip mounting area, so that the surface of the semiconductor chip mounting area is flat.

Abstract: A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the adhesive strength between the electrode 11 and the easy peeling portion 12 being less than the adhesive strength between the electrode 11 and the base material 10. A circuit board that has high connection reliability and enables narrow pitch mounting thereby can be provided.

Abstract: The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from the substrate. Especially, an integrated circuit which is formed by a thin film is extremely thin, and so there is a threat that the integrated circuit is flied when transporting, and so handling thereof is difficult. In accordance with the present invention, a separating layer (also referred to as a peeling layer) is damaged at a plurality of times by at least two different kinds of methods (a damage due to laser light irradiation, a damage due to etching, or a damage due to a physical means), subsequently, the layer to be peeled can be efficiently peeled from a substrate. Further, handling of individual devices becomes easy by arching the peeled device.

Abstract: Disclosed is a structure for mounting a component to a lighting device, including at least one lighting-device base, at least one metal film, and a lighting array chip. The lighting-device base has a surface to which a first layer of metal bonding agent is applied. The metal film has a surface attached to the first metal bonding agent layer on the surface of the lighting-device base. The lighting array chip has a bottom surface to which a second layer of metal bonding agent is applied. The second metal bonding agent layer is further attached to an opposite surface of the metal film so as to securely mount the lighting array chip to the surface of the lighting-device base.

Abstract: A base plate for a heat sink comprises a cooling plate and spacer elements, which are arranged on the surface of the cooling plate. The spacer elements and the cooling plate are made as one piece and the material in the surface region of the cooling plate and of the spacer elements being the same and formed in the same process.

Abstract: The present invention is a circuit connecting material used for the mutual connection of a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, and a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, with the edge parts and of the insulating layers being formed with a greater thickness than the electrodes on the basis of the main surfaces, wherein this circuit connecting material contains a bonding agent composition and conductive particles that have a mean particle size of 1 ?m or greater but less than 10 ?m and a hardness of 1.961 to 6.865 GPa, and this circuit connecting material exhibits a storage elastic modulus of 0.5 to 3 GPa at 40° C. and a mean coefficient of thermal expansion of 30 to 200 ppm/° C. at from 25° C. to 100° C. when subjected to the curing treatment.

Abstract: According to one embodiment, a semiconductor chip mounting body, with an enhanced shock-resistance at portions of the bonding member corresponding to the corners of a semiconductor chip, is provided. The semiconductor chip mounting body includes a circuit board having a circuit pattern formed on a mounting surface thereof, a semiconductor chip mounted on the circuit pattern of the circuit board, and a bonding member arranged at least between the circuit board and the semiconductor chip, and on the sides of the semiconductor chip to fix the semiconductor chip on the circuit board. The bonding member contains thermosetting resin and magnetic powder dispersed in the thermosetting resin. The magnetic powder is locally disposed in portions of the bonding member which is located the corners of the semiconductor chip.

Abstract: This publication discloses an electronic module and a method for manufacturing an electronic module, in which a component (6) is glued (5) to the surface of a conductive layer, from which conductive layer conductive patterns (14) are later formed. After gluing the component (6), an insulating-material layer (1), which surrounds the component (6) attached to the conductive layer, is formed on, or attached to the surface of the conductive layer. After the gluing of the component (6), feed-throughs are also made, through which electrical contacts can be made between the conductive layer and the contact zones (7) of the component. After this, conductive patterns (14) are made from the conductive layer, to the surface of which the component (6) is glued.

Abstract: A method for manufacturing an integrated circuit package in package system includes: providing a substrate having a first wire-bonded die with an active side mounted above; connecting the active side of the first wire-bonded die to the substrate with a bond-wire; mounting a wire-in-film adhesive having an isolation barrier over the first wire-bonded die; and encapsulating the first wire-bonded die, the bond-wires, and the wire-in-film adhesive with an encapsulation.

Abstract: There are provided an adhesive for connecting a circuit to be interposed between substrates having circuit electrodes thereon opposed to each other and to electrically connect the circuit electrodes on the substrates opposed to each other to the pressurizing direction under pressure, wherein the adhesive contains a compound having an acid equivalent of 5 to 500 KOH mg/g, and an adhesive for connecting a circuit to be interposed between substrates having circuit electrodes opposed to each other and to electrically connect the electrodes on the substrate opposed to each other to the pressurizing direction under pressure, wherein the adhesive comprises a first adhesive layer and a second adhesive layer, and a glass transition temperature of the first adhesive layer after pressure connection is higher than the glass transition temperature of the second adhesive layer after pressure connection.

Abstract: To simplify a peeling step in a method for manufacturing a semiconductor device including the peeling step. A first layer having a metal film is formed over a substrate; a second layer having a transistor is formed over the first layer having the metal film; a resin material is applied over the layer having the transistor; the resin material is cured by a heat treatment at a first heat treatment temperature to form a resin layer; the layer having the transistor is peeled from the substrate by a heat treatment at a second heat treatment temperature which is higher than the first heat treatment temperature; and the resin layer is peeled from the layer having the transistor by a heat treatment at a third heat treatment temperature which is higher than the second heat treatment temperature.

Abstract: A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 120 in which stud bumps 121 are provided to the principal surface 120a, a first resin layer 111 for covering the principal surface 120a of the semiconductor IC 120, and a second resin layer 112 for covering the back surface 120b of the semiconductor IC 120. The stud bumps 121 of the semiconductor IC 120 protrude from the surface of the first resin layer 111. The method for causing the stud bumps 121 to protrude from the surface of the first resin layer 111 may involve using a wet blasting method to cause an overall reduction of the thickness of the first resin layer 111. The stud bumps 121 can thereby be properly uncovered even when the electrode pitch of the semiconductor IC 120 is narrow.

Abstract: A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece and an IC die. The die attach adhesive precursor includes metal particles, a first plurality of first microcapsules having a polymerizable material inside, and a second plurality of second microcapsules having a polymerization agent inside to form a first polymer upon rupture of first and second microcapsules. A force sufficient to rupture at least a portion of the first plurality of first microcapsules and at least a portion of the second plurality of second microcapsules is applied to form a self-healing die attach adhesive wherein the first polymer binds the plurality of metal particles and the remaining microcapsules and secures the IC die to the top surface of the workpiece. The self-healing die attach adhesive generally includes at least 90 vol. % metal.

Abstract: The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies.

Abstract: To provide a components joining method and a components joining structure which can realize joining of components while securing conduction at a low electrical resistance with high reliability. In a construction in which by using a solder paste containing solder particles 5 in a thermosetting resin 3a, a rigid substrate 1 and a flexible substrate 7 are bonded by the thermosetting resin 3a, and a first terminal 2 and a second terminal 8 are electrically connected by the solder particles 5, a blending ratio of an activator of the thermosetting resin 3a in the solder paste is properly set and oxide film removed portions 2b, 8b, and 5b are partially formed in oxide films 2a, 8a, and 5a of the first terminal 2, the second terminal 8, and the solder particles 5.

Abstract: A chip on film (COF) structure includes a flexible circuit board and a chip. The flexible circuit board includes a flexible base film and a conductive layer. The flexible base film has a polyimide layer and an anisotropic conductive layer (ACL). The conductive layer is disposed on the flexible base film. The conductive layer and the ACL are separated by the polyimide layer. The chip is mounted with the conductive layer via interconnectors.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: An object of the present invention is to provide an adhesive sheet that can fill irregularities due to wiring of a substrate or a wire attached to a semiconductor chip, etc., does not form resin burrs during dicing, and has satisfactory heat resistance and moisture resistance. The present invention relates to an adhesive sheet comprising 100 parts by weight of a resin comprising 15 to 40 wt % of a high molecular weight component containing a crosslinking functional group and having a weight-average molecular weight of 100,000 or greater and a Tg of ?50° C. to 50° C., and 60 to 85 wt % of a thermosetting component containing an epoxy resin as a main component, and 40 to 180 parts by weight of a filler, the adhesive sheet having a thickness of 10 to 250 ?m.

Abstract: An active matrix substrate includes a first substrate, a driving integrated circuit chip mounted on the first substrate with an anisotropic electrically conductive layer, and an insulating member. The insulating member isolates a terminal from a wiring and a bump electrode that are adjacent to the terminal portion and isolates a bump electrode facing the terminal portion from a bump electrode and a wiring that are adjacent to the bump electrode.

Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.

Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: Provided are a tape, apparatus, and method that relate generally to a single layer adhesive which functions as a dicing tape and also as a die attach adhesive for dicing thinned wafers and subsequent die attach operations of the diced chips in semiconductor device fabrication. The tape, apparatus, and method include a backing with a surface modification that includes a pattern.

Abstract: An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive.

Abstract: An image pickup apparatus according to an embodiment includes: an image pickup device chip including an image pickup device formed on a first principal surface thereof and an external terminal for the image pickup device formed on a second principal surface thereof; a wiring board including a distal end portion including a connection pad, a flexure portion flexed at an angle of no less than 90 degrees, and an extending portion, the wiring board including a wiring layer extending from the distal end portion to the extending portion via the flexure portion, the wiring board being kept within a space immediately above the second principal surface of the image pickup device chip; a bonding layer that joins the second principal surface of the image pickup device chip and the distal end portion of the wiring board; and a bonding wire that electrically connects the external terminal and the connection pad.

Abstract: Provided is an adhesive tape which adheres two members to each other and decreases problems that may occur due to contraction and expansion of the adhered members when the temperature of the adhered two members changes. The adhesive tape includes: a base film having insulating properties; and an adhesive agent that adheres on both sides of the base film, wherein a coefficient of thermal expansion of the base film is 10 ppm or lower, a coefficient of thermal expansion of the adhesive tape is lower than 17 ppm, and an occupation rate of the base film in the adhesive tape exceeds 50%.

Abstract: An object of the present invention is to provide a die-adhering adhesive film which can be laminated on a back of a wafer at a temperature lower than a softening temperature of a protecting tape for an ultra-thin wafer, or a dicing tape to be laminated, can reduce a thermal stress such as warpage of a wafer, can simplify a step of manufacturing a semiconductor device, and is excellent in heat resistance and humidity resistance reliance, an adhesive sheet in which the adhesive film and a dicing tape are laminated, as well as a semiconductor device.