With Adhesive Means Patents (Class 257/783)
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Publication number: 20100007017Abstract: The present invention discloses an inter-connecting structure for a semiconductor package and a method for the same. The inter-connecting structure for the semiconductor package comprises a substrate formed to support a die thereon; core paste formed on the substrate and adjacent to the die; and a stiffener formed in an upper portion of the core paste, wherein the hardness of the stiffener is larger than the hardness of the core paste.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Inventors: Shih-Chuan Wei, Dyi-Chung Hu, Yu-Shan Hu
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Patent number: 7646103Abstract: A dicing/die-bonding film including a pressure-sensitive adhesive layer (2) on a supporting base material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein a releasability in an interface between the pressure-sensitive adhesive layer (2) and the die-bonding adhesive layer (3) is different between an interface (A) corresponding to a work-attaching region (3a) in the die-bonding adhesive layer (3) and an interface (B) corresponding to a part or a whole of the other region (3b), and the releasability of the interface (A) is higher than the releasability of the interface (B). The dicing/die-bonding film is excellent in balance between retention in dicing a work and releasability in releasing its diced chipped work together with the die-bonding adhesive layer.Type: GrantFiled: March 7, 2006Date of Patent: January 12, 2010Assignee: Nitto Denko CorporationInventors: Takeshi Matsumura, Masaki Mizutani
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Patent number: 7645637Abstract: The invention is based on the discovery that certain self-filleting die attach adhesives are useful in semiconductor die assemblies containing thin die. As used herein, the term “self-filleting” refers to any adhesive that when dispensed and then subjected to suitable cure conditions, will flow and fill up the area between two die or between a die and a substrate while not forming a bulky fillet that can overflow onto the top of the die. In addition, the invention is useful for tight tolerance semiconductor die assemblies, since the fillet from the die-attach adhesives employed in the methods of the invention does not cover bond fingers, thereby causing wire bond yield loss.Type: GrantFiled: October 16, 2006Date of Patent: January 12, 2010Assignee: Henkel CorporationInventor: Deborah Forray
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Patent number: 7646095Abstract: In a semiconductor device of the present invention, in order that the contact of electrodes formed on a film substrate with edge parts of a semiconductor element at the time such as when the semiconductor element is mounted thereon may be reliably prevented, in the semiconductor element mounted on at least one surface of the film substrate having the electrodes, an insulating protection part is formed at a desired position of the surface opposed to the electrodes, and the distance between the semiconductor element and the film substrate is set at not less than 10 ?m.Type: GrantFiled: September 21, 2004Date of Patent: January 12, 2010Assignee: Panasonic CorporationInventors: Kazushi Higashi, Kouichi Yoshida, Shinji Ishitani, Daido Komyoji
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Patent number: 7646088Abstract: [Problem] To provide an adhesive sheet which is used for a light-emitting diode device, and which is free from cracks and peeling off of the adhered portions. [Means for Solving the Problem] An adhesive sheet for a light-emitting diode device, which comprises a thermoplastic polymer containing epoxy groups and a compound containing functional groups which are addition reactive with the epoxy groups or a polymerization catalyst which can effect a ring opening polymerization of the epoxy groups, and in which said thermoplastic polymer is cross-linked so that its flowability is restrained.Type: GrantFiled: January 13, 2005Date of Patent: January 12, 2010Assignee: 3M Innovative Properties CompanyInventors: Koji Itoh, Shigeyoshi Ishii
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Patent number: 7646085Abstract: A semiconductor device includes external interface terminals and processing circuits, and it is fed with an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for, at least, a predetermined time period since the separation of an extraction detecting terminal among the external interface terminals, from the corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. Thus, a time period till the cutoff of the power source is easily made comparatively long. The power source feeding terminals should preferably be extended onto the insertion side of the semiconductor device, but an extendible distance is sometimes liable to be limited.Type: GrantFiled: September 24, 2004Date of Patent: January 12, 2010Assignee: Renesas Technology Corp.Inventors: Hirotaka Nishizawa, Kenji Osawa, Hideo Koike, Junichiro Osako, Tamaki Wada
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Patent number: 7646020Abstract: When bonding a workpiece to a substrate, processed parts of the substrate and the workpiece are observed and behavior such as the production of voids and the flowing of resin is observed. An apparatus for observing an assembled state of components includes: a stage on which a substrate is set; a head mechanism that bonds, by applying heat and pressure, an observation workpiece made of a transparent material to the substrate via resin supplied between the substrate and the observation workpiece; a light source that irradiates an observed part of the substrate and the observation workpiece mounted on the stage with light; and a camera that takes, from the observation workpiece side, an image of the observed part when the observation workpiece is bonded to the substrate set on the stage.Type: GrantFiled: August 31, 2007Date of Patent: January 12, 2010Assignee: Fujitsu LimitedInventors: Shuichi Takeuchi, Hidehiko Kira
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Patent number: 7642131Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.Type: GrantFiled: November 8, 2006Date of Patent: January 5, 2010Assignee: Harris CorporationInventors: Robert S. Vinson, Joseph B. Brief, Donald J. Beck, Gregory M. Jandzio
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Patent number: 7638880Abstract: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.Type: GrantFiled: August 26, 2008Date of Patent: December 29, 2009Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, David Wei Wang
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Patent number: 7638864Abstract: A digital camera module (100) includes a chip package (110) and a lens module (130), mounted on the chip package, for forming a focused image on the chip package. The chip package includes a supporter (112), a chip (114), a plurality of wires (116), a main adhesive (118), and a cover plate (119). The supporter includes a through hole defined therethrough and has a plurality of top contacts (1130) formed thereon around the through hole. The chip is disposed in the through hole and includes a plurality of pads (1144) arranged thereon. The wires electrically connect the pads to the top contacts. The main adhesive is applied to a gap between the chip and the supporter and fixes the chip to the supporter. The cover plate is adhered and supported on the main adhesive. A method for making the chip package is also provided.Type: GrantFiled: April 2, 2007Date of Patent: December 29, 2009Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Cheng Wu, Chun-Hung Lin
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Patent number: 7635869Abstract: In a light emitting device, a light emitting chip (12, 112) includes a stack of semiconductor layers (14) and an electrode (24, 141, 142) disposed on the stack of semiconductor layers. A support (10, 10?, 110, 210) has a generally planar surface (30) supporting the light emitting chip in a flip-chip fashion. An electrically conductive chip attachment material (40, 41, 141, 142) is recessed into the generally planar surface of the support such that the attachment material does not protrude substantially above the generally planar surface of the support. The attachment material provides electrical communication between the electrode of the light emitting chip and an electrically conductive path (36, 36?) of the support. Optionally, at least the stack of semiconductor layers and the electrode of the light emitting chip are also recessed into the generally planar surface of the support.Type: GrantFiled: September 14, 2006Date of Patent: December 22, 2009Assignee: Lumination LLCInventors: Boris Kolodin, Michael Hsing, Stanton Earl Weaver, Jr., Ivan Eliashevich, Srinath K. Aanegola
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Publication number: 20090309241Abstract: A method for forming an ultra thin die electronic package is provided. The method includes disposing a first polymer film on a first substrate. The method also includes applying a first adhesive layer to the first polymer film on the first substrate. The method further includes disposing at least one die on the first adhesive layer on the first substrate. The method also includes disposing a second polymer film on at least one additional substrate. The method further includes applying a second adhesive layer to the second polymer film on the at least one additional substrate. The method further includes attaching the first substrate and the at least one additional substrate via the first adhesive layer and the second adhesive layer such that the at least one die is interspersed between. The method also includes forming multiple vias on at least one of a top side, and at least one of a bottom side of the first and the at least one additional substrate, wherein the multiple vias are attached to the die.Type: ApplicationFiled: June 13, 2008Publication date: December 17, 2009Applicant: GENERAL ELECTRIC COMPANYInventors: Christopher James Kapusta, Joseph Alfred Iannotti, Kevin Matthew Durocher
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Patent number: 7633169Abstract: A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps is formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.Type: GrantFiled: February 26, 2007Date of Patent: December 15, 2009Assignee: Advanced Semiconductor Engineering Inc.Inventor: Jeng-Da Wu
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Patent number: 7629695Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.Type: GrantFiled: May 19, 2005Date of Patent: December 8, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
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Patent number: 7626262Abstract: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends between the first major surface and the second major surface and electrically connects the first major surface and the second major surface.Type: GrantFiled: June 14, 2006Date of Patent: December 1, 2009Assignee: Infineon Technologies AGInventors: Ralf Otremba, Xaver Schloegel, Josef Hoeglauer, Matthias Stecher
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Patent number: 7622325Abstract: An integrated circuit package system including a high-density small footprint system-in-package with a substrate is provided. Passive components are mounted on the substrate. Solder separators are provided on the substrate, the solder separators having flattened tops at a predetermined height above the substrate. A die is supported on the solder separators above the substrate.Type: GrantFiled: October 29, 2005Date of Patent: November 24, 2009Assignee: Stats Chippac Ltd.Inventors: IL Kwon Shim, Tsz Yin Ho, Dario S. Filoteo, Jr., Seng Guan Chow
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Patent number: 7615871Abstract: A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. A quantity of adhesive material can be applied to the projection to form an attachment structure, and the adhesive material can be connected to a microelectronic substrate with the attachment structure providing no electrically conductive link between the microelectronic substrate and the support member. The microelectronic substrate and the support member can then be electrically coupled, for example, with a wire bond. In one embodiment, the projection can be formed by disposing a first material on a support member while the first material is at least partially flowable, reducing the flowability of the first material, and disposing a second material (such as the adhesive) on the first material.Type: GrantFiled: June 30, 2006Date of Patent: November 10, 2009Assignee: Micron Technology, Inc.Inventor: Tongbi Jiang
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Patent number: 7615872Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.Type: GrantFiled: December 5, 2008Date of Patent: November 10, 2009Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.Inventors: Noriyuki Takahashi, Masahiro Ichitani, Rumiko Ichitani, legal representative, Kazuhiro Ichitani, legal representative, Sachiyo Ichitani, legal representative
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Patent number: 7611926Abstract: The thermosetting die bonding film of the invention is a thermosetting die bonding film used to produce a semiconductor device, which contains, as main components, 5 to 15% by weight of a thermoplastic resin component and 45 to 55% by weight of a thermosetting resin component, and has a melt viscosity of 400 Pa·s or more and 2500 Pa·s or less at 100° C. before the film is thermally set.Type: GrantFiled: February 29, 2008Date of Patent: November 3, 2009Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Sadahito Misumi, Takeshi Matsumura, Yasuhiro Amano, Masami Oikawa, Tsubasa Miki
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Publication number: 20090261483Abstract: An adhesive composition containing: (a) a thermoplastic resin; (b) a radical-polymerizable compound including two or more (meth)acryloyl groups; (c) a curing agent that generates a radical by photoirradiation of 150 to 750 nm and/or heating at 80 to 200° C.; and (d) a liquid rubber having a viscosity of 10 to 1000 Pa·s at 25° C.Type: ApplicationFiled: June 26, 2009Publication date: October 22, 2009Applicant: HITACHI CHEMICAL CO., LTD.Inventors: Shigeki KATOGI, Hoko SUTO, Masami YUSA
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Publication number: 20090261482Abstract: A semiconductor package (20) includes an organic substrate (24) and a semiconductor die subassembly (22). A method (50) for making the semiconductor package (20) entails providing (52) the organic substrate (24) having an opening (26) and electrical contacts (36). The subassembly (22) is formed by producing (64) a semiconductor die (28) and bonding it to a platform layer (30). An elastomeric adhesive (38) is utilized (92) to secure the subassembly (22) in the opening (26). Electrical interconnects (32) are provided (106) between the semiconductor die (28) and the electrical contacts (36) of the organic substrate (24). The organic substrate (24), semiconductor die (28), elastomeric adhesive (38), and electrical interconnects (32) are encapsulated (114) in a packaging material (46). The elastomeric adhesive (38) provides mechanical anchoring of the subassembly (22) to the substrate (24) and provides mechanical stress isolation of the semiconductor die (28) within the semiconductor package (20).Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Clem H. Brown, Vasile R. Thompson
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Patent number: 7605474Abstract: A composite conductive film formed of a polymer-matrix and a plurality of conductive lines less than micro-sized and its fabricating method are provided. The conductive lines are arranged parallel and spaced apart from each other so as to provide anisotropic conductivity. The present conductive film can serve as an electrical connection between a fine-pitch chip and a substrate. Additionally, an adhesive layer is formed on two opposite sides of the conductive film along its conductive direction to increase adhesive areas. The strength and reliability of the package using the conductive film are thus enhanced.Type: GrantFiled: June 30, 2006Date of Patent: October 20, 2009Assignee: Industrial Technology Research InstituteInventors: Ruoh Huey Uang, Yu Chih Chen, Ren Jen Lin, Syh Yuh Cheng
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Patent number: 7598622Abstract: A chip module with a substrate having a top side, a chip mounted on the top side of the substrate, and an encapsulation includes an encapsulation material. The encapsulation is applied on the chip and the top side of the substrate in such a way that the chip and the top side of the substrate are at least partly covered. The encapsulation material includes a polymer composition having at least a first polymer component and a second polymer component which are chemically covalently bonded by means of a crosslinker, the first polymer component imparting resistance toward a first class of chemically reactive compounds and the second polymer component imparting resistance toward a second class of chemically reactive compounds, the reactivities differing between the first and second classes of chemically reactive compounds.Type: GrantFiled: September 12, 2006Date of Patent: October 6, 2009Assignee: Infineon Technologies AGInventor: Manfred Mengel
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Publication number: 20090236757Abstract: A semiconductor device and method for manufacturing. One embodiment includes a carrier, a structured layer arranged over the carrier and a semiconductor chip applied to the structured layer. The structured layer includes a first structure made of an elastic material and a second structure made of an adhesive material.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Manfred Mengel, Joachim Mahler
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Patent number: 7592708Abstract: With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.Type: GrantFiled: September 28, 2006Date of Patent: September 22, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung-Gu Kim, Je-Gwang Yoo, Yong-Bin Lee, Yoo-Keum Wee, Seok-Hwan Huh, Chang-Sup Ryu
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Publication number: 20090230567Abstract: A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.Type: ApplicationFiled: March 11, 2008Publication date: September 17, 2009Inventors: James Yii Lee Kiong, Chong Hin Tan, Shivaram Sahadevan, Max Mah Boon Hooi, Tang Shiau Phing
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Patent number: 7586180Abstract: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed.Type: GrantFiled: July 2, 2008Date of Patent: September 8, 2009Assignee: Renesas Technology Corp.Inventors: Toshiyuki Hata, Hiroshi Sato
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Publication number: 20090218703Abstract: A lamination tape is disclosed which includes a base film with an adhesive layer on one side wherein the coefficient of thermal expansion (CTE) of the adhesive layer is adapted so as to reduce warpage of a semiconductor die when the lamination tape is attached to the passive side of the semiconductor die.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Inventors: Soo Gil Park, Kimyung Yoon
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Patent number: 7582974Abstract: A semiconductor device that improves adhesion between a resin and a die pad and prevents cracking of the resin includes: a semiconductor chip; a die pad on which the semiconductor chip is mounted; a bonding agent for bonding the semiconductor chip to the die pad; a plurality of inner leads provided at the outer periphery of the die pad; outer leads extending from the inner leads; bonding wires connecting the inner leads to the semiconductor chip mounted on the die pad; and a resin for sealing the inner leads, the die pad, the semiconductor chip, the bonding agent and the bonding wires. The bonding agent is further disposed in all or part of a margin of the die pad at a peripheral portion where the semiconductor chip is mounted, and a plurality of dimples are formed in the surface of the bonding agent in the die pad margin.Type: GrantFiled: April 9, 2008Date of Patent: September 1, 2009Assignee: NEC Electronics CorporationInventors: Yoshiharu Kaneda, Motoaki Shimizu
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Patent number: 7579676Abstract: A leadless leadframe has a plurality of bottom leads and a plurality of top soldering pads formed in different layers. After encapsulation and before solder ball placement, a half-etching process is performed to remove the bottom leads to make the top soldering pads electrically isolated, exposed and embedded in the encapsulant for solder ball placement where the soldering area of the top soldering pads is defined without the need of solder mask(s) to solve the diffusion of solder balls on the leads during reflow.Type: GrantFiled: October 13, 2006Date of Patent: August 25, 2009Assignees: ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.Inventor: Hung-Tsun Lin
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Patent number: 7579260Abstract: A method of dividing an adhesive film for die bonding which is bonded to the rear surface of a wafer having devices in a plurality of areas sectioned by dividing lines formed in a lattice pattern on the front surface, into pieces corresponding to the devices, comprising the steps of putting the adhesive film side of the wafer on the front surface of a dicing tape mounted on an annular frame; cutting the wafer whose adhesive film side has been put on the dicing tape into devices along the dividing lines and cutting the adhesive film incompletely in such a way that an uncut portion is caused to remain; and expanding the dicing tape after the cutting step to divide the adhesive film into pieces corresponding to the devices.Type: GrantFiled: April 16, 2007Date of Patent: August 25, 2009Assignee: Disco CorporationInventor: Masaru Nakamura
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Patent number: 7573141Abstract: A semiconductor package includes a support plate made of an electrically non-conducting material. Electrical connection vias are formed outside a chip fixing region provided on the front face of the support plate. Electrical connection wires connect pads on a front of the chip to pads on the front of the support plate associated with the electrical connection vias. The front face of the support plate is further provided with at least one intermediate front layer made of a thermally conducting material extending at least partly below the chip. The rear face of the support plate is provided with at least one rear layer made of a thermally conducting material extending at least partly opposite the front layer. The front and rear layers are connected by vias made of a thermally conducting material that fills through-holes made through the plate.Type: GrantFiled: October 8, 2004Date of Patent: August 11, 2009Assignee: STMicroelectronics S.A.Inventor: Jérôme Lopez
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Patent number: 7566575Abstract: A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix are formed by solder-plating the surface of connecting terminals 12 on a mounting circuit 10. In a second step, a continuity test is performed by pressing bumps 21 against the contacts 2. In a final third step, the contacts 2 pressed are melted to connect the connecting terminals 12 to the bumps 21. That is, the semiconductor chip 20 is connected to the mounting circuit 10 while maintaining a state in which they pass the continuity test, thereby significantly reducing the occurrence of defective continuity in the semiconductor-chip-mounting circuit 1.Type: GrantFiled: July 30, 2007Date of Patent: July 28, 2009Assignee: ALPS Electric Co., Ltd.Inventor: Shinji Murata
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Patent number: 7564139Abstract: It is an object of the present invention to provide a technique for making a semiconductor device thinner without using a back-grinding method for a silicon wafer. According to the present invention, an integrated circuit film is mounted, thereby making a semiconductor device mounting the integrated circuit film thinner. The term “an integrated circuit film” means a film-like integrated circuit which is manufactured based on an integrated circuit manufactured by a semiconductor film formed over a substrate such as a glass substrate or a quartz substrate. In the present invention, the integrated circuit film is manufactured by a technique for transferring.Type: GrantFiled: November 30, 2007Date of Patent: July 21, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Kuwabara, Junya Maruyama, Yumiko Ohno, Toru Takayama, Yuugo Goto, Etsuko Arakawa, Shunpei Yamazaki
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Patent number: 7564140Abstract: A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.Type: GrantFiled: April 25, 2006Date of Patent: July 21, 2009Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Hao Lee, Yu-Po Wang, Cheng-Hsu Hsiao
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Patent number: 7563706Abstract: A material for forming an insulating film with low dielectric constant of this invention is a solution including a fine particle principally composed of a silicon atom and an oxygen atom and having a large number of pores, a resin and a solvent.Type: GrantFiled: May 10, 2007Date of Patent: July 21, 2009Assignee: Panasonic CorporationInventors: Hideo Nakagawa, Masaru Sasago
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Publication number: 20090179335Abstract: A printed circuit board (PCB) and a semiconductor package that are configured to prevent delamination and voids. In one example embodiment, the semiconductor package includes a PCB having a base substrate on which conductive patterns are formed and which includes an interior region having a die paddle for receiving a semiconductor chip and an exterior region disposed outside the interior region. The PCB also includes a first solder resist formed on a portion of the base substrate corresponding to the interior region and a second solder resist formed on a portion of the base substrate corresponding to the exterior region. The second solder resist may also have a greater surface roughness than the surface roughness of the first solder resist.Type: ApplicationFiled: November 3, 2008Publication date: July 16, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-Jin OH, Chang-Hoon HAN, Kwang-Ryul LEE, Hyoung-Suk KIM
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Patent number: 7560819Abstract: A semiconductor device, including a semiconductor chip having electrodes, a substrate having an interconnect pattern, and an adhesive, the adhesive having a first portion and a second portion, the first portion interposed between a surface of the substrate on which the interconnect pattern is formed and a surface of the semiconductor chip on which the electrodes are formed, the second portion not overlapping with the semiconductor chip. Further disclosed is the semiconductor device mounted on the circuit board and an electronic instrument having the semiconductor device.Type: GrantFiled: February 15, 2007Date of Patent: July 14, 2009Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
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Patent number: 7553701Abstract: The present invention relates to a semiconductor packaging method. The method comprises (S1) applying a die adhesive to an upper surface of a member through screen-printing; (S2) B-stage curing the member having the die adhesive; (S3) attaching a die on the B-stage cured die adhesive; (S4) wire-bonding the die to the member; and (S5) encapsulating the outside of the resultant, after the B-stage curing process of the step S2, a degree of cure of the die adhesive shows a decrease in heat capacity by 80 to 100%, and the step S3 is performed such that the die adhesive maintains an adhesive strength of 10 kgf/cm2 or more at normal temperature after the die attaching.Type: GrantFiled: August 21, 2008Date of Patent: June 30, 2009Assignee: LS Mitron Ltd.Inventors: Joon-Mo Seo, Byoung-Un Kang, Jae-Hoon Kim, Soon-Young Hyun, Ji-Eun Kim, Jun-Woo Lee, Ju-Hyuk Kim
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Patent number: 7554197Abstract: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.Type: GrantFiled: April 10, 2006Date of Patent: June 30, 2009Assignees: ChipMOS Technologies (Bermuda) Ltd, ChipMOS Technologies Inc.Inventors: Hsiang-Ming Huang, An-Hong Liu, Yeong-Jyh Lin, Yi-Chang Lee, Wu-Chang Tu, Chun-Hung Lin, Shih Feng Chiu
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Patent number: 7550318Abstract: A method is provided for forming peripheral contacts between a die and a substrate. In accordance with the method, a die (305) is provided which has first and second opposing major surfaces, wherein the first major surface is attached to a substrate (303) having a first group (323) of contact pads disposed thereon, and wherein the second major surface has a second group (311) of contact pads disposed thereon. An electrically conductive pathway (326) is formed between the first and second groups of contacts with an electrically conductive polymeric composition.Type: GrantFiled: August 11, 2006Date of Patent: June 23, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee, James W. Miller
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Publication number: 20090146320Abstract: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.Type: ApplicationFiled: January 12, 2009Publication date: June 11, 2009Applicants: The Regents of the University of California, Lewis & Clark CollegeInventors: Kellar Autumn, Ronald S. Fearing, Steven D. Jones
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Patent number: 7541667Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.Type: GrantFiled: June 17, 2005Date of Patent: June 2, 2009Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
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Patent number: 7535094Abstract: The present invention relates to a substrate structure comprising at least two substrate layers extending in substantially parallel planes, which substrate layers are (Z-)interconnected in a direction substantially perpendicular to said planes. It comprises at least one adhesive film layer for interconnecting said at least two substrate layers, said adhesive film layer(s) comprising non-conductive portions and conductive portions. The position(s) of conductive portions is controllable such as to admit positioning of conductive portions at locations in the substrate layers where electrical conductivity is needed in a direction substantially perpendicular to the planar extension of, and between, two interconnected substrate layers.Type: GrantFiled: September 14, 2005Date of Patent: May 19, 2009Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: H{dot over (a)}kan Törnqvist, Sophia Johansson, Malin Sjöberg, Klas Axelsson
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Patent number: 7535111Abstract: A semiconductor component with a semiconductor chip and an adhesive film, and a method for its production is disclosed. In one embodiment, the semiconductor component has the adhesive film, which is internally prestressed and is adhesive on both faces, between the rear face of the semiconductor chip and a chip connecting surface on a circuit mount.Type: GrantFiled: October 10, 2006Date of Patent: May 19, 2009Assignee: Infineon Technologies AGInventors: Michael Bauer, Kai Chong Chan
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Publication number: 20090108473Abstract: Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package includes a metal layer, an integrated circuit die, and an adhesive material. The metal layer has a first surface that has a die-attach region. The metal layer further has one or more recessed regions formed in the first surface of the metal layer adjacent to the die-attach region. The adhesive material attaches a first surface of the die to the die-attach region and at least partially fills the recessed region(s). Excess adhesive material flows into the recessed region(s) during application of the die to the die-attach region, so that the side surfaces of the die remain substantially uncovered by the adhesive material. By preventing the excess adhesive material from covering the side surfaces of the die, the adhesive material is prevented from penetrating the side surfaces of the die, which could damage the die.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: BROADCOM CORPORATIONInventors: Ken Jian Ming Wang, Muh-Ren Lin, Rezaur Rahman Khan
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Publication number: 20090102060Abstract: A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in the form of a ring of adhesive about a central hollow area. The wafer carrying the pattern of adhesive pads on its active surface is singulated into individual dies, each die having an adhesive pad thereon. The bottom die is attached to a base with an adhesive which cures without curing the adhesive pad.Type: ApplicationFiled: October 17, 2007Publication date: April 23, 2009Applicant: ANALOG DEVICES, INC.Inventor: Thomas M. Goida
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Patent number: 7521797Abstract: A method of manufacturing a substrate joint body by mounting a TFT on a wiring substrate includes a step of arranging an electrode pad of the wiring substrate and an electrode pad of the TFT at a predetermined interval and mechanically coupling the wiring substrate and the TFT with a adhesive and a step of electrically coupling the wiring substrate and the TFT by growing a bump from the electrode pad of the wiring substrate and/or the electrode pad of the TFT.Type: GrantFiled: March 7, 2005Date of Patent: April 21, 2009Assignee: Seiko Epson CorporationInventors: Tsuyoshi Yoda, Suguru Akagawa
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Patent number: 7518237Abstract: Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes disposing a first adhesive on a surface of a microfeature workpiece, and disposing a second adhesive on a surface of a support member. The method can further include adhesively attaching the microfeature workpiece to the support member by contacting the first adhesive with the second adhesive while the second adhesive is only partially cured. In further particular embodiments, the first and second adhesives can have different compositions, and the second adhesive can be fully cured after the microfeature workpiece and support member are adhesively attached.Type: GrantFiled: April 19, 2006Date of Patent: April 14, 2009Assignee: Micron Technology, Inc.Inventors: Craig T. Clyne, John C. Fernandez
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Patent number: 7514772Abstract: A resin layer in which adhesion to a conductive film is higher than that of a sealing resin to the conductive film is disposed on the sealing resin in which it is difficult to form the conductive film, and wiring patterns electrically connected to electronic components are disposed on the resin layer.Type: GrantFiled: April 25, 2006Date of Patent: April 7, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tomoki Kobayashi, Toshiji Shimada, Akinobu Inoue, Atsunori Kajiki, Hiroyuki Kato, Hiroshi Shimizu